Scheduling a scientific workflow onto a computational grid is considered. A computational grid can be regarded as a heterogeneous parallel machine such that the speed of each processor varies over time. A scientific workflow can be modeled as a DAG of tasks. This paper focuses on a coarse-grained workflow. So, any communication delay between tasks is negligible because computation time of every task is much longer than the corresponding communication delay. Hence, in this paper, a coarse-grained workflow grid scheduling problem (WSP for short) is defined as an extension of the classical precedence constrained scheduling problem over a uniform parallel machine with processor speed fluctuation. The objective of our problem is to minimize the makespan of a schedule. It is known that no approximation algorithm exist if a grid has a very long period with zero spare computing power. However, such situation seems to be unrealistic. This paper gives a proof that, unless P = NP, WSP is not approximable within a factor of 1.5 even if accurate performance prediction is possible, all processors have the same peak speed, and speed of every processor at any time is restricted to either 50% or 100% of the peak speed. Since the quite restricted problem is not approximable, any more general problem such that accurate performance prediction is impossible and/or processor speed fluctuation pattern is not restricted is also not approximable. So, the proof implies that WSP is not approximable within a factor of 1.5 in realistic grid environment unless P = NP.
{"title":"On Non-Approximability of Coarse-Grained Workflow Grid Scheduling","authors":"N. Fujimoto","doi":"10.1109/I-SPAN.2008.35","DOIUrl":"https://doi.org/10.1109/I-SPAN.2008.35","url":null,"abstract":"Scheduling a scientific workflow onto a computational grid is considered. A computational grid can be regarded as a heterogeneous parallel machine such that the speed of each processor varies over time. A scientific workflow can be modeled as a DAG of tasks. This paper focuses on a coarse-grained workflow. So, any communication delay between tasks is negligible because computation time of every task is much longer than the corresponding communication delay. Hence, in this paper, a coarse-grained workflow grid scheduling problem (WSP for short) is defined as an extension of the classical precedence constrained scheduling problem over a uniform parallel machine with processor speed fluctuation. The objective of our problem is to minimize the makespan of a schedule. It is known that no approximation algorithm exist if a grid has a very long period with zero spare computing power. However, such situation seems to be unrealistic. This paper gives a proof that, unless P = NP, WSP is not approximable within a factor of 1.5 even if accurate performance prediction is possible, all processors have the same peak speed, and speed of every processor at any time is restricted to either 50% or 100% of the peak speed. Since the quite restricted problem is not approximable, any more general problem such that accurate performance prediction is impossible and/or processor speed fluctuation pattern is not restricted is also not approximable. So, the proof implies that WSP is not approximable within a factor of 1.5 in realistic grid environment unless P = NP.","PeriodicalId":305776,"journal":{"name":"2008 International Symposium on Parallel Architectures, Algorithms, and Networks (i-span 2008)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115282351","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Barrier coverage, which guarantees that every movement crossing a barrier of sensors will be detected, is known to be an appropriate model of coverage for moving detection and boundary guard. The related problems about barrier coverage with stationary sensors are extensively studied. When sensors are randomly deployed, we require much more sensors to achieve barrier coverage than deterministic deployment. In this paper we study barrier coverage with mobile sensors, in which the sensors can be relocated after deployment, and we are able to utilize much fewer mobile sensors than stationary sensors to achieve barrier coverage with random deployment. We study the energy-efficient relocation problem for barrier coverage, and propose a centralized barrier algorithm, which computes the relocated positions based on knowing the initial positions of all sensors. For practicability and scalability, we further design a distributed barrier algorithm based on our proposed virtual force model. We conduct extensive simulations to study the effectiveness of the proposed algorithms.
{"title":"Barrier Coverage with Mobile Sensors","authors":"Changxiang Shen, Wei-Fang Cheng, Xiangke Liao, Shaoliang Peng","doi":"10.1109/I-SPAN.2008.8","DOIUrl":"https://doi.org/10.1109/I-SPAN.2008.8","url":null,"abstract":"Barrier coverage, which guarantees that every movement crossing a barrier of sensors will be detected, is known to be an appropriate model of coverage for moving detection and boundary guard. The related problems about barrier coverage with stationary sensors are extensively studied. When sensors are randomly deployed, we require much more sensors to achieve barrier coverage than deterministic deployment. In this paper we study barrier coverage with mobile sensors, in which the sensors can be relocated after deployment, and we are able to utilize much fewer mobile sensors than stationary sensors to achieve barrier coverage with random deployment. We study the energy-efficient relocation problem for barrier coverage, and propose a centralized barrier algorithm, which computes the relocated positions based on knowing the initial positions of all sensors. For practicability and scalability, we further design a distributed barrier algorithm based on our proposed virtual force model. We conduct extensive simulations to study the effectiveness of the proposed algorithms.","PeriodicalId":305776,"journal":{"name":"2008 International Symposium on Parallel Architectures, Algorithms, and Networks (i-span 2008)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116909377","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Queue computation model is a novel alternative for high performance architectures. Compiling for queue machines requires a different approach than compiling for traditional architectures. We have solved the problem of generating correct code with the queue compiler infrastructure. In this paper we introduce some problems encountered when optimizing code for queue machines. Common-subexpression elimination (CSE) is a widely used optimization to improve execution time. This paper makes a quantitative evaluation of how this optimization affects the characteristics of queue programs. We have found that in average, 28% of instructions are eliminated, and 15% of the critical path is reduced. We determine how enlarging the scope of compilation from expressions to basic blocks affects the distribution of offsetted instructions.
{"title":"Quantitative Evaluation of Common Subexpression Elimination on Queue Machines","authors":"A. Canedo, M. Sowa, B. Abderazek","doi":"10.1109/I-SPAN.2008.25","DOIUrl":"https://doi.org/10.1109/I-SPAN.2008.25","url":null,"abstract":"Queue computation model is a novel alternative for high performance architectures. Compiling for queue machines requires a different approach than compiling for traditional architectures. We have solved the problem of generating correct code with the queue compiler infrastructure. In this paper we introduce some problems encountered when optimizing code for queue machines. Common-subexpression elimination (CSE) is a widely used optimization to improve execution time. This paper makes a quantitative evaluation of how this optimization affects the characteristics of queue programs. We have found that in average, 28% of instructions are eliminated, and 15% of the critical path is reduced. We determine how enlarging the scope of compilation from expressions to basic blocks affects the distribution of offsetted instructions.","PeriodicalId":305776,"journal":{"name":"2008 International Symposium on Parallel Architectures, Algorithms, and Networks (i-span 2008)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115032888","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The science of haptics has received enormous attention in the last decade. One of the major application trends of haptics technology is data visualization and training. In this paper, we present our work towards developing a haptically enabled model for the structure of DNA. The graphic model of the DNA strand is made up of individual base pair models. The environment presents two views of the model: a global view that reflects the real stretching forces for a 5000 base pair strand and a 40 base pair portion of the strand to display the twisting of the molecules. The addition of the haptic model enables users to feel the stretching and twisting forces while manipulating the model through the PHANTOMreg Desktop haptic device. Since the interaction forces are in the piconewton range, the forces applied by/to the user are scaled accordingly. The model can serve as a good instructional aid for helping users to understand the molecular structure of DNA through effective visual representation and interactive manipulation. In incorporating more physical details, it may also have a future use in simulating protein and enzyme interactions with DNA.
{"title":"A Haptic Enabled DNA Model Sensing","authors":"Dan Martin, M. Eid, Abdulmotaleb El Saddik","doi":"10.1109/I-SPAN.2008.47","DOIUrl":"https://doi.org/10.1109/I-SPAN.2008.47","url":null,"abstract":"The science of haptics has received enormous attention in the last decade. One of the major application trends of haptics technology is data visualization and training. In this paper, we present our work towards developing a haptically enabled model for the structure of DNA. The graphic model of the DNA strand is made up of individual base pair models. The environment presents two views of the model: a global view that reflects the real stretching forces for a 5000 base pair strand and a 40 base pair portion of the strand to display the twisting of the molecules. The addition of the haptic model enables users to feel the stretching and twisting forces while manipulating the model through the PHANTOMreg Desktop haptic device. Since the interaction forces are in the piconewton range, the forces applied by/to the user are scaled accordingly. The model can serve as a good instructional aid for helping users to understand the molecular structure of DNA through effective visual representation and interactive manipulation. In incorporating more physical details, it may also have a future use in simulating protein and enzyme interactions with DNA.","PeriodicalId":305776,"journal":{"name":"2008 International Symposium on Parallel Architectures, Algorithms, and Networks (i-span 2008)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128566238","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Fahimeh Jafari, M. S. Talebi, A. Khonsari, M. Moghaddam
With the advances of the semiconductor technology, the enormous number of transistors available on a single chip allows designers to integrate dozens of IP blocks together with large amounts of embedded memory. This has been led to the concept of network on a chip (NoC), in which different modules would be connected by a simple network of shared links and routers and is considered as a solution to replace traditional bus-based architectures to address the global communication challenges in nanoscale technologies. In NoC architectures, controlling congestion of the best effort traffic will continue to be an important design goal. Towards this, employing end-to-end congestion control is becoming more imminent in the design process of NoCs. In this paper, we introduce a centralized algorithm based on the delay minimization of best effort sources. The proposed algorithm can be used as a mechanism to control the flow of best effort source rates by which the sum of propagation delays of network is to be minimized.
{"title":"A Novel Congestion Control Scheme in Network-on-Chip Based on Best Effort Delay-Sum Optimization","authors":"Fahimeh Jafari, M. S. Talebi, A. Khonsari, M. Moghaddam","doi":"10.1109/I-SPAN.2008.45","DOIUrl":"https://doi.org/10.1109/I-SPAN.2008.45","url":null,"abstract":"With the advances of the semiconductor technology, the enormous number of transistors available on a single chip allows designers to integrate dozens of IP blocks together with large amounts of embedded memory. This has been led to the concept of network on a chip (NoC), in which different modules would be connected by a simple network of shared links and routers and is considered as a solution to replace traditional bus-based architectures to address the global communication challenges in nanoscale technologies. In NoC architectures, controlling congestion of the best effort traffic will continue to be an important design goal. Towards this, employing end-to-end congestion control is becoming more imminent in the design process of NoCs. In this paper, we introduce a centralized algorithm based on the delay minimization of best effort sources. The proposed algorithm can be used as a mechanism to control the flow of best effort source rates by which the sum of propagation delays of network is to be minimized.","PeriodicalId":305776,"journal":{"name":"2008 International Symposium on Parallel Architectures, Algorithms, and Networks (i-span 2008)","volume":"30 20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114334754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-05-07DOI: 10.1142/S0219265909002595
B. Bensaou, Z. Kong, D. Tsang
The enhanced distributed channel access (EDCA) is designed to provide differentiated services without real performance guarantees such as hard bandwidth and delay bounds in the IEEE 802.11e based wireless LANs. In this paper we design a measurement-assisted, model-based call admission control (MM- CAC) scheme to support guaranteed QoS in the EDCA. For this purpose, we first develop a novel analytical model of the legacy IEEE 802.11 DCF under non-saturation conditions; then using this model, we define the concept of equivalent number of competing entities, to convert a heterogeneous (multi-class) EDCA network into an equivalent homogeneous network. Our analytical model is then invoked to decide to admit a new flow or reject it with much little computational complexity as compared to a fully fledged EDCA model. Numerical results validate our model and analysis, and simulations demonstrate the effectiveness of our MM-CAC scheme.
{"title":"A Measurement-Assisted, Model-Based Admission Control Algorithm for IEEE 802.11e","authors":"B. Bensaou, Z. Kong, D. Tsang","doi":"10.1142/S0219265909002595","DOIUrl":"https://doi.org/10.1142/S0219265909002595","url":null,"abstract":"The enhanced distributed channel access (EDCA) is designed to provide differentiated services without real performance guarantees such as hard bandwidth and delay bounds in the IEEE 802.11e based wireless LANs. In this paper we design a measurement-assisted, model-based call admission control (MM- CAC) scheme to support guaranteed QoS in the EDCA. For this purpose, we first develop a novel analytical model of the legacy IEEE 802.11 DCF under non-saturation conditions; then using this model, we define the concept of equivalent number of competing entities, to convert a heterogeneous (multi-class) EDCA network into an equivalent homogeneous network. Our analytical model is then invoked to decide to admit a new flow or reject it with much little computational complexity as compared to a fully fledged EDCA model. Numerical results validate our model and analysis, and simulations demonstrate the effectiveness of our MM-CAC scheme.","PeriodicalId":305776,"journal":{"name":"2008 International Symposium on Parallel Architectures, Algorithms, and Networks (i-span 2008)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130476168","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In large systems, economical and efficiency concerns restrict the allocation of each resource to every node in the network. Therefore, it is desirable to distribute copies of resource in order to share them and achieve a certain performance measure. In this paper, we consider the problem of distributing resources in Cube-Connected Cycles. Both adjacency and distant placements are considered in this paper. In adjacency placements, dominating sets and perfect dominating sets are used. The proposed algorithms for distant placements use known placements for basic hypercube graphs. Therefore, in these placements we avoid the additional costs needed for deploying the network. We prove that the presented algorithms provide an optimum result for Cube-Connected Cycles.
{"title":"Resource Placement in Cube-Connected Cycles","authors":"Paria Moinzadeh, H. Sarbazi-Azad, N. Yazdani","doi":"10.1109/I-SPAN.2008.36","DOIUrl":"https://doi.org/10.1109/I-SPAN.2008.36","url":null,"abstract":"In large systems, economical and efficiency concerns restrict the allocation of each resource to every node in the network. Therefore, it is desirable to distribute copies of resource in order to share them and achieve a certain performance measure. In this paper, we consider the problem of distributing resources in Cube-Connected Cycles. Both adjacency and distant placements are considered in this paper. In adjacency placements, dominating sets and perfect dominating sets are used. The proposed algorithms for distant placements use known placements for basic hypercube graphs. Therefore, in these placements we avoid the additional costs needed for deploying the network. We prove that the presented algorithms provide an optimum result for Cube-Connected Cycles.","PeriodicalId":305776,"journal":{"name":"2008 International Symposium on Parallel Architectures, Algorithms, and Networks (i-span 2008)","volume":"49 12","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121011697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Due to bandwidth constraint and highly dynamic topology of mobile ad hoc networks, supporting quality of service (QoS) is a challenging task. In this paper, we present two efficient route recovery mechanisms for QoS routing based on an extension of the AODV (ad hoc on demand distance vector) routing protocol that deals with delay and bandwidth constraints. One is based on route maintenance by intermediate node using a special local route repair mechanism and the other one is route maintenance by the destination node. Our methods reduce control overhead and delay incurred while following the traditional approach of route recovery. The simulation results reveal the performance improvements in terms of control overhead, end-to-end delivery ratio and connection setup latency.
由于移动自组织网络的带宽限制和高度动态的拓扑结构，支持服务质量(QoS)是一项具有挑战性的任务。在本文中，我们基于AODV (ad hoc on demand distance vector)路由协议的扩展，提出了两种有效的路由恢复机制，用于处理延迟和带宽约束。一种是基于中间节点的路由维护，采用特殊的本地路由修复机制;另一种是基于目的节点的路由维护。我们的方法减少了传统路由恢复方法所带来的控制开销和延迟。仿真结果显示了在控制开销、端到端传输比和连接建立延迟方面的性能改进。
{"title":"Enhancing Route Recovery for QAODV Routing in Mobile Ad Hoc Networks","authors":"N. Sarma, Sukumar Nandi, R. Tripathi","doi":"10.1109/I-SPAN.2008.31","DOIUrl":"https://doi.org/10.1109/I-SPAN.2008.31","url":null,"abstract":"Due to bandwidth constraint and highly dynamic topology of mobile ad hoc networks, supporting quality of service (QoS) is a challenging task. In this paper, we present two efficient route recovery mechanisms for QoS routing based on an extension of the AODV (ad hoc on demand distance vector) routing protocol that deals with delay and bandwidth constraints. One is based on route maintenance by intermediate node using a special local route repair mechanism and the other one is route maintenance by the destination node. Our methods reduce control overhead and delay incurred while following the traditional approach of route recovery. The simulation results reveal the performance improvements in terms of control overhead, end-to-end delivery ratio and connection setup latency.","PeriodicalId":305776,"journal":{"name":"2008 International Symposium on Parallel Architectures, Algorithms, and Networks (i-span 2008)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132527588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Akbar Sharifi, R. Sabbaghi‐Nadooshan, H. Sarbazi-Azad
Nowadays networks-on-chip are emerging as a hot topic in IC designs with high integration. In addition to popular mesh and torus topologies, other structures can also be considered especially in 3D VLSI design. The shuffle-exchange topology is one of the popular interconnection architectures for multiprocessors due to its scalability and self-routing capability. By vertically stacking two or more silicon wafers, connected with a high-density and high-speed interconnect, it is now possible to combine multiple active device layers within a single IC. In this paper we propose an efficient three dimensional layout for a novel 2D mesh structure based on the shuffle-exchange topology. Simulation results show that by using the third dimension, performance and latency can be improved compared to the 2D VLSI implementation.
{"title":"The Shuffle-Exchange Mesh Topology for 3D NoCs","authors":"Akbar Sharifi, R. Sabbaghi‐Nadooshan, H. Sarbazi-Azad","doi":"10.1109/I-SPAN.2008.23","DOIUrl":"https://doi.org/10.1109/I-SPAN.2008.23","url":null,"abstract":"Nowadays networks-on-chip are emerging as a hot topic in IC designs with high integration. In addition to popular mesh and torus topologies, other structures can also be considered especially in 3D VLSI design. The shuffle-exchange topology is one of the popular interconnection architectures for multiprocessors due to its scalability and self-routing capability. By vertically stacking two or more silicon wafers, connected with a high-density and high-speed interconnect, it is now possible to combine multiple active device layers within a single IC. In this paper we propose an efficient three dimensional layout for a novel 2D mesh structure based on the shuffle-exchange topology. Simulation results show that by using the third dimension, performance and latency can be improved compared to the 2D VLSI implementation.","PeriodicalId":305776,"journal":{"name":"2008 International Symposium on Parallel Architectures, Algorithms, and Networks (i-span 2008)","volume":"378 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123898525","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In wireless sensor networks, almost all geographic routing algorithms assume that sensors are accurately located. In this paper, we propose an energy efficient geographic routing algorithm (EEG-Routing). In our method, before the deployment of sensors in their environment, sensor positions are known with position error bounds which are potentially larges. According to this knowledge, it is possible to compute, before the deployment the probability that two sensors communicate. EEG-Routing introduces a new metric which defines, regarding to communication probabilities, energy consumptions and realized progress, communication costs between neighbors. EEG-Routing simultaneously optimizes two criteria: the energy consumption and the delivery rate, in networks where sensors are inaccurately located. Performances are validated by simulations which compare EEG-Routing with an energy-optimal algorithm.
{"title":"An Energy-Efficient Geographic Routing with Location Errors in Wireless Sensor Networks","authors":"Julien Champ, C. Saad","doi":"10.1109/I-SPAN.2008.49","DOIUrl":"https://doi.org/10.1109/I-SPAN.2008.49","url":null,"abstract":"In wireless sensor networks, almost all geographic routing algorithms assume that sensors are accurately located. In this paper, we propose an energy efficient geographic routing algorithm (EEG-Routing). In our method, before the deployment of sensors in their environment, sensor positions are known with position error bounds which are potentially larges. According to this knowledge, it is possible to compute, before the deployment the probability that two sensors communicate. EEG-Routing introduces a new metric which defines, regarding to communication probabilities, energy consumptions and realized progress, communication costs between neighbors. EEG-Routing simultaneously optimizes two criteria: the energy consumption and the delivery rate, in networks where sensors are inaccurately located. Performances are validated by simulations which compare EEG-Routing with an energy-optimal algorithm.","PeriodicalId":305776,"journal":{"name":"2008 International Symposium on Parallel Architectures, Algorithms, and Networks (i-span 2008)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-05-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129409197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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