Pub Date : 2012-09-30DOI: 10.1109/ICCD.2012.6378623
Yu Cai, Gulay Yalcin, O. Mutlu, E. Haratsch, A. Cristal, O. Unsal, K. Mai
With the continued scaling of NAND flash and multi-level cell technology, flash-based storage has gained widespread use in systems ranging from mobile platforms to enterprise servers. However, the robustness of NAND flash cells is an increasing concern, especially at nanometer-regime process geometries. NAND flash memory bit error rate increases exponentially with the number of program/erase cycles. Stronger error correcting codes (ECC) can be used to tolerate higher error rates, but these have diminishing returns with increasing P/E cycles and can have prohibitively high power, area, and latency overheads. The goal of this paper is to develop new techniques that can tolerate high bit error rates without requiring prohibitively strong ECC. Our techniques, called Flash Correct-and-Refresh (FCR) exploit the observation that the dominant error source in NAND flash memory is retention errors, caused by flash cells losing charge over time. The key idea is to periodically read, correct, and reprogram (in-place) or remap the stored data before it accumulates more retention errors than can be corrected by simple ECC. Detailed simulations of a solid-state drive (SSD) storage system driven by measured experimental data from error characterization on real flash memory chips show that our techniques provide 46× average lifetime improvement on a variety of workloads at no additional hardware cost. We also find that our techniques achieve lifetime improvements that cannot feasibly be achieved with stronger ECC.
{"title":"Flash correct-and-refresh: Retention-aware error management for increased flash memory lifetime","authors":"Yu Cai, Gulay Yalcin, O. Mutlu, E. Haratsch, A. Cristal, O. Unsal, K. Mai","doi":"10.1109/ICCD.2012.6378623","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378623","url":null,"abstract":"With the continued scaling of NAND flash and multi-level cell technology, flash-based storage has gained widespread use in systems ranging from mobile platforms to enterprise servers. However, the robustness of NAND flash cells is an increasing concern, especially at nanometer-regime process geometries. NAND flash memory bit error rate increases exponentially with the number of program/erase cycles. Stronger error correcting codes (ECC) can be used to tolerate higher error rates, but these have diminishing returns with increasing P/E cycles and can have prohibitively high power, area, and latency overheads. The goal of this paper is to develop new techniques that can tolerate high bit error rates without requiring prohibitively strong ECC. Our techniques, called Flash Correct-and-Refresh (FCR) exploit the observation that the dominant error source in NAND flash memory is retention errors, caused by flash cells losing charge over time. The key idea is to periodically read, correct, and reprogram (in-place) or remap the stored data before it accumulates more retention errors than can be corrected by simple ECC. Detailed simulations of a solid-state drive (SSD) storage system driven by measured experimental data from error characterization on real flash memory chips show that our techniques provide 46× average lifetime improvement on a variety of workloads at no additional hardware cost. We also find that our techniques achieve lifetime improvements that cannot feasibly be achieved with stronger ECC.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123930233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-30DOI: 10.1109/ICCD.2012.6378641
Can Sitik, B. Taskin
This paper investigates the effectiveness of a multi-voltage clock network design that is built using the mesh topology. Unlike a clock tree, a single clock mesh that spans multiple voltage domains is infeasible due to the incompatibility of voltage levels of the clock drivers on the electrically-shorted mesh - each voltage domain requires a separate mesh. These disjoint meshes need to be matched in clock skew between the domains. In addition, the additional power dissipation of the level shifters in the logic needs to be compared against the power savings of multi-voltage domain implementation. The case study performed with the largest ISCAS'89 benchmark circuits operating at 500 MHz, 90 nm technology concludes two important results that highlight the benefits of multi-voltage clock mesh design: 1) The multi-voltage domain clock mesh can achieve 37.14% lower power with a 9 ps increase in clock skew over the single-voltage domain clock mesh, and 2) The multi-voltage domain clock mesh achieves 66 ps less skew with a 20.92% increase in power dissipation over a multi-voltage domain clock tree.
{"title":"Multi-voltage domain clock mesh design","authors":"Can Sitik, B. Taskin","doi":"10.1109/ICCD.2012.6378641","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378641","url":null,"abstract":"This paper investigates the effectiveness of a multi-voltage clock network design that is built using the mesh topology. Unlike a clock tree, a single clock mesh that spans multiple voltage domains is infeasible due to the incompatibility of voltage levels of the clock drivers on the electrically-shorted mesh - each voltage domain requires a separate mesh. These disjoint meshes need to be matched in clock skew between the domains. In addition, the additional power dissipation of the level shifters in the logic needs to be compared against the power savings of multi-voltage domain implementation. The case study performed with the largest ISCAS'89 benchmark circuits operating at 500 MHz, 90 nm technology concludes two important results that highlight the benefits of multi-voltage clock mesh design: 1) The multi-voltage domain clock mesh can achieve 37.14% lower power with a 9 ps increase in clock skew over the single-voltage domain clock mesh, and 2) The multi-voltage domain clock mesh achieves 66 ps less skew with a 20.92% increase in power dissipation over a multi-voltage domain clock tree.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129155036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-30DOI: 10.1109/ICCD.2012.6378607
J. Torrellas
For conventional memory use, this design improves bandwidth, latency and energy characteristics - without changing the high-volume DRAM design. However, it is easy to imagine how to augment the capabilities of the logic die to support Intelligent Memory Operations. These can consist of preprocessing the data as it is read from the DRAM stack into the processor chip. They can also involve performing operations in place on the DRAM data.
{"title":"FlexRAM: Toward an advanced Intelligent Memory system: A retrospective paper","authors":"J. Torrellas","doi":"10.1109/ICCD.2012.6378607","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378607","url":null,"abstract":"For conventional memory use, this design improves bandwidth, latency and energy characteristics - without changing the high-volume DRAM design. However, it is easy to imagine how to augment the capabilities of the logic die to support Intelligent Memory Operations. These can consist of preprocessing the data as it is read from the DRAM stack into the processor chip. They can also involve performing operations in place on the DRAM data.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129366198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-30DOI: 10.1109/ICCD.2012.6378694
Ahmad Lashgar, A. Baniasadi, A. Khonsari
Modern GPUs synchronize threads grouped in warps. The number of threads included in each warp (or warp size) affects divergence, synchronization overhead, and the efficiency of memory access coalescing. Small warps reduce the performance penalty associated with branch and memory divergence at the expense of a reduction in memory coalescing. Large warps enhance memory coalescing significantly but also increase branch and memory divergence. Dynamic workload behavior, including branch/memory divergence and coalescing, is an important factor in determining the warp size returning best performance. Based on this observation, we propose Dynamic Warp Resizing (DWR). DWR outperforms static warp size decisions, up to 2.28X.
{"title":"Dynamic warp resizing: Analysis and benefits in high-performance SIMT","authors":"Ahmad Lashgar, A. Baniasadi, A. Khonsari","doi":"10.1109/ICCD.2012.6378694","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378694","url":null,"abstract":"Modern GPUs synchronize threads grouped in warps. The number of threads included in each warp (or warp size) affects divergence, synchronization overhead, and the efficiency of memory access coalescing. Small warps reduce the performance penalty associated with branch and memory divergence at the expense of a reduction in memory coalescing. Large warps enhance memory coalescing significantly but also increase branch and memory divergence. Dynamic workload behavior, including branch/memory divergence and coalescing, is an important factor in determining the warp size returning best performance. Based on this observation, we propose Dynamic Warp Resizing (DWR). DWR outperforms static warp size decisions, up to 2.28X.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114795198","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-30DOI: 10.1109/ICCD.2012.6378643
Chengguang Ma, Shun'an Zhong, H. Dang
Stochastic arithmetic provide several benefits over traditional computing method such as high fault tolerance, simple hardware implementation, low hardware area. In order to increase accuracy of error analysis and improve method of performance evaluation for stochastic computing systems, a new variance transfer function for stochastic computing systems based on combinational logic is proposed in this work. The transfer function is proved by a new mathematical method: hypergeometric decomposition, which makes stochastic computing theory more perfect and reliable. According to the variance transfer function, several measurements based on variance are developed to evaluate performance between different stochastic computing algorithms. By comparing this method with traditional bit-level simulation method, variance measurements are proved to be less time consumption, more comprehensive, and more effective to evaluate and understand stochastic computing systems.
{"title":"Understanding variance propagation in stochastic computing systems","authors":"Chengguang Ma, Shun'an Zhong, H. Dang","doi":"10.1109/ICCD.2012.6378643","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378643","url":null,"abstract":"Stochastic arithmetic provide several benefits over traditional computing method such as high fault tolerance, simple hardware implementation, low hardware area. In order to increase accuracy of error analysis and improve method of performance evaluation for stochastic computing systems, a new variance transfer function for stochastic computing systems based on combinational logic is proposed in this work. The transfer function is proved by a new mathematical method: hypergeometric decomposition, which makes stochastic computing theory more perfect and reliable. According to the variance transfer function, several measurements based on variance are developed to evaluate performance between different stochastic computing algorithms. By comparing this method with traditional bit-level simulation method, variance measurements are proved to be less time consumption, more comprehensive, and more effective to evaluate and understand stochastic computing systems.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127430601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-30DOI: 10.1109/ICCD.2012.6378649
Firas Hawi, M. Sawan
In this paper, we design, evaluate and compare two phase-based passive stereovision architectures. We present two approaches to implement phase-based correspondence search algorithms in real-time for sparse stereovision applications. The first approach enhances the accuracy of the 1D phase correlation method. The second approach optimizes the 2D phase correlation method at the cost of degradation in disparity estimation accuracy. We report experimental results that encourage the use of the proposed systems in a 3D imaging device dedicated to cover vision for blinds through cortical visual stimulation. FPGA implementation running at 200 fps is described.
{"title":"Phase-based passive stereovision systems dedicated to cortical visual stimulators","authors":"Firas Hawi, M. Sawan","doi":"10.1109/ICCD.2012.6378649","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378649","url":null,"abstract":"In this paper, we design, evaluate and compare two phase-based passive stereovision architectures. We present two approaches to implement phase-based correspondence search algorithms in real-time for sparse stereovision applications. The first approach enhances the accuracy of the 1D phase correlation method. The second approach optimizes the 2D phase correlation method at the cost of degradation in disparity estimation accuracy. We report experimental results that encourage the use of the proposed systems in a 3D imaging device dedicated to cover vision for blinds through cortical visual stimulation. FPGA implementation running at 200 fps is described.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124524120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-30DOI: 10.1109/ICCD.2012.6378628
D. Hély, Maurin Augagneur, Y. Clauzel, Jeremy Dubeuf
In this work, we propose a hardware Trojan within a given encryption platform. This malicious hardware aims at leaking the secret key used for encryption without perturbing the system so that the user does not notice it. We propose a hardware Trojan which detects any new encryption start and then transmit the used expended key on the system serial link. This hardware Trojan does not require any processor modification. The paper presents the way the hardware Trojan has been developed according the given platform and the associated information. This work has been developed by Grenoble INP students (M. Augagneur, Y. Clauzel and J. Dubeuf) during the secure IC design labs of the Grenoble INP Esisar and was then presented for the Embedded System Challenge during the Cyber Security Awareness Week (CSAW) 2011 organized by Polytechnic Institute of New York University.
在这项工作中，我们提出了一个硬件木马在给定的加密平台。这种恶意硬件的目的是在不干扰系统的情况下泄露用于加密的密钥，这样用户就不会注意到它。我们提出了一种硬件木马，它可以检测到任何新的加密启动，然后在系统串行链路上传输使用的扩展密钥。这个硬件木马不需要任何处理器修改。本文介绍了基于给定平台和相关信息的硬件木马的开发方法。这项工作是由格勒诺布尔INP学生(M. Augagneur, Y. Clauzel和J. Dubeuf)在格勒诺布尔INP Esisar的安全IC设计实验室中开发的，然后在2011年由纽约大学理工学院组织的网络安全意识周(CSAW)期间提出嵌入式系统挑战。
{"title":"Malicious key emission via hardware Trojan against encryption system","authors":"D. Hély, Maurin Augagneur, Y. Clauzel, Jeremy Dubeuf","doi":"10.1109/ICCD.2012.6378628","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378628","url":null,"abstract":"In this work, we propose a hardware Trojan within a given encryption platform. This malicious hardware aims at leaking the secret key used for encryption without perturbing the system so that the user does not notice it. We propose a hardware Trojan which detects any new encryption start and then transmit the used expended key on the system serial link. This hardware Trojan does not require any processor modification. The paper presents the way the hardware Trojan has been developed according the given platform and the associated information. This work has been developed by Grenoble INP students (M. Augagneur, Y. Clauzel and J. Dubeuf) during the secure IC design labs of the Grenoble INP Esisar and was then presented for the Embedded System Challenge during the Cyber Security Awareness Week (CSAW) 2011 organized by Polytechnic Institute of New York University.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121845908","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-30DOI: 10.1109/ICCD.2012.6378677
Atena Roshan Fekr, Majid Janidarmian, O. Sarbishei, Benjamin Nahill, K. Radecka, Z. Zilic
Multi-sensor data fusion is an efficient method to provide both accurate and fault-tolerant sensor readouts. Furthermore, detection of faults in a reasonably short amount of time is crucial for applications dealing with high risks. In order to deliver high accuracies for the sensor measurements, it is required to perform a calibration for each sensor. This paper focuses on designing a fault-tolerant calibrated multisensor system. First, the least squares method is applied to calibrate each sensor using a linear curve fitting function. Next, an analytical technique is proposed to carry out a fault-tolerant multi-sensor data fusion, while minimizing the Mean-Square-Error (MSE) for the final sensor readout. While our data fusion approach is applicable to different multi-sensor systems, the experimental results are shown for 16 temperature sensors, where an environmental thermal chamber was used as the reference model to calibrate the sensors and perform the measurements.
{"title":"MSE minimization and fault-tolerant data fusion for multi-sensor systems","authors":"Atena Roshan Fekr, Majid Janidarmian, O. Sarbishei, Benjamin Nahill, K. Radecka, Z. Zilic","doi":"10.1109/ICCD.2012.6378677","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378677","url":null,"abstract":"Multi-sensor data fusion is an efficient method to provide both accurate and fault-tolerant sensor readouts. Furthermore, detection of faults in a reasonably short amount of time is crucial for applications dealing with high risks. In order to deliver high accuracies for the sensor measurements, it is required to perform a calibration for each sensor. This paper focuses on designing a fault-tolerant calibrated multisensor system. First, the least squares method is applied to calibrate each sensor using a linear curve fitting function. Next, an analytical technique is proposed to carry out a fault-tolerant multi-sensor data fusion, while minimizing the Mean-Square-Error (MSE) for the final sensor readout. While our data fusion approach is applicable to different multi-sensor systems, the experimental results are shown for 16 temperature sensors, where an environmental thermal chamber was used as the reference model to calibrate the sensors and perform the measurements.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121883025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-30DOI: 10.1109/ICCD.2012.6378662
Saurabh Kothawade, D. Ancajas, Koushik Chakraborty, Sanghamitra Roy
Degradation of transistor parameter values due to Negative Bias Temperature Instability (NBTI) has emerged as a major reliability problem in current and future transistor generations. NBTI Aging of SRAM cell leads to a lower noise margin, thereby increasing the failure rate. The physical register file, which consists of an array of SRAM cells, can suffer from data loss, leading to system failure. In this paper, we explore a novel approach by investigating NBTI stress and mitigation at the instruction granularity. While a wide range of NBTI stress exists in different registers, the stress induced by specific instructions is highly predictable. Using such a prediction mechanism, we propose an NBTI tolerant power efficient physical register file design. Our approach improves the noise margin in a register file by 20%, 32%, and 125% for the 45nm, 32nm, and 22nm technology nodes, respectively. Overall, we observe 14.8% power saving and a 19.8% area penalty in the register file.
{"title":"Mitigating NBTI in the physical register file through stress prediction","authors":"Saurabh Kothawade, D. Ancajas, Koushik Chakraborty, Sanghamitra Roy","doi":"10.1109/ICCD.2012.6378662","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378662","url":null,"abstract":"Degradation of transistor parameter values due to Negative Bias Temperature Instability (NBTI) has emerged as a major reliability problem in current and future transistor generations. NBTI Aging of SRAM cell leads to a lower noise margin, thereby increasing the failure rate. The physical register file, which consists of an array of SRAM cells, can suffer from data loss, leading to system failure. In this paper, we explore a novel approach by investigating NBTI stress and mitigation at the instruction granularity. While a wide range of NBTI stress exists in different registers, the stress induced by specific instructions is highly predictable. Using such a prediction mechanism, we propose an NBTI tolerant power efficient physical register file design. Our approach improves the noise margin in a register file by 20%, 32%, and 125% for the 45nm, 32nm, and 22nm technology nodes, respectively. Overall, we observe 14.8% power saving and a 19.8% area penalty in the register file.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123481222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-30DOI: 10.1109/ICCD.2012.6378611
K. Kant, R. Iyer, P. Mohapatra
Secure socket layer (SSL) is the most popular protocol used in the Internet for facilitating secure communications. In this paper, we analyze the performance and architectural impact of SSL on the servers in terms of various parameters such as throughput, utilization, cache sizes, cache miss ratios, number of processors, control dependencies, file access sizes, bus transactions, network load, etc. The major conclusions from this study are as follows: The use of SSL increases computational cost of the transactions by a factor of 5-7. SSL transactions do not benefit much from a larger L2 cache, but a larger LI cache would be helpful. A complex logic for handling control dependencies is not useful for SSL transaction as the frequency of branches is very low. Because SSL workload is highly CPU bound, it may be possible to enhance SSL performance by using a number of other architectural features as well.
{"title":"Architectural impact of secure socket layer on Internet servers","authors":"K. Kant, R. Iyer, P. Mohapatra","doi":"10.1109/ICCD.2012.6378611","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378611","url":null,"abstract":"Secure socket layer (SSL) is the most popular protocol used in the Internet for facilitating secure communications. In this paper, we analyze the performance and architectural impact of SSL on the servers in terms of various parameters such as throughput, utilization, cache sizes, cache miss ratios, number of processors, control dependencies, file access sizes, bus transactions, network load, etc. The major conclusions from this study are as follows: The use of SSL increases computational cost of the transactions by a factor of 5-7. SSL transactions do not benefit much from a larger L2 cache, but a larger LI cache would be helpful. A complex logic for handling control dependencies is not useful for SSL transaction as the frequency of branches is very low. Because SSL workload is highly CPU bound, it may be possible to enhance SSL performance by using a number of other architectural features as well.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131675733","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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