Pub Date : 2012-09-30DOI: 10.1109/ICCD.2012.6378667
Amer Qouneh, Zhongqi Li, Madhura Joshi, Wangyuan Zhang, Xin Fu, Tao Li
With silicon optical technology moving towards maturity, the use of photonic network-on-chip (NoCs) for global chip communication is emerging as a promising solution to communication requirements of future many core processors. It is expected that photonic NoCs will play an important role in alleviating current power, latency, and bandwidth constraints. However, photonic NoCs are sensitive to ambient temperature variations because their basic constituents, ring resonators, are themselves sensitive to those variations. Since ring resonators are basic building blocks for photonic modulators, switches, multiplexers, and demultiplexers, variations of on-chip temperature pose serious challenges to the proper operation of photonic NoCs. Proposed methods that mitigate the effects of temperature at device level are either difficult to use in CMOS processes or not suitable for large scale implementation. In this paper, we propose Aurora, a thermally resilient photonic NoC architecture design that supports reliable and low bit error rate (BER) on-chip communications in the presence of large temperature variations. Our proposed architecture leverages solutions at both device and architecture layers that synergistically provide significant improvements. To compensate for small temperature variations, our design varies the bias current through ring resonators. For larger temperature variations, we propose architecture-level techniques to re-route messages away from hot regions, and through cooler regions, to their destinations, thereby lowering BER. Our simulation results show that Aurora provides a robust architectural solution to handle temperature variation effects on future photonic NoCs. For instance, average BER and message error rate (MER) are reduced by 78% and 30% respectively when the combined device and architectural technique (SPF) is applied. From the perspective of power efficiency, Aurora is also superior to conventional photonic NoC architectures by as much as 33%.
{"title":"Aurora: A thermally resilient photonic network-on-chip architecture","authors":"Amer Qouneh, Zhongqi Li, Madhura Joshi, Wangyuan Zhang, Xin Fu, Tao Li","doi":"10.1109/ICCD.2012.6378667","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378667","url":null,"abstract":"With silicon optical technology moving towards maturity, the use of photonic network-on-chip (NoCs) for global chip communication is emerging as a promising solution to communication requirements of future many core processors. It is expected that photonic NoCs will play an important role in alleviating current power, latency, and bandwidth constraints. However, photonic NoCs are sensitive to ambient temperature variations because their basic constituents, ring resonators, are themselves sensitive to those variations. Since ring resonators are basic building blocks for photonic modulators, switches, multiplexers, and demultiplexers, variations of on-chip temperature pose serious challenges to the proper operation of photonic NoCs. Proposed methods that mitigate the effects of temperature at device level are either difficult to use in CMOS processes or not suitable for large scale implementation. In this paper, we propose Aurora, a thermally resilient photonic NoC architecture design that supports reliable and low bit error rate (BER) on-chip communications in the presence of large temperature variations. Our proposed architecture leverages solutions at both device and architecture layers that synergistically provide significant improvements. To compensate for small temperature variations, our design varies the bias current through ring resonators. For larger temperature variations, we propose architecture-level techniques to re-route messages away from hot regions, and through cooler regions, to their destinations, thereby lowering BER. Our simulation results show that Aurora provides a robust architectural solution to handle temperature variation effects on future photonic NoCs. For instance, average BER and message error rate (MER) are reduced by 78% and 30% respectively when the combined device and architectural technique (SPF) is applied. From the perspective of power efficiency, Aurora is also superior to conventional photonic NoC architectures by as much as 33%.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129171697","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-30DOI: 10.1109/ICCD.2012.6378659
Samy Zaynoun, Muhammed S. Khairy, A. Eltawil, F. Kurdahi, A. Djahromi
As a result of supply voltage reduction and process variations effects, the error free margin for dynamic voltage scaling has been drastically reduced. This paper presents an error aware model for arithmetic and logic circuits that accurately and rapidly estimates the propagation delays of the output bits in a digital block operating under voltage scaling to identify circuit-level failures (timing violations) within the block. Consequently, these failure models are then used to examine how circuit-level failures affect system-level reliability. A case study consisting of a CORDIC DSP unit employing the proposed model provides tradeoffs between power, performance and reliability.
{"title":"Fast error aware model for arithmetic and logic circuits","authors":"Samy Zaynoun, Muhammed S. Khairy, A. Eltawil, F. Kurdahi, A. Djahromi","doi":"10.1109/ICCD.2012.6378659","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378659","url":null,"abstract":"As a result of supply voltage reduction and process variations effects, the error free margin for dynamic voltage scaling has been drastically reduced. This paper presents an error aware model for arithmetic and logic circuits that accurately and rapidly estimates the propagation delays of the output bits in a digital block operating under voltage scaling to identify circuit-level failures (timing violations) within the block. Consequently, these failure models are then used to examine how circuit-level failures affect system-level reliability. A case study consisting of a CORDIC DSP unit employing the proposed model provides tradeoffs between power, performance and reliability.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122395326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-30DOI: 10.1109/ICCD.2012.6378682
Sachhidh Kannan, Jeyavijayan Rajendran, R. Karri, O. Sinanoglu
Emerging Resistive Random Access Memories (RRAM) devices are an attractive option for future memory architectures due to their low-power and high density. However, their capacity is limited by sneak paths and the sensitivity of the sense amplifiers (SA). We develop a framework to maximize the capacity of RRAM memories by modeling the interactions between memory capacity, sneak paths, device parameters, and the sense amplifier. The framework explores the design space of the memory by considering different read/write mechanisms, sneak path elimination techniques, and multi-level storage.
{"title":"Engineering crossbar based emerging memory technologies","authors":"Sachhidh Kannan, Jeyavijayan Rajendran, R. Karri, O. Sinanoglu","doi":"10.1109/ICCD.2012.6378682","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378682","url":null,"abstract":"Emerging Resistive Random Access Memories (RRAM) devices are an attractive option for future memory architectures due to their low-power and high density. However, their capacity is limited by sneak paths and the sensitivity of the sense amplifiers (SA). We develop a framework to maximize the capacity of RRAM memories by modeling the interactions between memory capacity, sneak paths, device parameters, and the sense amplifier. The framework explores the design space of the memory by considering different read/write mechanisms, sneak path elimination techniques, and multi-level storage.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132798719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-30DOI: 10.1109/ICCD.2012.6378672
R. Morris, Avinash Karanth Kodi, A. Louri
The power dissipation of metallic interconnects in future multicore architectures is projected to be a major bottleneck as we scale to sub-nanometer regime. This has motivated researchers to develop alternate power-efficient technology solutions to the performance limitations of future multicores. Nanophotonic interconnects (NIs) is a disruptive technology solution that is capable of delivering the communication bandwidth at low power dissipation when the number of cores is scaled to large numbers. Similarly, 3D stacking is another interconnect technology solution that can lead to low energy/bit for communication. In this paper, we propose to combine NIs with with 3D stacking to develop a scalable, reconfigurable, power-efficient and high-performance interconnect for future many-core systems called 3D-NoC. We propose to develop a multi-layer NIs that can dynamically reconfigure without system intervention and allocate channel bandwidth from less utilized links to more utilized communication links. Our simulation results indicate that the performance can be further improved by 10%-25% for Splash-2, PARSEC and SPEC CPU2006 benchmarks.
{"title":"3D-NoC: Reconfigurable 3D photonic on-chip interconnect for multicores","authors":"R. Morris, Avinash Karanth Kodi, A. Louri","doi":"10.1109/ICCD.2012.6378672","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378672","url":null,"abstract":"The power dissipation of metallic interconnects in future multicore architectures is projected to be a major bottleneck as we scale to sub-nanometer regime. This has motivated researchers to develop alternate power-efficient technology solutions to the performance limitations of future multicores. Nanophotonic interconnects (NIs) is a disruptive technology solution that is capable of delivering the communication bandwidth at low power dissipation when the number of cores is scaled to large numbers. Similarly, 3D stacking is another interconnect technology solution that can lead to low energy/bit for communication. In this paper, we propose to combine NIs with with 3D stacking to develop a scalable, reconfigurable, power-efficient and high-performance interconnect for future many-core systems called 3D-NoC. We propose to develop a multi-layer NIs that can dynamically reconfigure without system intervention and allocate channel bandwidth from less utilized links to more utilized communication links. Our simulation results indicate that the performance can be further improved by 10%-25% for Splash-2, PARSEC and SPEC CPU2006 benchmarks.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114988712","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-30DOI: 10.1109/ICCD.2012.6378630
D. Hély, Maurin Augagneur, Y. Clauzel, Jeremy Dubeuf
In this work, we propose a physical unclonable function (i.e. PUF) based on setup time violations. The paper presents the way the PUF has been developed detailing the successive design iterations. This work has been developed by Grenoble INP students (J. Dubeuf, M. Augagneur and Y. Clauzel) during the secure IC design course at Grenoble INP Esisar for the Embedded System Challenge during the Cyber Security Awareness Week (CSAW) 2011 organized by Polytechnic Institute of New York University.
在这项工作中，我们提出了一个基于设置时间违规的物理不可克隆函数(即PUF)。本文介绍了PUF的开发方法，详细介绍了连续的设计迭代。这项工作是由格勒诺布尔INP学生(J. Dubeuf, M. Augagneur和Y. Clauzel)在格勒诺布尔INP Esisar的安全IC设计课程中开发的，该课程是为了参加由纽约大学理工学院组织的2011年网络安全意识周(CSAW)期间的嵌入式系统挑战。
{"title":"A physical unclonable function based on setup time violation","authors":"D. Hély, Maurin Augagneur, Y. Clauzel, Jeremy Dubeuf","doi":"10.1109/ICCD.2012.6378630","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378630","url":null,"abstract":"In this work, we propose a physical unclonable function (i.e. PUF) based on setup time violations. The paper presents the way the PUF has been developed detailing the successive design iterations. This work has been developed by Grenoble INP students (J. Dubeuf, M. Augagneur and Y. Clauzel) during the secure IC design course at Grenoble INP Esisar for the Embedded System Challenge during the Cyber Security Awareness Week (CSAW) 2011 organized by Polytechnic Institute of New York University.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123082792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-30DOI: 10.1109/ICCD.2012.6378704
Shohei Ono, Takeshi Matsumoto, M. Fujita
In modern VLSI designs, assertions play an important role to understand design intention and ensure correctness of designs. In this paper, we consider to generate assertions from simulation results. This assertion extraction is performed by examining whether a logical relation is satisfied among a set of signals. We propose to accelerate it by utilizing a highly parallelized computation performed by GPGPUs. Through the experiments with designs from industry, our implementation on GPGPU runs 30 times faster than a software implementation.
{"title":"Automatic assertion extraction in gate-level simulation using GPGPUs","authors":"Shohei Ono, Takeshi Matsumoto, M. Fujita","doi":"10.1109/ICCD.2012.6378704","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378704","url":null,"abstract":"In modern VLSI designs, assertions play an important role to understand design intention and ensure correctness of designs. In this paper, we consider to generate assertions from simulation results. This assertion extraction is performed by examining whether a logical relation is satisfied among a set of signals. We propose to accelerate it by utilizing a highly parallelized computation performed by GPGPUs. Through the experiments with designs from industry, our implementation on GPGPU runs 30 times faster than a software implementation.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124970266","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-30DOI: 10.1109/ICCD.2012.6378670
Taraneh Taghavi, Shyam Ramji, F. Musante, Suhasini Rege
In this paper we present a method for parameterized free space redistribution of a fragmented placement. The fragmentation problem arises in different contexts within the physical design automation, including post physical synthesis for filler cell insertion, incremental placement, timing optimization, and late mode ECO fix-ups. To address this problem, we apply a post-placement parameterized method of defragmentation. This method involves capturing a view of a given placement and modeling a dynamic programming problem to optimally maximize the amount of so-called useful free space as defined by a given set of parameters. The parameters act as constraints to preserve the row placement and order of the cells while minimizing the perturbation of the whole design for a successful timing and design closure. Experimental results demonstrate that by applying the proposed technique, on average, 9.7% increase in the number of inserted filler cells and 5.7% improvement in the success rate of incremental placement requests can be achieved with minimal or no impact on timing and wirelength. Moreover, when deployed in early mode buffering for timing optimization, this technique can result in 3% reduction in the number of paths with negative slacks.
{"title":"Parameterized free space redistribution for engineering change in placement of integrated circuits","authors":"Taraneh Taghavi, Shyam Ramji, F. Musante, Suhasini Rege","doi":"10.1109/ICCD.2012.6378670","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378670","url":null,"abstract":"In this paper we present a method for parameterized free space redistribution of a fragmented placement. The fragmentation problem arises in different contexts within the physical design automation, including post physical synthesis for filler cell insertion, incremental placement, timing optimization, and late mode ECO fix-ups. To address this problem, we apply a post-placement parameterized method of defragmentation. This method involves capturing a view of a given placement and modeling a dynamic programming problem to optimally maximize the amount of so-called useful free space as defined by a given set of parameters. The parameters act as constraints to preserve the row placement and order of the cells while minimizing the perturbation of the whole design for a successful timing and design closure. Experimental results demonstrate that by applying the proposed technique, on average, 9.7% increase in the number of inserted filler cells and 5.7% improvement in the success rate of incremental placement requests can be achieved with minimal or no impact on timing and wirelength. Moreover, when deployed in early mode buffering for timing optimization, this technique can result in 3% reduction in the number of paths with negative slacks.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122118962","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-30DOI: 10.1109/ICCD.2012.6378626
Zihan Xu, K. Sutaria, Chengen Yang, C. Chakrabarti, Yu Cao
As CMOS based memory devices near their end, memory technologies, such as Phase Change Random Access Memory (PRAM), have emerged as viable alternatives. This work develops a hierarchical modeling framework that connects the unique device physics of PRAM with its circuit and state transition properties. Such an approach enables design exploration at various levels in order to optimize the performance and yield. By providing a complete set of compact models, it supports SPICE simulation of PRAM in the presence of process variations and temporal degradation. Furthermore, this work proposes a new metric, State Transition Curve (STC) that supports the assessment of other performance metrics (e.g., power, speed, yield, etc.), helping gain valuable insights on PRAM reliability.
{"title":"Hierarchical modeling of Phase Change memory for reliable design","authors":"Zihan Xu, K. Sutaria, Chengen Yang, C. Chakrabarti, Yu Cao","doi":"10.1109/ICCD.2012.6378626","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378626","url":null,"abstract":"As CMOS based memory devices near their end, memory technologies, such as Phase Change Random Access Memory (PRAM), have emerged as viable alternatives. This work develops a hierarchical modeling framework that connects the unique device physics of PRAM with its circuit and state transition properties. Such an approach enables design exploration at various levels in order to optimize the performance and yield. By providing a complete set of compact models, it supports SPICE simulation of PRAM in the presence of process variations and temporal degradation. Furthermore, this work proposes a new metric, State Transition Curve (STC) that supports the assessment of other performance metrics (e.g., power, speed, yield, etc.), helping gain valuable insights on PRAM reliability.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129760681","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-30DOI: 10.1109/ICCD.2012.6378648
E. Kakoulli, V. Soteriou, T. Theocharides
The inherent spatio-temporal unevenness of traffic flows in Networks-on-Chips (NoCs) can cause unforeseen, and in cases, severe forms of congestion, known as hotspots. Hotspots reduce the NoC's effective throughput, where in the worst case scenario, the entire network can be brought to an unrecoverable halt as a hotspot(s) spreads across the topology. To alleviate this problematic phenomenon several adaptive routing algorithms employ online load-balancing functions, aiming to reduce the possibility of hotspots arising. Most, however, work passively, merely distributing traffic as evenly as possible among alternative network paths, and they cannot guarantee the absence of network congestion as their reactive capability in reducing hotspot formation(s) is limited. In this paper we present a new pro-active Hotspot-Preventive Routing Algorithm (HPRA) which uses the advance knowledge gained from network-embedded Artificial Neural Network-based (ANN) hotspot predictors to guide packet routing across the network in an effort to mitigate any unforeseen near-future occurrences of hotspots. These ANNs are trained offline and during multicore operation they gather online buffer utilization data to predict about-to-be-formed hotspots, promptly informing the HPRA routing algorithm to take appropriate action in preventing hotspot formation(s). Evaluation results across two synthetic traffic patterns, and traffic benchmarks gathered from a chip multiprocessor architecture, show that HPRA can reduce network latency and improve network throughput up to 81% when compared against several existing state-of-the-art congestion-aware routing functions. Hardware synthesis results demonstrate the efficacy of the HPRA mechanism.
{"title":"HPRA: A pro-active Hotspot-Preventive high-performance routing algorithm for Networks-on-Chips","authors":"E. Kakoulli, V. Soteriou, T. Theocharides","doi":"10.1109/ICCD.2012.6378648","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378648","url":null,"abstract":"The inherent spatio-temporal unevenness of traffic flows in Networks-on-Chips (NoCs) can cause unforeseen, and in cases, severe forms of congestion, known as hotspots. Hotspots reduce the NoC's effective throughput, where in the worst case scenario, the entire network can be brought to an unrecoverable halt as a hotspot(s) spreads across the topology. To alleviate this problematic phenomenon several adaptive routing algorithms employ online load-balancing functions, aiming to reduce the possibility of hotspots arising. Most, however, work passively, merely distributing traffic as evenly as possible among alternative network paths, and they cannot guarantee the absence of network congestion as their reactive capability in reducing hotspot formation(s) is limited. In this paper we present a new pro-active Hotspot-Preventive Routing Algorithm (HPRA) which uses the advance knowledge gained from network-embedded Artificial Neural Network-based (ANN) hotspot predictors to guide packet routing across the network in an effort to mitigate any unforeseen near-future occurrences of hotspots. These ANNs are trained offline and during multicore operation they gather online buffer utilization data to predict about-to-be-formed hotspots, promptly informing the HPRA routing algorithm to take appropriate action in preventing hotspot formation(s). Evaluation results across two synthetic traffic patterns, and traffic benchmarks gathered from a chip multiprocessor architecture, show that HPRA can reduce network latency and improve network throughput up to 81% when compared against several existing state-of-the-art congestion-aware routing functions. Hardware synthesis results demonstrate the efficacy of the HPRA mechanism.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127224435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-09-30DOI: 10.1109/ICCD.2012.6378686
Mickael Lanoe, E. Senn
Embedded systems have to support more and more demanding multimedia applications. Heterogeneous multi-core architectures are now commonplace in mobile electronic devices. The impact on the power and energy consumption is tremendous; it has to be evaluated as soon as possible in the design process. Multimedia development frameworks are used to abstract the complexity of the hardware to the designer. In this paper, we propose a methodology to develop high-level performance and consumption models for multimedia streaming applications based on the GStreamer framework. Our approach is based on measurements of the power consumptions and execution times during the processing of combined video and audio streams. Performance and consumption models are build for various plugins instantiated in the corresponding GStreamer pipelines. The combination of estimations for all those plugins leads to a precise evaluation of the complete plugin performances. The precision of the models is evaluated against measurements for different real-life streaming applications.
{"title":"Energy modelling of embedded multimedia streaming applications with GStreamer on heterogeneous MPSoC","authors":"Mickael Lanoe, E. Senn","doi":"10.1109/ICCD.2012.6378686","DOIUrl":"https://doi.org/10.1109/ICCD.2012.6378686","url":null,"abstract":"Embedded systems have to support more and more demanding multimedia applications. Heterogeneous multi-core architectures are now commonplace in mobile electronic devices. The impact on the power and energy consumption is tremendous; it has to be evaluated as soon as possible in the design process. Multimedia development frameworks are used to abstract the complexity of the hardware to the designer. In this paper, we propose a methodology to develop high-level performance and consumption models for multimedia streaming applications based on the GStreamer framework. Our approach is based on measurements of the power consumptions and execution times during the processing of combined video and audio streams. Performance and consumption models are build for various plugins instantiated in the corresponding GStreamer pipelines. The combination of estimations for all those plugins leads to a precise evaluation of the complete plugin performances. The precision of the models is evaluated against measurements for different real-life streaming applications.","PeriodicalId":313428,"journal":{"name":"2012 IEEE 30th International Conference on Computer Design (ICCD)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-09-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130408369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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