Pub Date : 2015-04-13DOI: 10.1109/RTAS.2015.7108415
Masud Ahmed, P. Hettiarachchi, N. Fisher
Over the years, multiple hardware and software operating modes have been employed in many computing devices (e.g., tablets, smart-phones, GPS receivers) to efficiently utilize device resources. Similar advantages are also preferred in realtime systems (RTS) due to the requirement that a RTS must respond in a timely manner to a physical environment that may change sporadically. An efficient multi-modal system (MMS) is also a prerequisite for the development of real-time control systems which can maintain stable system behavior while ensuring timing guarantees for a changing set of real-time tasks. However, the currently-available fixed-priority (FP) schedulability analysis for multi-modal systems with both software/hardware modes is computationally expensive. In addition, current schedulability analysis for systems that support mode changes requires an assumption that is often not suitable for cyber-physical systems (CPS): sensing and actuation in the underlying physical plant are preemptible activities. However, sensors such as radar transmitter/ receiver requires non-preemptible access to the processor upon sending and then processing the return signal for accuracy. In this research, we develop a framework for multi-modal RTS scheduled by FP algorithm along with efficient schedulability analysis with pseudo-polynomial complexity considering the advantages and limitations of specific software/hardware model. Two simulations: a case study on adaptive cruise control in automotive systems, and schedulability comparison are included to corroborate the performance of the schedulability analysis.
{"title":"Analysis of real-time multi-modal FP-scheduled systems with non-preemptible regions","authors":"Masud Ahmed, P. Hettiarachchi, N. Fisher","doi":"10.1109/RTAS.2015.7108415","DOIUrl":"https://doi.org/10.1109/RTAS.2015.7108415","url":null,"abstract":"Over the years, multiple hardware and software operating modes have been employed in many computing devices (e.g., tablets, smart-phones, GPS receivers) to efficiently utilize device resources. Similar advantages are also preferred in realtime systems (RTS) due to the requirement that a RTS must respond in a timely manner to a physical environment that may change sporadically. An efficient multi-modal system (MMS) is also a prerequisite for the development of real-time control systems which can maintain stable system behavior while ensuring timing guarantees for a changing set of real-time tasks. However, the currently-available fixed-priority (FP) schedulability analysis for multi-modal systems with both software/hardware modes is computationally expensive. In addition, current schedulability analysis for systems that support mode changes requires an assumption that is often not suitable for cyber-physical systems (CPS): sensing and actuation in the underlying physical plant are preemptible activities. However, sensors such as radar transmitter/ receiver requires non-preemptible access to the processor upon sending and then processing the return signal for accuracy. In this research, we develop a framework for multi-modal RTS scheduled by FP algorithm along with efficient schedulability analysis with pseudo-polynomial complexity considering the advantages and limitations of specific software/hardware model. Two simulations: a case study on adaptive cruise control in automotive systems, and schedulability comparison are included to corroborate the performance of the schedulability analysis.","PeriodicalId":320300,"journal":{"name":"21st IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130370048","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-13DOI: 10.1109/RTAS.2015.7108392
Qi Zhang, Xuandong Li, Linzhang Wang, Tian Zhang, Yi Wang, Z. Shao
NAND flash has been widely adopted as storage devices in real-time embedded systems. However, garbage collection is needed to reclaim space and introduces a lot of time overhead. As the worst system latency is determined by the worst-case execution time of garbage collection in NAND flash, it is important to optimize garbage collection so as to give a deterministic worst system latency. On the other hand, since the garbage collection does not happen very often, optimizing garbage collection should not bring too much overhead to the average system latency. This paper presents for the first time a worst-case and average-case joint optimization scheme for garbage collection in NAND flash. With our scheme, garbage collection can be postponed to the latest stage so improves the average system latency. By combining partial garbage collection and over-provisioning, our scheme can guarantee that one free block is enough to hold all pages from both write requests and valid-page copies. The experiments have been conducted on a real embedded platform and the results show that our technique can improve both worstcase and average-case system latency compared with the previous works.
{"title":"Optimizing deterministic garbage collection in NAND flash storage systems","authors":"Qi Zhang, Xuandong Li, Linzhang Wang, Tian Zhang, Yi Wang, Z. Shao","doi":"10.1109/RTAS.2015.7108392","DOIUrl":"https://doi.org/10.1109/RTAS.2015.7108392","url":null,"abstract":"NAND flash has been widely adopted as storage devices in real-time embedded systems. However, garbage collection is needed to reclaim space and introduces a lot of time overhead. As the worst system latency is determined by the worst-case execution time of garbage collection in NAND flash, it is important to optimize garbage collection so as to give a deterministic worst system latency. On the other hand, since the garbage collection does not happen very often, optimizing garbage collection should not bring too much overhead to the average system latency. This paper presents for the first time a worst-case and average-case joint optimization scheme for garbage collection in NAND flash. With our scheme, garbage collection can be postponed to the latest stage so improves the average system latency. By combining partial garbage collection and over-provisioning, our scheme can guarantee that one free block is enough to hold all pages from both write requests and valid-page copies. The experiments have been conducted on a real embedded platform and the results show that our technique can improve both worstcase and average-case system latency compared with the previous works.","PeriodicalId":320300,"journal":{"name":"21st IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"217 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134173316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-13DOI: 10.1109/RTAS.2015.7108453
Mohamed Hassan, A. Kaushik, Hiren D. Patel
We explore techniques to reverse-engineer properties of DRAM memory controllers (MCs). This includes page policies, address mapping schemes and command arbitration schemes. There are several benefits to knowing this information: they allow analysis techniques to effectively compute worst-case bounds, and they allow customizations to be made in software for predictability. We develop a latency-based analysis, and use this analysis to devise algorithms for micro-benchmarks to extract properties of MCs. In order to cover a breadth of page policies, address mappings and command arbitration schemes, we explore our technique using a micro-architecture simulation framework and document our findings.
{"title":"Reverse-engineering embedded memory controllers through latency-based analysis","authors":"Mohamed Hassan, A. Kaushik, Hiren D. Patel","doi":"10.1109/RTAS.2015.7108453","DOIUrl":"https://doi.org/10.1109/RTAS.2015.7108453","url":null,"abstract":"We explore techniques to reverse-engineer properties of DRAM memory controllers (MCs). This includes page policies, address mapping schemes and command arbitration schemes. There are several benefits to knowing this information: they allow analysis techniques to effectively compute worst-case bounds, and they allow customizations to be made in software for predictability. We develop a latency-based analysis, and use this analysis to devise algorithms for micro-benchmarks to extract properties of MCs. In order to cover a breadth of page policies, address mappings and command arbitration schemes, we explore our technique using a micro-architecture simulation framework and document our findings.","PeriodicalId":320300,"journal":{"name":"21st IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129166808","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-13DOI: 10.1109/RTAS.2015.7108450
R. Pellizzoni, Neda Paryab, Man-Ki Yoon, Stanley Bak, Sibin Mohan, R. Bobba
Traditionally real-time systems and security have been considered as separate domains. Recent attacks on various systems with real-time properties have shown the need for a redesign of such systems to include security as a first class principle. In this paper, we propose a general model for capturing security constraints between tasks in a real-time system. This model is then used in conjunction with real-time scheduling algorithms to prevent the leakage of information via storage channels on implicitly shared resources. We expand upon a mechanism to enforce these constraints viz., cleaning up of shared resource state, and provide schedulability conditions based on fixed priority scheduling with both preemptive and non-preemptive tasks. We perform extensive evaluations, both theoretical and experimental, the latter on a hardware-in-the-loop simulator of an unmanned aerial vehicle (UAV) that executes on a demonstration platform.
{"title":"A generalized model for preventing information leakage in hard real-time systems","authors":"R. Pellizzoni, Neda Paryab, Man-Ki Yoon, Stanley Bak, Sibin Mohan, R. Bobba","doi":"10.1109/RTAS.2015.7108450","DOIUrl":"https://doi.org/10.1109/RTAS.2015.7108450","url":null,"abstract":"Traditionally real-time systems and security have been considered as separate domains. Recent attacks on various systems with real-time properties have shown the need for a redesign of such systems to include security as a first class principle. In this paper, we propose a general model for capturing security constraints between tasks in a real-time system. This model is then used in conjunction with real-time scheduling algorithms to prevent the leakage of information via storage channels on implicitly shared resources. We expand upon a mechanism to enforce these constraints viz., cleaning up of shared resource state, and provide schedulability conditions based on fixed priority scheduling with both preemptive and non-preemptive tasks. We perform extensive evaluations, both theoretical and experimental, the latter on a hardware-in-the-loop simulator of an unmanned aerial vehicle (UAV) that executes on a demonstration platform.","PeriodicalId":320300,"journal":{"name":"21st IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133218010","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-13DOI: 10.1109/RTAS.2015.7108419
Connor Imes, David H. K. Kim, M. Maggio, H. Hoffmann
Embedded real-time systems must meet timing constraints while minimizing energy consumption. To this end, many energy optimizations are introduced for specific platforms or specific applications. These solutions are not portable, however, and when the application or the platform change, these solutions must be redesigned. Portable techniques are hard to develop due to the varying tradeoffs experienced with different application/platform configurations. This paper addresses the problem of finding and exploiting general tradeoffs, using control theory and mathematical optimization to achieve energy minimization under soft real-time application constraints. The paper presents POET, an open-source C library and runtime system that takes a specification of the platform resources and optimizes the application execution. We test POET's ability to portably deliver predictable timing and energy reduction on two embedded systems with different tradeoff spaces - the first with a mobile Intel Haswell processor, and the second with an ARM big.LITTLE System on Chip. POET achieves the desired latency goals with small error while consuming, on average, only 1.3% more energy than the dynamic optimal oracle on the Haswell and 2.9% more on the ARM. We believe this open-source, library-based approach to resource management will simplify the process of writing portable, energy-efficient code for embedded systems.
{"title":"POET: a portable approach to minimizing energy under soft real-time constraints","authors":"Connor Imes, David H. K. Kim, M. Maggio, H. Hoffmann","doi":"10.1109/RTAS.2015.7108419","DOIUrl":"https://doi.org/10.1109/RTAS.2015.7108419","url":null,"abstract":"Embedded real-time systems must meet timing constraints while minimizing energy consumption. To this end, many energy optimizations are introduced for specific platforms or specific applications. These solutions are not portable, however, and when the application or the platform change, these solutions must be redesigned. Portable techniques are hard to develop due to the varying tradeoffs experienced with different application/platform configurations. This paper addresses the problem of finding and exploiting general tradeoffs, using control theory and mathematical optimization to achieve energy minimization under soft real-time application constraints. The paper presents POET, an open-source C library and runtime system that takes a specification of the platform resources and optimizes the application execution. We test POET's ability to portably deliver predictable timing and energy reduction on two embedded systems with different tradeoff spaces - the first with a mobile Intel Haswell processor, and the second with an ARM big.LITTLE System on Chip. POET achieves the desired latency goals with small error while consuming, on average, only 1.3% more energy than the dynamic optimal oracle on the Haswell and 2.9% more on the ARM. We believe this open-source, library-based approach to resource management will simplify the process of writing portable, energy-efficient code for embedded systems.","PeriodicalId":320300,"journal":{"name":"21st IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133251327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-13DOI: 10.1109/RTAS.2015.7108436
Chong Li, Sisu Xi, Chenyang Lu, C. Gill, R. Guérin
As virtualization technology becomes ever more capable, large-scale distributed applications are increasingly deployed in virtualized environments such as data centers and computational clouds. Many large-scale applications have soft real-time requirements and benefit from low and predictable latency, even in the presence of diverse traffic patterns between virtualized hosts. In this paper, we examine the policies and mechanisms affecting communication latency between virtual machines based on the Xen platform, and identify limitations that could result in long or unpredictable network traffic latencies. To address these limitations, we propose VATC, a Virtualization-Aware Traffic Control framework for prioritizing network traffic in virtualized hosts. Results of our experiments show how and why VATC can improve predictability and reduce delay for latency sensitive applications, while introducing limited overhead.
{"title":"Prioritizing soft real-time network traffic in virtualized hosts based on Xen","authors":"Chong Li, Sisu Xi, Chenyang Lu, C. Gill, R. Guérin","doi":"10.1109/RTAS.2015.7108436","DOIUrl":"https://doi.org/10.1109/RTAS.2015.7108436","url":null,"abstract":"As virtualization technology becomes ever more capable, large-scale distributed applications are increasingly deployed in virtualized environments such as data centers and computational clouds. Many large-scale applications have soft real-time requirements and benefit from low and predictable latency, even in the presence of diverse traffic patterns between virtualized hosts. In this paper, we examine the policies and mechanisms affecting communication latency between virtual machines based on the Xen platform, and identify limitations that could result in long or unpredictable network traffic latencies. To address these limitations, we propose VATC, a Virtualization-Aware Traffic Control framework for prioritizing network traffic in virtualized hosts. Results of our experiments show how and why VATC can improve predictability and reduce delay for latency sensitive applications, while introducing limited overhead.","PeriodicalId":320300,"journal":{"name":"21st IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129636215","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-13DOI: 10.1109/RTAS.2015.7108445
Jung-Eun Kim, T. Abdelzaher, L. Sha
This paper solves the challenge of offline response time analysis of independent periodic tasks with constrained deadlines early in the software development cycle, under generalized rate-monotonic scheduling. CPU budgets are allocated to different applications and each application is composed of multiple periodic tasks that must share the same budget. Physical application requirements impose specifications on task periods and deadlines from the very beginning, but unlike the common assumption in traditional response time analysis, task execution times are not known. This is because task execution times depend on the exact system implementation, which is not finalized until later in the development cycle. Questions facing designers become: will my task meet its deadline given lack of knowledge of other tasks' execution times? What is the smallest deadline that my task can meet? These questions are traditionally addressed by using a two level scheduler: CPU is partitioned and assigned to application, and task priorities are determined within the scope of an application, and when server becomes active it schedules the tasks locally. Such two level scheduling approach introduces priority inversion across applications. In our approach, different applications' tasks are globally scheduled and yet the CPU resource is still partitioned and assigned to applications as a CPU budget. We schedule all the tasks globally while enforcing application budgets. The proposed new form of response time analysis is called budgeted generalized rate-monotonic analysis to compute the maximum response time for each task given only application budgets and task periods, but without knowledge of task execution times. We formulate this schedulability problem as a mixed integer linear programming problem and demonstrate a solution that computes the exact worst-case response times. Evaluation shows that our solution outperforms, in terms of schedulability, both global utilization bounds and mechanisms that attain temporal modularity via resource partitioning.
{"title":"Budgeted generalized rate monotonic analysis for the partitioned, yet globally scheduled uniprocessor model","authors":"Jung-Eun Kim, T. Abdelzaher, L. Sha","doi":"10.1109/RTAS.2015.7108445","DOIUrl":"https://doi.org/10.1109/RTAS.2015.7108445","url":null,"abstract":"This paper solves the challenge of offline response time analysis of independent periodic tasks with constrained deadlines early in the software development cycle, under generalized rate-monotonic scheduling. CPU budgets are allocated to different applications and each application is composed of multiple periodic tasks that must share the same budget. Physical application requirements impose specifications on task periods and deadlines from the very beginning, but unlike the common assumption in traditional response time analysis, task execution times are not known. This is because task execution times depend on the exact system implementation, which is not finalized until later in the development cycle. Questions facing designers become: will my task meet its deadline given lack of knowledge of other tasks' execution times? What is the smallest deadline that my task can meet? These questions are traditionally addressed by using a two level scheduler: CPU is partitioned and assigned to application, and task priorities are determined within the scope of an application, and when server becomes active it schedules the tasks locally. Such two level scheduling approach introduces priority inversion across applications. In our approach, different applications' tasks are globally scheduled and yet the CPU resource is still partitioned and assigned to applications as a CPU budget. We schedule all the tasks globally while enforcing application budgets. The proposed new form of response time analysis is called budgeted generalized rate-monotonic analysis to compute the maximum response time for each task given only application budgets and task periods, but without knowledge of task execution times. We formulate this schedulability problem as a mixed integer linear programming problem and demonstrate a solution that computes the exact worst-case response times. Evaluation shows that our solution outperforms, in terms of schedulability, both global utilization bounds and mechanisms that attain temporal modularity via resource partitioning.","PeriodicalId":320300,"journal":{"name":"21st IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124705417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-13DOI: 10.1109/RTAS.2015.7108457
N. Asmussen, M. Völp, Benedikt Noethen, A. Ungethüm
Many-core systems are increasingly used in real-time settings to meet the performance requirements of advanced applications such as the classification and tracking of dynamic objects for autonomous driving [1] or the generation of safe trajectories through rough terrain [2]. Task sets of these applications are often mixtures of short running, low latency tasks, such as the various filtering steps required for signal or image processing, and long running tasks, such as route planning, which occupy their assigned core for extended periods of time. Short running tasks often follow a data flow programming paradigm and are organized into directed acyclic graphs (DAG) based on their input-/output-dependencies. Once these dependencies are met, they execute without further task interactions until they complete producing outputs for subsequent tasks. Long running tasks on the other hand interact frequently with other tasks, accessing data located in the memories of remote cores or interacting with operating-system services. This demonstrator shows how both types of applications can be integrated into a single many-core architecture.
{"title":"Demo abstract: Taming many heterogeneous cores","authors":"N. Asmussen, M. Völp, Benedikt Noethen, A. Ungethüm","doi":"10.1109/RTAS.2015.7108457","DOIUrl":"https://doi.org/10.1109/RTAS.2015.7108457","url":null,"abstract":"Many-core systems are increasingly used in real-time settings to meet the performance requirements of advanced applications such as the classification and tracking of dynamic objects for autonomous driving [1] or the generation of safe trajectories through rough terrain [2]. Task sets of these applications are often mixtures of short running, low latency tasks, such as the various filtering steps required for signal or image processing, and long running tasks, such as route planning, which occupy their assigned core for extended periods of time. Short running tasks often follow a data flow programming paradigm and are organized into directed acyclic graphs (DAG) based on their input-/output-dependencies. Once these dependencies are met, they execute without further task interactions until they complete producing outputs for subsequent tasks. Long running tasks on the other hand interact frequently with other tasks, accessing data located in the memories of remote cores or interacting with operating-system services. This demonstrator shows how both types of applications can be integrated into a single many-core architecture.","PeriodicalId":320300,"journal":{"name":"21st IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130036496","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-13DOI: 10.1109/RTAS.2015.7108459
Masud Ahmed, Honglei Chen, N. Fisher
The interaction of a cyber-physical system (CPS) may impose additional constraints upon cyber aspects of the system. For instance, sensing and actuation often require non-preemption to ensure “accuracy” in data acquisition (e.g., radar sensors in automotive a cruise control system). Furthermore, CPS may require that a system adapts to changing environment which requires support for multiple operating modes. A multimode CPS may also enable resource-efficient solution by providing shared processing platforms to subsystems. Recent development [1] of multi-modal fixed-priority schedulability with non-preemption can facilitate multi-modal CPS-based design. In this demo, we present the benefits of such design choices by devloping a simple automotive adaptive cruise control (ACC) system using System objectsTM and Phased Array System ToolboxTM, which provides state-of-the-art tools for radar simulation. The ACC application composes tasks for radar transmission, reception, and controller upon a single processing platform. We consider radar transmission and signal receiving tasks to have non-preemptible execution regions.
{"title":"Demo abstract: Multi-modal scheduling of radar-based cruise control system","authors":"Masud Ahmed, Honglei Chen, N. Fisher","doi":"10.1109/RTAS.2015.7108459","DOIUrl":"https://doi.org/10.1109/RTAS.2015.7108459","url":null,"abstract":"The interaction of a cyber-physical system (CPS) may impose additional constraints upon cyber aspects of the system. For instance, sensing and actuation often require non-preemption to ensure “accuracy” in data acquisition (e.g., radar sensors in automotive a cruise control system). Furthermore, CPS may require that a system adapts to changing environment which requires support for multiple operating modes. A multimode CPS may also enable resource-efficient solution by providing shared processing platforms to subsystems. Recent development [1] of multi-modal fixed-priority schedulability with non-preemption can facilitate multi-modal CPS-based design. In this demo, we present the benefits of such design choices by devloping a simple automotive adaptive cruise control (ACC) system using System objectsTM and Phased Array System ToolboxTM, which provides state-of-the-art tools for radar simulation. The ACC application composes tasks for radar transmission, reception, and controller upon a single processing platform. We consider radar transmission and signal receiving tasks to have non-preemptible execution regions.","PeriodicalId":320300,"journal":{"name":"21st IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134196563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-04-13DOI: 10.1109/RTAS.2015.7108446
Jihye Kwon, Kang-Wook Kim, Sangyoun Paik, Jihwa Lee, Chang-Gun Lee
Past researches on multicore scheduling assume that a computational unit has already been parallelized into a prefixed number of threads. However, with recent technologies such as OpenCL, a computational unit can be parallelized in many different ways with runtime selectable numbers of threads. This paper proposes an optimal algorithm for parallelizing and scheduling a set of parallel tasks with multiple parallelization options on multiple CPU cores. The proposed algorithm is validated through both simulation and actual implementation. To the best of our knowledge, this is the first work addressing the problem of scheduling real-time tasks with multiple parallelization options on multiple CPU cores.
{"title":"Multicore scheduling of parallel real-time tasks with multiple parallelization options","authors":"Jihye Kwon, Kang-Wook Kim, Sangyoun Paik, Jihwa Lee, Chang-Gun Lee","doi":"10.1109/RTAS.2015.7108446","DOIUrl":"https://doi.org/10.1109/RTAS.2015.7108446","url":null,"abstract":"Past researches on multicore scheduling assume that a computational unit has already been parallelized into a prefixed number of threads. However, with recent technologies such as OpenCL, a computational unit can be parallelized in many different ways with runtime selectable numbers of threads. This paper proposes an optimal algorithm for parallelizing and scheduling a set of parallel tasks with multiple parallelization options on multiple CPU cores. The proposed algorithm is validated through both simulation and actual implementation. To the best of our knowledge, this is the first work addressing the problem of scheduling real-time tasks with multiple parallelization options on multiple CPU cores.","PeriodicalId":320300,"journal":{"name":"21st IEEE Real-Time and Embedded Technology and Applications Symposium","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-04-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114394306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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