Pub Date : 2017-12-01DOI: 10.1109/ICCECE.2017.8526224
Namrata Singh, Jayati Bhardwaj
Preventing the secret data from malicious attackers or intruders is a part of a wide range field known as steganography. Adding a pinch to this wide area of research with a new variety could be of great deal to get rid of the attackers. This paper presents a video steganography technique for hiding audio data sequences into the random frames of the cover video. The embedding is done by using the LSB embedding technique. Before inculcating the new LSB bits of audio, XORing among the audio bits and the original LSB bits is done. This XORing avoids distortion in the cover video as well as prevents data loss after extraction.
{"title":"Randomized LSB Based Video Steganography for Hiding Acoustic Data Using XOR Technique","authors":"Namrata Singh, Jayati Bhardwaj","doi":"10.1109/ICCECE.2017.8526224","DOIUrl":"https://doi.org/10.1109/ICCECE.2017.8526224","url":null,"abstract":"Preventing the secret data from malicious attackers or intruders is a part of a wide range field known as steganography. Adding a pinch to this wide area of research with a new variety could be of great deal to get rid of the attackers. This paper presents a video steganography technique for hiding audio data sequences into the random frames of the cover video. The embedding is done by using the LSB embedding technique. Before inculcating the new LSB bits of audio, XORing among the audio bits and the original LSB bits is done. This XORing avoids distortion in the cover video as well as prevents data loss after extraction.","PeriodicalId":325599,"journal":{"name":"2017 International Conference on Computer, Electrical & Communication Engineering (ICCECE)","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126238668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICCECE.2017.8526188
S. Banerjee, S. Chattaraj
A Kalman Filter based solution to running train localization problem from station to station (in short distance) has been explored. Signal system based solution aided with track side installed hardware is a classical approach, however, involves high operational cost due to installation, maintenance and protection against vandalism. Recent development is sought based on the principles of intelligent distributed control system, which operates on data supplied by both on board navigation sensors and satellite navigation system. Such a system is prone to failure due to transient nature of satellite data in adverse situations. Kalman filter based estimator constructed with only on-board sensor data has been proven to be at par. However, such a full order filter involves many states in its dynamics, which incurs high computational cost. Present work discusses the design and implementation of a reduced order Kalman filter based on on-board sensor data, to solve running train localization problem. Simulation results are presented in order to establish the effectiveness of the proposed filter.
{"title":"Performance Evaluation of a Reduced Order Kalman Filter for Running Train Localization Problem","authors":"S. Banerjee, S. Chattaraj","doi":"10.1109/ICCECE.2017.8526188","DOIUrl":"https://doi.org/10.1109/ICCECE.2017.8526188","url":null,"abstract":"A Kalman Filter based solution to running train localization problem from station to station (in short distance) has been explored. Signal system based solution aided with track side installed hardware is a classical approach, however, involves high operational cost due to installation, maintenance and protection against vandalism. Recent development is sought based on the principles of intelligent distributed control system, which operates on data supplied by both on board navigation sensors and satellite navigation system. Such a system is prone to failure due to transient nature of satellite data in adverse situations. Kalman filter based estimator constructed with only on-board sensor data has been proven to be at par. However, such a full order filter involves many states in its dynamics, which incurs high computational cost. Present work discusses the design and implementation of a reduced order Kalman filter based on on-board sensor data, to solve running train localization problem. Simulation results are presented in order to establish the effectiveness of the proposed filter.","PeriodicalId":325599,"journal":{"name":"2017 International Conference on Computer, Electrical & Communication Engineering (ICCECE)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130887543","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICCECE.2017.8526197
Roshan Ghosh, Saikat Mondal, Sudip Kumar Ghorui
Development in Silicon Carbide (SiC) semiconductor technology is gaining immense importance compared to the conventional silicon based semiconductor devices. Application areas where excellent level of efficiency, fast switching frequencies, very minimum switching losses and impressive performance under elevated temperatures is expected SiC provides the best results. Thus it plays a prominent role in future electrical grid technology. This paper analyses the performance of a SiC based voltage source converter (VSC) operating in HVDC transmission system under the DC fault condition. Simulations conducted on MATLAB/Simulink shows that proposed SiC based VSC-HVDC protection scheme reduces the DC short circuit fault current very quickly compared to the Si based VSC. Performance of three phase harmonic filters to eliminate the converter generated harmonics is also examined.
{"title":"SiC MOSFET Based VSC Used in HVDC Transmission with DC Fault Protection Scheme","authors":"Roshan Ghosh, Saikat Mondal, Sudip Kumar Ghorui","doi":"10.1109/ICCECE.2017.8526197","DOIUrl":"https://doi.org/10.1109/ICCECE.2017.8526197","url":null,"abstract":"Development in Silicon Carbide (SiC) semiconductor technology is gaining immense importance compared to the conventional silicon based semiconductor devices. Application areas where excellent level of efficiency, fast switching frequencies, very minimum switching losses and impressive performance under elevated temperatures is expected SiC provides the best results. Thus it plays a prominent role in future electrical grid technology. This paper analyses the performance of a SiC based voltage source converter (VSC) operating in HVDC transmission system under the DC fault condition. Simulations conducted on MATLAB/Simulink shows that proposed SiC based VSC-HVDC protection scheme reduces the DC short circuit fault current very quickly compared to the Si based VSC. Performance of three phase harmonic filters to eliminate the converter generated harmonics is also examined.","PeriodicalId":325599,"journal":{"name":"2017 International Conference on Computer, Electrical & Communication Engineering (ICCECE)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114783973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICCECE.2017.8526191
Arnab Pal, A. Chakraborty, A. Bhowmik, Bhaskar Bhattacharya
The necessity for flexible electric systems, changing regulatory & economic scenarios, energy savings & environmental impact are providing impetus to the development of distributed generation (DG), which is predicted to play an increasing role in the electric power system of the near future. Allocation of DG units at non optimum places can result low or over voltages in the network. On the other hand, the installation of DG can have positive impacts on the distribution system by enabling reactive power compensation for a voltage control, reducing the losses, contributing for frequency regulation and acting as spinning reserve in the main system. For that reason, the use of a methodology capable of analyzing the influence on some system characteristics of DG allocation can be very useful for the system planning engineer when dealing with the increase of DG penetration that is happening nowadays. This paper presents two newly developed backward forward sweep load flow based algorithms to determine the optimal location to place a DG unit in IEEE 33 and IEEE 69 test bus distribution systems to improve the voltage profile of the entire system as well as power loss minimization. The proposed methods are found to be very effective for power loss minimization with fast convergence.
{"title":"Optimal Placement of DG Units in Distribution Network Using APCSA and OBOSA for Power Loss and Execution Time Minimization","authors":"Arnab Pal, A. Chakraborty, A. Bhowmik, Bhaskar Bhattacharya","doi":"10.1109/ICCECE.2017.8526191","DOIUrl":"https://doi.org/10.1109/ICCECE.2017.8526191","url":null,"abstract":"The necessity for flexible electric systems, changing regulatory & economic scenarios, energy savings & environmental impact are providing impetus to the development of distributed generation (DG), which is predicted to play an increasing role in the electric power system of the near future. Allocation of DG units at non optimum places can result low or over voltages in the network. On the other hand, the installation of DG can have positive impacts on the distribution system by enabling reactive power compensation for a voltage control, reducing the losses, contributing for frequency regulation and acting as spinning reserve in the main system. For that reason, the use of a methodology capable of analyzing the influence on some system characteristics of DG allocation can be very useful for the system planning engineer when dealing with the increase of DG penetration that is happening nowadays. This paper presents two newly developed backward forward sweep load flow based algorithms to determine the optimal location to place a DG unit in IEEE 33 and IEEE 69 test bus distribution systems to improve the voltage profile of the entire system as well as power loss minimization. The proposed methods are found to be very effective for power loss minimization with fast convergence.","PeriodicalId":325599,"journal":{"name":"2017 International Conference on Computer, Electrical & Communication Engineering (ICCECE)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123328621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICCECE.2017.8526187
Anirban Chowdhury, Raniit Roy, K. Mandal
An improved, fast and simple optimization algorithm, Jaya, is applied on a multi-objective, constrained problem to find the optimal allocation of a single and two distributed generators (DG), taking care of security limits. During sizing and optimal allocation of the DG/DGs, technical, social and economic conditions have been taken into account. The objective function is based on indices namely, voltage profile enhancement index (VPEI), emission cost benefit index (ECBI) and benefit cost ratio (BCR), so as to analyze the effect of the DG/DGs on IEEE 33 and IEEE 69 bus systems. This manuscript presents a comparative study of single DG and twin DG allocation of same capacity in total as well as the performance of Jaya in calculating the optimal size of DG considering the technical, social and economic impacts.
{"title":"Comparative Study of Single and Multiple Point Renewable Energy Based DG Allocation Considering Improvement of Voltage Stability, Economic and Environmental Factors Using Jaya Algorithm","authors":"Anirban Chowdhury, Raniit Roy, K. Mandal","doi":"10.1109/ICCECE.2017.8526187","DOIUrl":"https://doi.org/10.1109/ICCECE.2017.8526187","url":null,"abstract":"An improved, fast and simple optimization algorithm, Jaya, is applied on a multi-objective, constrained problem to find the optimal allocation of a single and two distributed generators (DG), taking care of security limits. During sizing and optimal allocation of the DG/DGs, technical, social and economic conditions have been taken into account. The objective function is based on indices namely, voltage profile enhancement index (VPEI), emission cost benefit index (ECBI) and benefit cost ratio (BCR), so as to analyze the effect of the DG/DGs on IEEE 33 and IEEE 69 bus systems. This manuscript presents a comparative study of single DG and twin DG allocation of same capacity in total as well as the performance of Jaya in calculating the optimal size of DG considering the technical, social and economic impacts.","PeriodicalId":325599,"journal":{"name":"2017 International Conference on Computer, Electrical & Communication Engineering (ICCECE)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124512136","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICCECE.2017.8526216
D. Roy, R. Dasgupta
In this Paper the Multi-Objective Particle Swarm Optimisation has been used to demonstrate ways to improve the efficiency of Tea Industry after implementation in MAT-LAB. The data for Terai Tea Estate has been extracted from the Financial Statements obtained from Tea Board. The ratio functions have been identified, whose maximisation will improve the performance of the organisation. The regression analysis has been performed to estimate the coefficients of two ratio functions. The Pareto Front has been derived for this dual objective function using Multi-Objective Particle Swarm Optimisation. The results have been presented in this paper.
{"title":"Performance Improvement of Tea Industry with Multi Objective Particle Swarm Optimisation","authors":"D. Roy, R. Dasgupta","doi":"10.1109/ICCECE.2017.8526216","DOIUrl":"https://doi.org/10.1109/ICCECE.2017.8526216","url":null,"abstract":"In this Paper the Multi-Objective Particle Swarm Optimisation has been used to demonstrate ways to improve the efficiency of Tea Industry after implementation in MAT-LAB. The data for Terai Tea Estate has been extracted from the Financial Statements obtained from Tea Board. The ratio functions have been identified, whose maximisation will improve the performance of the organisation. The regression analysis has been performed to estimate the coefficients of two ratio functions. The Pareto Front has been derived for this dual objective function using Multi-Objective Particle Swarm Optimisation. The results have been presented in this paper.","PeriodicalId":325599,"journal":{"name":"2017 International Conference on Computer, Electrical & Communication Engineering (ICCECE)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114939101","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICCECE.2017.8526211
M. Tewari, Susovan Jana, R. Parekh
Image reconstruction from image fragments has lots of application areas like forensics, art restoration, reconstructive surgery, archeology, puzzle gaming, and civil construction. Reconstruction becomes more challenging when number of fragments increases, image size increases, fragments are similar in shape and color, or fragments are transformed and shuffled. To execute image reconstruction in an effective and efficient manner, an automated computer-based system has been proposed in this paper using image processing techniques. A median filter is first applied to remove noise, after which Speeded Up Robust Features (SURF) are used to orient the fragments properly by reversing any arbitrary transformation applied. Finally, the candidate fragment for each position is chosen using an intelligent fragment selection technique. The proposed method achieves a very good accuracy of 97.78% to 100% and takes minimal time for reconstruction as compared to manual reconstruction.
{"title":"An Automated System for Image Reconstruction from Distorted Image Fragments","authors":"M. Tewari, Susovan Jana, R. Parekh","doi":"10.1109/ICCECE.2017.8526211","DOIUrl":"https://doi.org/10.1109/ICCECE.2017.8526211","url":null,"abstract":"Image reconstruction from image fragments has lots of application areas like forensics, art restoration, reconstructive surgery, archeology, puzzle gaming, and civil construction. Reconstruction becomes more challenging when number of fragments increases, image size increases, fragments are similar in shape and color, or fragments are transformed and shuffled. To execute image reconstruction in an effective and efficient manner, an automated computer-based system has been proposed in this paper using image processing techniques. A median filter is first applied to remove noise, after which Speeded Up Robust Features (SURF) are used to orient the fragments properly by reversing any arbitrary transformation applied. Finally, the candidate fragment for each position is chosen using an intelligent fragment selection technique. The proposed method achieves a very good accuracy of 97.78% to 100% and takes minimal time for reconstruction as compared to manual reconstruction.","PeriodicalId":325599,"journal":{"name":"2017 International Conference on Computer, Electrical & Communication Engineering (ICCECE)","volume":"85 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126239061","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICCECE.2017.8526219
Saikat Mondal, Sudip Kumar Ghorui, Roshan Ghosh
Fuzzy logic based control system provides a simple and efficient method to control highly complex and imprecise situation. However, the lack of simple hardware designs that is the capable of implementing fuzzy controller's parameters in a single chip, sometimes limits the capability of fuzzy based system in an automotive and industrial environment. In present days, a reconfigurable hardware platform like field programmable gate array (FPGA) has become an alluring alternative to synthesis and implements the desired system with an appropriate design for automation tool. This paper aims to address different hardware implementation issues of fuzzy system on a real-time environment (FPGA) and also proposes the hardware friendly neuro-fuzzy technique as a better replacement of a fuzzy system. In this paper, a simple rule base has been realized on the Xilinx SPARTAN 3AN FPGA development board to bolster the feasibility and superiority of the neuro-fuzzy over the fuzzy system. For the purpose of hardware implementation, optimum choice in terms of speed, accuracy and resource utilization is obtained in case of neuro-fuzzy technique and the results are in conformation.
{"title":"Hybrid System: A Smart Choice for Real Time Application","authors":"Saikat Mondal, Sudip Kumar Ghorui, Roshan Ghosh","doi":"10.1109/ICCECE.2017.8526219","DOIUrl":"https://doi.org/10.1109/ICCECE.2017.8526219","url":null,"abstract":"Fuzzy logic based control system provides a simple and efficient method to control highly complex and imprecise situation. However, the lack of simple hardware designs that is the capable of implementing fuzzy controller's parameters in a single chip, sometimes limits the capability of fuzzy based system in an automotive and industrial environment. In present days, a reconfigurable hardware platform like field programmable gate array (FPGA) has become an alluring alternative to synthesis and implements the desired system with an appropriate design for automation tool. This paper aims to address different hardware implementation issues of fuzzy system on a real-time environment (FPGA) and also proposes the hardware friendly neuro-fuzzy technique as a better replacement of a fuzzy system. In this paper, a simple rule base has been realized on the Xilinx SPARTAN 3AN FPGA development board to bolster the feasibility and superiority of the neuro-fuzzy over the fuzzy system. For the purpose of hardware implementation, optimum choice in terms of speed, accuracy and resource utilization is obtained in case of neuro-fuzzy technique and the results are in conformation.","PeriodicalId":325599,"journal":{"name":"2017 International Conference on Computer, Electrical & Communication Engineering (ICCECE)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121905518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICCECE.2017.8526196
Syed Ali Imran Quadri, Mohd Ziauddin Jahangir
Branch predictors are implemented on pipelined CPUs having different types of instructions. Both unconditional and conditional branches are implemented utilizing different instruction set formats of the CPU. A basic pipelined CPU consists of three stages Fetch, Decode, and Execute. All the instructions are executed in parallel, hence every stage is busy with an instruction which saves the wastage of time and increases the performance. Hazards will occur because of Conditional branches in the pipeline which changes the sequential flow of execution. To overcome these hazards, the pipeline should be made empty and loaded with appropriate instruction which avoids the wastage of time. Hence Branch predictors are essential in CPUs as it saves the wastage of time by guessing the correct sequence of instruction as the conditional branches changes the sequence of instructions. Three types of Branch Predictors are implemented on pipelined CPUs separately which are simulated, synthesized and bit-files are generated using Xilinx ISE tool, the bit-files are later dumped on Xilinx SPARTAN-6 board and the results are analyzed using CHIPSCOPE.
{"title":"Design, Implementation and Performance Comparison of Different Branch Predictors on Pipelined-CPU","authors":"Syed Ali Imran Quadri, Mohd Ziauddin Jahangir","doi":"10.1109/ICCECE.2017.8526196","DOIUrl":"https://doi.org/10.1109/ICCECE.2017.8526196","url":null,"abstract":"Branch predictors are implemented on pipelined CPUs having different types of instructions. Both unconditional and conditional branches are implemented utilizing different instruction set formats of the CPU. A basic pipelined CPU consists of three stages Fetch, Decode, and Execute. All the instructions are executed in parallel, hence every stage is busy with an instruction which saves the wastage of time and increases the performance. Hazards will occur because of Conditional branches in the pipeline which changes the sequential flow of execution. To overcome these hazards, the pipeline should be made empty and loaded with appropriate instruction which avoids the wastage of time. Hence Branch predictors are essential in CPUs as it saves the wastage of time by guessing the correct sequence of instruction as the conditional branches changes the sequence of instructions. Three types of Branch Predictors are implemented on pipelined CPUs separately which are simulated, synthesized and bit-files are generated using Xilinx ISE tool, the bit-files are later dumped on Xilinx SPARTAN-6 board and the results are analyzed using CHIPSCOPE.","PeriodicalId":325599,"journal":{"name":"2017 International Conference on Computer, Electrical & Communication Engineering (ICCECE)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128008981","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-12-01DOI: 10.1109/ICCECE.2017.8526190
Mehr-e-Munir, S. Kiani, Daniyal Babar, S. Khan
Ground irregularities also known as Defected ground structures (DGS) is a freshly presented innovatory way in designing of patch antennas to boost up the performance of antenna constraints. This study presents a novel proposal of ground irregularities or defected ground structure is proposed for suppression of mutual coupling effects among 2xl multiple input multiple output patch array designed on Roggers Duroid 5880. The two adjacent M shape structures surrounding Dumbbell Shaped structure and sandwiched between Dumbbell shape patterns showed the significant level of surface wave suppression up to −46dB while maintaining the gain of 4.7dB and 5.6dBi of directivity. The patch array operates at 4 to 4.3GHz for Fixed and Radio satellite services (FSS) and (RSS) and radio altimeter application systems.
{"title":"Mutual Coupling Minimization of MIMO Antenna for Satellite Services and Radio Service Applications","authors":"Mehr-e-Munir, S. Kiani, Daniyal Babar, S. Khan","doi":"10.1109/ICCECE.2017.8526190","DOIUrl":"https://doi.org/10.1109/ICCECE.2017.8526190","url":null,"abstract":"Ground irregularities also known as Defected ground structures (DGS) is a freshly presented innovatory way in designing of patch antennas to boost up the performance of antenna constraints. This study presents a novel proposal of ground irregularities or defected ground structure is proposed for suppression of mutual coupling effects among 2xl multiple input multiple output patch array designed on Roggers Duroid 5880. The two adjacent M shape structures surrounding Dumbbell Shaped structure and sandwiched between Dumbbell shape patterns showed the significant level of surface wave suppression up to −46dB while maintaining the gain of 4.7dB and 5.6dBi of directivity. The patch array operates at 4 to 4.3GHz for Fixed and Radio satellite services (FSS) and (RSS) and radio altimeter application systems.","PeriodicalId":325599,"journal":{"name":"2017 International Conference on Computer, Electrical & Communication Engineering (ICCECE)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131337303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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