Pub Date : 2013-09-29DOI: 10.1109/EMSOFT.2013.6658583
A. Al-Nayeem, Cheolgi Kim, Woochul Kang, Po-Liang Wu, L. Sha
The Physically-Asynchronous Logically-Synchronous (PALS) system is a recently proposed architectural pattern for cyber-physical systems. It guarantees a logically synchronous design abstraction for real-time distributed computations. In this work, we develop a new middleware, called PALSware, to support an efficient and robust implementation of the PALS system and its extensions. PALSware guarantees consistency in distributed applications by eliminating any asynchronous interactions resulting from distributed clocks and node failures. We present a layered design for this middle-ware that is both reusable in different system architectures and can be extended with architecture-specific solutions for fault management. We demonstrate the middleware for an academic control testbed and show the consistency in a fault injection framework designed for this middleware.
{"title":"Middleware design for Physically-Asynchronous Logically-Synchronous (PALS) systems","authors":"A. Al-Nayeem, Cheolgi Kim, Woochul Kang, Po-Liang Wu, L. Sha","doi":"10.1109/EMSOFT.2013.6658583","DOIUrl":"https://doi.org/10.1109/EMSOFT.2013.6658583","url":null,"abstract":"The Physically-Asynchronous Logically-Synchronous (PALS) system is a recently proposed architectural pattern for cyber-physical systems. It guarantees a logically synchronous design abstraction for real-time distributed computations. In this work, we develop a new middleware, called PALSware, to support an efficient and robust implementation of the PALS system and its extensions. PALSware guarantees consistency in distributed applications by eliminating any asynchronous interactions resulting from distributed clocks and node failures. We present a layered design for this middle-ware that is both reusable in different system architectures and can be extended with architecture-specific solutions for fault management. We demonstrate the middleware for an academic control testbed and show the consistency in a fault injection framework designed for this middleware.","PeriodicalId":325726,"journal":{"name":"2013 Proceedings of the International Conference on Embedded Software (EMSOFT)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125507864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-29DOI: 10.1109/EMSOFT.2013.6658591
D. Harel, Amir Kantor, Guy Katz, Assaf Marron, Lior Mizrahi, Gera Weiss
We present a method and a tool for composing a reactive system and for accompanying the development and documentation process with a proof of its correctness. The approach is based on behavioral programming (BP) and the Z3 SMT solver. We show how program verification can be automated and streamlined by combining properties of individual modules, specified and verified separately, with application-independent specifications both of the BP semantics and of general theories. The method may yield an exponential acceleration of the verification process when compared with model-checking the composite application. We show that formalization of properties of independent modules in preparation for the correctness proofs can be useful as documentation for future development. We view this work as a further step towards making formal correctness proofs standard practice in the development of reactive systems, and carried out by programmers at large.
{"title":"On composing and proving the correctness of reactive behavior","authors":"D. Harel, Amir Kantor, Guy Katz, Assaf Marron, Lior Mizrahi, Gera Weiss","doi":"10.1109/EMSOFT.2013.6658591","DOIUrl":"https://doi.org/10.1109/EMSOFT.2013.6658591","url":null,"abstract":"We present a method and a tool for composing a reactive system and for accompanying the development and documentation process with a proof of its correctness. The approach is based on behavioral programming (BP) and the Z3 SMT solver. We show how program verification can be automated and streamlined by combining properties of individual modules, specified and verified separately, with application-independent specifications both of the BP semantics and of general theories. The method may yield an exponential acceleration of the verification process when compared with model-checking the composite application. We show that formalization of properties of independent modules in preparation for the correctness proofs can be useful as documentation for future development. We view this work as a further step towards making formal correctness proofs standard practice in the development of reactive systems, and carried out by programmers at large.","PeriodicalId":325726,"journal":{"name":"2013 Proceedings of the International Conference on Embedded Software (EMSOFT)","volume":"72 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127371978","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-29DOI: 10.1109/EMSOFT.2013.6658587
Liang Zou, N. Zhan, Shuling Wang, M. Fränzle, S. Qin
Simulink is an industrial de-facto standard for building executable models of embedded systems and their environments, facilitating validation by simulation. Due to the inherent incompleteness of this form of system validation, complementing simulation by formal verification would be desirable. A prerequisite for such an approach is a formal semantics of Simulink's graphical models. In this paper, we show how to encode Simulink diagrams into Hybrid CSP (HCSP), a formal modelling language encoding hybrid system dynamics by means of an extension of CSP. The translation from Simulink to HCSP is fully automatic. We furthermore discuss how to utilize a Hybrid Hoare Logic Prover to verify the translated HCSP models. We demonstrate our approach on a combined scenario originating from the Chinese High-speed Train Control System at Level 3 (CTCS-3).
{"title":"Verifying Simulink diagrams via a Hybrid Hoare Logic Prover","authors":"Liang Zou, N. Zhan, Shuling Wang, M. Fränzle, S. Qin","doi":"10.1109/EMSOFT.2013.6658587","DOIUrl":"https://doi.org/10.1109/EMSOFT.2013.6658587","url":null,"abstract":"Simulink is an industrial de-facto standard for building executable models of embedded systems and their environments, facilitating validation by simulation. Due to the inherent incompleteness of this form of system validation, complementing simulation by formal verification would be desirable. A prerequisite for such an approach is a formal semantics of Simulink's graphical models. In this paper, we show how to encode Simulink diagrams into Hybrid CSP (HCSP), a formal modelling language encoding hybrid system dynamics by means of an extension of CSP. The translation from Simulink to HCSP is fully automatic. We furthermore discuss how to utilize a Hybrid Hoare Logic Prover to verify the translated HCSP models. We demonstrate our approach on a combined scenario originating from the Chinese High-speed Train Control System at Level 3 (CTCS-3).","PeriodicalId":325726,"journal":{"name":"2013 Proceedings of the International Conference on Embedded Software (EMSOFT)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132670711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-29DOI: 10.1109/EMSOFT.2013.6658599
Rajiv Nishtala, D. Mossé, V. Petrucci
Given the wide variety of performance demands for various workloads, the trend in embedded systems is shifting from homogeneous to heterogeneous processors, which have been shown to yield performance and energy saving benefits. A typical heterogeneous processor has cores with different performance and power characteristics, that is, high performance and power hungry (“big”) cores, and low power and performance (“small”) cores. In order to satisfy the memory bandwidth and computation demands of various threads, it is important (albeit challenging) to map threads to cores. Such assignment should take into account that threads could potentially be harmful to each other in the usage of shared resources (e.g., cache, memory). We propose a scheme for dynamic energy-efficient assignment of threads to big/small cores, DIO-E (Distributed Intensity Online-Energy), which is an enhancement of the previously proposed DIO. In contrast to DIO, we take into account both CPU and memory demands of threads to characterize the performance of threads when co-running on the same core at run-time. Our results show that DIO-E improves the energy-delay-squared product (ED2) by 9% (average) over DIO, running on a performance-asymmetric multicore system. Both DIO and DIO-E show about 50% improvement in ED2 over a state-of-the-art solution.
{"title":"Energy-aware thread co-location in heterogeneous multicore processors","authors":"Rajiv Nishtala, D. Mossé, V. Petrucci","doi":"10.1109/EMSOFT.2013.6658599","DOIUrl":"https://doi.org/10.1109/EMSOFT.2013.6658599","url":null,"abstract":"Given the wide variety of performance demands for various workloads, the trend in embedded systems is shifting from homogeneous to heterogeneous processors, which have been shown to yield performance and energy saving benefits. A typical heterogeneous processor has cores with different performance and power characteristics, that is, high performance and power hungry (“big”) cores, and low power and performance (“small”) cores. In order to satisfy the memory bandwidth and computation demands of various threads, it is important (albeit challenging) to map threads to cores. Such assignment should take into account that threads could potentially be harmful to each other in the usage of shared resources (e.g., cache, memory). We propose a scheme for dynamic energy-efficient assignment of threads to big/small cores, DIO-E (Distributed Intensity Online-Energy), which is an enhancement of the previously proposed DIO. In contrast to DIO, we take into account both CPU and memory demands of threads to characterize the performance of threads when co-running on the same core at run-time. Our results show that DIO-E improves the energy-delay-squared product (ED2) by 9% (average) over DIO, running on a performance-asymmetric multicore system. Both DIO and DIO-E show about 50% improvement in ED2 over a state-of-the-art solution.","PeriodicalId":325726,"journal":{"name":"2013 Proceedings of the International Conference on Embedded Software (EMSOFT)","volume":"113 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124344590","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-29DOI: 10.1109/EMSOFT.2013.6658604
Parasara Sridhar Duggirala, S. Mitra, Mahesh Viswanathan
Simulations can help enhance confidence in system designs but they provide almost no formal guarantees. In this paper, we present a simulation-based verification framework for embedded systems described by non-linear, switched systems. In our framework, users are required to annotate the dynamics in each control mode of switched system by something we call a discrepancy function that formally measures the nature of trajectory convergence/divergence of the system. Discrepancy functions generalize other measures of trajectory convergence and divergence like Contraction Metrics and Incremental Lyapunov functions. Exploiting such annotations, we present a sound and relatively complete verification procedure for robustly safe/unsafe systems. We have built a tool based on the framework that is integrated into the popular Simulink/Stateflow modeling environment. Experiments with our prototype tool shows that the approach (a) outperforms other verification tools on standard linear and non-linear benchmarks, (b) scales reasonably to larger dimensional systems and to longer time horizons, and (c) applies to models with diverging trajectories and unknown parameters.
{"title":"Verification of annotated models from executions","authors":"Parasara Sridhar Duggirala, S. Mitra, Mahesh Viswanathan","doi":"10.1109/EMSOFT.2013.6658604","DOIUrl":"https://doi.org/10.1109/EMSOFT.2013.6658604","url":null,"abstract":"Simulations can help enhance confidence in system designs but they provide almost no formal guarantees. In this paper, we present a simulation-based verification framework for embedded systems described by non-linear, switched systems. In our framework, users are required to annotate the dynamics in each control mode of switched system by something we call a discrepancy function that formally measures the nature of trajectory convergence/divergence of the system. Discrepancy functions generalize other measures of trajectory convergence and divergence like Contraction Metrics and Incremental Lyapunov functions. Exploiting such annotations, we present a sound and relatively complete verification procedure for robustly safe/unsafe systems. We have built a tool based on the framework that is integrated into the popular Simulink/Stateflow modeling environment. Experiments with our prototype tool shows that the approach (a) outperforms other verification tools on standard linear and non-linear benchmarks, (b) scales reasonably to larger dimensional systems and to longer time horizons, and (c) applies to models with diverging trajectories and unknown parameters.","PeriodicalId":325726,"journal":{"name":"2013 Proceedings of the International Conference on Embedded Software (EMSOFT)","volume":"142 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131936288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-29DOI: 10.1109/EMSOFT.2013.6658596
Andrea Baldovin, E. Mezzetti, T. Vardanega
Preemption is a key factor against architectural coupling in concurrent systems. The whole verification process of real-time systems postulates composability in multiple dimensions, including time. As coupling wrecks composability, the design of real-time systems really needs preemption. However preemption effects complicate feasibility analysis or make it more pessimistic. Hence methods that limit preemptions without affecting feasibility are attractive. State-of-the-art approaches to limited preemption, however, do not treat resource sharing with the importance that it deserves. The placement of non-preemptive regions - and their interactions with shared resources - should not become a design problem, but rather stay as an implementation level feature that does not backtrack to the design space. In this paper we present a refinement to the state-of-the-art limited preemption model that addresses the interaction with resource sharing, and discuss a kernel implementation that uses run-time knowledge to warrant safe and efficient overlaps between critical sections and non-preemptive regions. Experimental results prove the effectiveness of the proposed solution.
{"title":"Limited preemptive scheduling of non-independent task sets","authors":"Andrea Baldovin, E. Mezzetti, T. Vardanega","doi":"10.1109/EMSOFT.2013.6658596","DOIUrl":"https://doi.org/10.1109/EMSOFT.2013.6658596","url":null,"abstract":"Preemption is a key factor against architectural coupling in concurrent systems. The whole verification process of real-time systems postulates composability in multiple dimensions, including time. As coupling wrecks composability, the design of real-time systems really needs preemption. However preemption effects complicate feasibility analysis or make it more pessimistic. Hence methods that limit preemptions without affecting feasibility are attractive. State-of-the-art approaches to limited preemption, however, do not treat resource sharing with the importance that it deserves. The placement of non-preemptive regions - and their interactions with shared resources - should not become a design problem, but rather stay as an implementation level feature that does not backtrack to the design space. In this paper we present a refinement to the state-of-the-art limited preemption model that addresses the interaction with resource sharing, and discuss a kernel implementation that uses run-time knowledge to warrant safe and efficient overlaps between critical sections and non-preemptive regions. Experimental results prove the effectiveness of the proposed solution.","PeriodicalId":325726,"journal":{"name":"2013 Proceedings of the International Conference on Embedded Software (EMSOFT)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122307484","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-29DOI: 10.1109/EMSOFT.2013.6658600
Eva Darulova, Viktor Kunčak, R. Majumdar, I. Saha
Several problems in the implementations of control systems, signal-processing systems, and scientific computing systems reduce to compiling a polynomial expression over the reals into an imperative program using fixed-point arithmetic. Fixed-point arithmetic only approximates real values, and its operators do not have the fundamental properties of real arithmetic, such as associativity. Consequently, a naive compilation process can yield a program that significantly deviates from the real polynomial, whereas a different order of evaluation can result in a program that is close to the real value on all inputs in its domain. We present a compilation scheme for real-valued arithmetic expressions to fixed-point arithmetic programs. Given a real-valued polynomial expression t, we find an expression t' that is equivalent to t over the reals, but whose implementation as a series of fixed-point operations minimizes the error between the fixed-point value and the value of t over the space of all inputs. We show that the corresponding decision problem, checking whether there is an implementation t' of t whose error is less than a given constant, is NP-hard. We then propose a solution technique based on genetic programming. Our technique evaluates the fitness of each candidate program using a static analysis based on affine arithmetic. We show that our tool can significantly reduce the error in the fixed-point implementation on a set of linear control system benchmarks. For example, our tool found implementations whose errors are only one half of the errors in the original fixed-point expressions.
{"title":"Synthesis of fixed-point programs","authors":"Eva Darulova, Viktor Kunčak, R. Majumdar, I. Saha","doi":"10.1109/EMSOFT.2013.6658600","DOIUrl":"https://doi.org/10.1109/EMSOFT.2013.6658600","url":null,"abstract":"Several problems in the implementations of control systems, signal-processing systems, and scientific computing systems reduce to compiling a polynomial expression over the reals into an imperative program using fixed-point arithmetic. Fixed-point arithmetic only approximates real values, and its operators do not have the fundamental properties of real arithmetic, such as associativity. Consequently, a naive compilation process can yield a program that significantly deviates from the real polynomial, whereas a different order of evaluation can result in a program that is close to the real value on all inputs in its domain. We present a compilation scheme for real-valued arithmetic expressions to fixed-point arithmetic programs. Given a real-valued polynomial expression t, we find an expression t' that is equivalent to t over the reals, but whose implementation as a series of fixed-point operations minimizes the error between the fixed-point value and the value of t over the space of all inputs. We show that the corresponding decision problem, checking whether there is an implementation t' of t whose error is less than a given constant, is NP-hard. We then propose a solution technique based on genetic programming. Our technique evaluates the fitness of each candidate program using a static analysis based on affine arithmetic. We show that our tool can significantly reduce the error in the fixed-point implementation on a set of linear control system benchmarks. For example, our tool found implementations whose errors are only one half of the errors in the original fixed-point expressions.","PeriodicalId":325726,"journal":{"name":"2013 Proceedings of the International Conference on Embedded Software (EMSOFT)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125912637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-29DOI: 10.1109/EMSOFT.2013.6658593
D. Chu, J. Jaffar
We consider the problem of bounding the worst-case resource usage of programs, where assertions about valid program executions may be enforced at selected program points. It is folklore that to be precise, path-sensitivity (up to loops) is needed. This entails unrolling loops in the manner of symbolic simulation. To be tractable, however, the treatment of the individual loop iterations must be greedy in the sense once analysis is finished on one iteration, we cannot backtrack to change it. We show that under these conditions, enforcing assertions produces unsound results. The fundamental reason is that complying with assertions requires the analysis to be fully sensitive (also with loops) wrt. the assertion variables. We then present an algorithm where the treatment of each loop is separated in two phases. The first phase uses a greedy strategy in unrolling the loop. This phase explores what is conceptually a symbolic execution tree, which is of enormous size, while eliminates infeasible paths and dominated paths that guaranteed not to contribute to the worst case bound. A compact representation is produced at the end of this phase. Finally, the second phase attacks the remaining problem, to determine the worst-case path in the simplified tree, excluding all paths that violate the assertions from bound calculation. Scalability, in both phases, is achieved via an adaptation of a dynamic programming algorithm.
{"title":"Path-sensitive resource analysis compliant with assertions","authors":"D. Chu, J. Jaffar","doi":"10.1109/EMSOFT.2013.6658593","DOIUrl":"https://doi.org/10.1109/EMSOFT.2013.6658593","url":null,"abstract":"We consider the problem of bounding the worst-case resource usage of programs, where assertions about valid program executions may be enforced at selected program points. It is folklore that to be precise, path-sensitivity (up to loops) is needed. This entails unrolling loops in the manner of symbolic simulation. To be tractable, however, the treatment of the individual loop iterations must be greedy in the sense once analysis is finished on one iteration, we cannot backtrack to change it. We show that under these conditions, enforcing assertions produces unsound results. The fundamental reason is that complying with assertions requires the analysis to be fully sensitive (also with loops) wrt. the assertion variables. We then present an algorithm where the treatment of each loop is separated in two phases. The first phase uses a greedy strategy in unrolling the loop. This phase explores what is conceptually a symbolic execution tree, which is of enormous size, while eliminates infeasible paths and dominated paths that guaranteed not to contribute to the worst case bound. A compact representation is produced at the end of this phase. Finally, the second phase attacks the remaining problem, to determine the worst-case path in the simplified tree, excluding all paths that violate the assertions from bound calculation. Scalability, in both phases, is achieved via an adaptation of a dynamic programming algorithm.","PeriodicalId":325726,"journal":{"name":"2013 Proceedings of the International Conference on Embedded Software (EMSOFT)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114898084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-29DOI: 10.1109/EMSOFT.2013.6658582
B. Mazumder, J. Hallstrom
We present an incremental code update strategy used to efficiently reprogram wireless sensor nodes. We adapt a linear space and quadratic time algorithm (Hirschberg's algorithm) for computing maximal common subsequences to build an edit map specifying an edit sequence, required to transform the code running in a sensor network to a new code image. We then present a heuristic-based optimization strategy for efficient edit script encoding to reduce th.e edit map size. Finally, we present experimental results to demonstrate the reduction in data size to reprogram a network using this mechanism. The approach achieves reductions of 99.987% for simple changes, and between 86.95% and 94.58% for more complex changes, compared to full image transmissions - leading to significantly lower energy costs for wireless sensor network reprogramming. We compare the results with reductions achieved by other incremental update strategies described in prior work.
{"title":"An efficient code update solution for wireless sensor network reprogramming","authors":"B. Mazumder, J. Hallstrom","doi":"10.1109/EMSOFT.2013.6658582","DOIUrl":"https://doi.org/10.1109/EMSOFT.2013.6658582","url":null,"abstract":"We present an incremental code update strategy used to efficiently reprogram wireless sensor nodes. We adapt a linear space and quadratic time algorithm (Hirschberg's algorithm) for computing maximal common subsequences to build an edit map specifying an edit sequence, required to transform the code running in a sensor network to a new code image. We then present a heuristic-based optimization strategy for efficient edit script encoding to reduce th.e edit map size. Finally, we present experimental results to demonstrate the reduction in data size to reprogram a network using this mechanism. The approach achieves reductions of 99.987% for simple changes, and between 86.95% and 94.58% for more complex changes, compared to full image transmissions - leading to significantly lower energy costs for wireless sensor network reprogramming. We compare the results with reductions achieved by other incremental update strategies described in prior work.","PeriodicalId":325726,"journal":{"name":"2013 Proceedings of the International Conference on Embedded Software (EMSOFT)","volume":"175 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115267838","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-09-29DOI: 10.1109/EMSOFT.2013.6658584
Yeong-Jae Woo, Jin-Soo Kim
NAND flash-based solid state drives (SSDs) are replacing magnetic disks because of their fast random access performance, shock resistance, and low power consumption. However, the number of program and erase cycles that can be performed on NAND flash is limited. To overcome this limitation, SSDs require a sophisticated wear-leveling algorithm which distributes program/erase cycles evenly across all flash blocks. While most of existing wear-leveling algorithms are only based on the erase counts of flash blocks, our empirical study indicates that the erase count alone is not a good wear index which tells us how much a flash block is worn out. This paper proposes a new wear index for MLC NAND flash memory which takes into account more diverse properties of NAND flash memory. To show the effectiveness of the proposed wear index, we also develop a wear-leveling algorithm, named Equalizer. In our evaluation with three realistic workloads, Equalizer based on the proposed wear index improves the effective lifetime of SSDs by up to 145% compared to the existing wear-leveling technique based on the erase count.
{"title":"Diversifying wear index for MLC NAND flash memory to extend the lifetime of SSDs","authors":"Yeong-Jae Woo, Jin-Soo Kim","doi":"10.1109/EMSOFT.2013.6658584","DOIUrl":"https://doi.org/10.1109/EMSOFT.2013.6658584","url":null,"abstract":"NAND flash-based solid state drives (SSDs) are replacing magnetic disks because of their fast random access performance, shock resistance, and low power consumption. However, the number of program and erase cycles that can be performed on NAND flash is limited. To overcome this limitation, SSDs require a sophisticated wear-leveling algorithm which distributes program/erase cycles evenly across all flash blocks. While most of existing wear-leveling algorithms are only based on the erase counts of flash blocks, our empirical study indicates that the erase count alone is not a good wear index which tells us how much a flash block is worn out. This paper proposes a new wear index for MLC NAND flash memory which takes into account more diverse properties of NAND flash memory. To show the effectiveness of the proposed wear index, we also develop a wear-leveling algorithm, named Equalizer. In our evaluation with three realistic workloads, Equalizer based on the proposed wear index improves the effective lifetime of SSDs by up to 145% compared to the existing wear-leveling technique based on the erase count.","PeriodicalId":325726,"journal":{"name":"2013 Proceedings of the International Conference on Embedded Software (EMSOFT)","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121431963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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