Pub Date : 2015-12-07DOI: 10.1109/PATMOS.2015.7347590
J. Innocenti, L. Welter, N. Borrel, F. Julien, J. Portal, J. Sonzogni, L. Lopez, P. Masson, S. Niel, P. Dreux, Julia Castellan
This paper presents an original solution to decrease significantly the power consumption of CMOS digital circuits. The supply voltage VDD and the MOSFET width are reduced and allow lowering the dynamic current of circuits by 25%. A CAD-to-mask script was developed in order to automatically reduce all physical widths of low-voltage transistors used in standard cells. With this operation, no additional redesign of standard cells was necessary. Moreover, a new optimized process based on e-NVM (embedded Non-Volatile Memory) CMOS 80 nm technology is developed. ION current is improved by 15% and 50% for NMOS and PMOS transistors, respectively. This, let us decrease dynamic current without impacting circuit performance. Finally, the static current of the circuit is reduced by 60% through design and process optimization.
{"title":"Dynamic current reduction of CMOS digital circuits through design and process optimization","authors":"J. Innocenti, L. Welter, N. Borrel, F. Julien, J. Portal, J. Sonzogni, L. Lopez, P. Masson, S. Niel, P. Dreux, Julia Castellan","doi":"10.1109/PATMOS.2015.7347590","DOIUrl":"https://doi.org/10.1109/PATMOS.2015.7347590","url":null,"abstract":"This paper presents an original solution to decrease significantly the power consumption of CMOS digital circuits. The supply voltage VDD and the MOSFET width are reduced and allow lowering the dynamic current of circuits by 25%. A CAD-to-mask script was developed in order to automatically reduce all physical widths of low-voltage transistors used in standard cells. With this operation, no additional redesign of standard cells was necessary. Moreover, a new optimized process based on e-NVM (embedded Non-Volatile Memory) CMOS 80 nm technology is developed. ION current is improved by 15% and 50% for NMOS and PMOS transistors, respectively. This, let us decrease dynamic current without impacting circuit performance. Finally, the static current of the circuit is reduced by 60% through design and process optimization.","PeriodicalId":325869,"journal":{"name":"2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"186 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133672994","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-07DOI: 10.1109/PATMOS.2015.7347596
Rodrigo Fonseca Rocha Soares, F. Sill, D. Timmermann
The definition of parameters of integrated circuit technologies is driven by technological constraints as well as by intended applications. In case of the latter, opposing criteria, like design delay, power consumptions and area, have to be considered. Common approaches focus usually on the analysis based on selected and isolated cells. However, this might not represent the exact impact of a technology parameter on actual designs. Hence, this work proposes a flow for the exploration of technology parameter values that considers the application in real designs. Additionally, the proposed approach allows the comparison of different technology generation with a reasonable effort. Results indicate an improvement of the predictions of up to 46 % in comparison to single cell analysis. Further, the applicability of the approach is successfully evaluated using a predictive technology based on Carbon nanotubes.
{"title":"Exploration of technology parameter values of integrated circuit technologies","authors":"Rodrigo Fonseca Rocha Soares, F. Sill, D. Timmermann","doi":"10.1109/PATMOS.2015.7347596","DOIUrl":"https://doi.org/10.1109/PATMOS.2015.7347596","url":null,"abstract":"The definition of parameters of integrated circuit technologies is driven by technological constraints as well as by intended applications. In case of the latter, opposing criteria, like design delay, power consumptions and area, have to be considered. Common approaches focus usually on the analysis based on selected and isolated cells. However, this might not represent the exact impact of a technology parameter on actual designs. Hence, this work proposes a flow for the exploration of technology parameter values that considers the application in real designs. Additionally, the proposed approach allows the comparison of different technology generation with a reasonable effort. Results indicate an improvement of the predictions of up to 46 % in comparison to single cell analysis. Further, the applicability of the approach is successfully evaluated using a predictive technology based on Carbon nanotubes.","PeriodicalId":325869,"journal":{"name":"2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125328493","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-12-07DOI: 10.1109/PATMOS.2015.7347586
S. Sarangi, Rajshekar Kalayappan, Prathmesh Kallurkar, Seep Goel, E. Peter
In this paper, we present the design of a new Java based, cycle-accurate, heterogeneous architectural simulator, Tejas. Tejas is a trace driven simulator, which is platform-independent. It can simulate binaries in any ISA and corresponding to virtually any operating system. It can itself run on virtually any machine. It is one of the fastest cycle accurate simulators available in academia. This is achieved through employing optimized data structures, improving the simulator's cache locality, and reducing the amount of wasteful work done. Tejas offers a rich library of architectural features that are modular and highly configurable. Tejas has been validated against real hardware (Dell PowerEdge R620 server) and has been shown to be more accurate than some of the most popular architectural simulators.
{"title":"Tejas: A java based versatile micro-architectural simulator","authors":"S. Sarangi, Rajshekar Kalayappan, Prathmesh Kallurkar, Seep Goel, E. Peter","doi":"10.1109/PATMOS.2015.7347586","DOIUrl":"https://doi.org/10.1109/PATMOS.2015.7347586","url":null,"abstract":"In this paper, we present the design of a new Java based, cycle-accurate, heterogeneous architectural simulator, Tejas. Tejas is a trace driven simulator, which is platform-independent. It can simulate binaries in any ISA and corresponding to virtually any operating system. It can itself run on virtually any machine. It is one of the fastest cycle accurate simulators available in academia. This is achieved through employing optimized data structures, improving the simulator's cache locality, and reducing the amount of wasteful work done. Tejas offers a rich library of architectural features that are modular and highly configurable. Tejas has been validated against real hardware (Dell PowerEdge R620 server) and has been shown to be more accurate than some of the most popular architectural simulators.","PeriodicalId":325869,"journal":{"name":"2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-12-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126535475","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/PATMOS.2015.7347587
Soundous Chairat, E. Beigné, M. Belleville
This paper introduces a novel asynchronous communication network for reconfiguration purposes inside an adaptive Wireless Sensor Network (WSN) Node. To insure an efficient energy consumption, both analog and digital reconfigurable blocks, able to adapt their performances depending on the available energy budget, are integrated in such a node. The proposed communication network serves to pass along configuration data between the microcontroller and the adaptive circuits, which have different speed and latency constraints than the functional data. This article presents the current state of the art for on and off-chip communication networks, an analysis of which topology is the most suitable in this application, and a comparison between two possible topologies.
{"title":"Dedicated network for distributed configuration in a mixed-signal Wireless Sensor Node circuit","authors":"Soundous Chairat, E. Beigné, M. Belleville","doi":"10.1109/PATMOS.2015.7347587","DOIUrl":"https://doi.org/10.1109/PATMOS.2015.7347587","url":null,"abstract":"This paper introduces a novel asynchronous communication network for reconfiguration purposes inside an adaptive Wireless Sensor Network (WSN) Node. To insure an efficient energy consumption, both analog and digital reconfigurable blocks, able to adapt their performances depending on the available energy budget, are integrated in such a node. The proposed communication network serves to pass along configuration data between the microcontroller and the adaptive circuits, which have different speed and latency constraints than the functional data. This article presents the current state of the art for on and off-chip communication networks, an analysis of which topology is the most suitable in this application, and a comparison between two possible topologies.","PeriodicalId":325869,"journal":{"name":"2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115098676","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/PATMOS.2015.7347602
Victor Lira, E. Tavares
Network virtualization has been pointed out as a promising technique to tackle Internet's current ossification and to mitigate sustainability issues related to energy consumption. A critical issue is the virtual network embedding (VNE), due to the NP-hard nature of the problem. Thus, several heuristics have been proposed aiming to achieve efficient allocations. In this paper, we extend the VNE problem to consider dependability and energy consumption issues, utilizing an approach based on GRASP metaheuristic. Experimental results demonstrate energy savings obtained with the proposed approach over representative VNE techniques. The results also present a trade-off between energy consumption, availability and cost.
{"title":"Energy-aware mapping for dependable virtual networks","authors":"Victor Lira, E. Tavares","doi":"10.1109/PATMOS.2015.7347602","DOIUrl":"https://doi.org/10.1109/PATMOS.2015.7347602","url":null,"abstract":"Network virtualization has been pointed out as a promising technique to tackle Internet's current ossification and to mitigate sustainability issues related to energy consumption. A critical issue is the virtual network embedding (VNE), due to the NP-hard nature of the problem. Thus, several heuristics have been proposed aiming to achieve efficient allocations. In this paper, we extend the VNE problem to consider dependability and energy consumption issues, utilizing an approach based on GRASP metaheuristic. Experimental results demonstrate energy savings obtained with the proposed approach over representative VNE techniques. The results also present a trade-off between energy consumption, availability and cost.","PeriodicalId":325869,"journal":{"name":"2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117057257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-09-01DOI: 10.1109/PATMOS.2015.7347603
S. Ghissoni, E. Costa, R. Reis
This paper reports the reuse of smaller optimized FFT (Fast Fourier Transform) blocks for the realization of larger power efficient radix-2 FFTs. The smaller FFT blocks use Constant Matrix Multiplication (CMM) method along its stages that are implemented with Carry Save Adders (CSA). The use of CMM at gate level enables the replacement of the multiplication operations by addition/subtractions and shifts for each stage of the real and imaginary parts of the FFT butterflies. The larger FFT is obtained through the composition of the optimized smaller FFT modules. Through a control unit, the partial decomposition of coefficients allows the computation of all coefficients necessary for the larger FFTs. The use of pipeline into the stages of the FFT enabled gains in both power and performance when compared with the previous non-pipelined solution. Moreover, the results showed that, when using pipeline, our solution is more delay and power efficient when compared with prominent works from the literature.
{"title":"Reusing smaller optimized FFT blocks for the realization of larger power-efficient radix-2 FFTs","authors":"S. Ghissoni, E. Costa, R. Reis","doi":"10.1109/PATMOS.2015.7347603","DOIUrl":"https://doi.org/10.1109/PATMOS.2015.7347603","url":null,"abstract":"This paper reports the reuse of smaller optimized FFT (Fast Fourier Transform) blocks for the realization of larger power efficient radix-2 FFTs. The smaller FFT blocks use Constant Matrix Multiplication (CMM) method along its stages that are implemented with Carry Save Adders (CSA). The use of CMM at gate level enables the replacement of the multiplication operations by addition/subtractions and shifts for each stage of the real and imaginary parts of the FFT butterflies. The larger FFT is obtained through the composition of the optimized smaller FFT modules. Through a control unit, the partial decomposition of coefficients allows the computation of all coefficients necessary for the larger FFTs. The use of pipeline into the stages of the FFT enabled gains in both power and performance when compared with the previous non-pipelined solution. Moreover, the results showed that, when using pipeline, our solution is more delay and power efficient when compared with prominent works from the literature.","PeriodicalId":325869,"journal":{"name":"2015 25th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131103792","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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