The accurate modeling of on-chip inductors is very important and a necessity in today's RF circuit design. This paper presents an accurate modeling method for on-chip inductors which includes various parameters and parasitic. A number of important parameters are the skin effect, mutual inductance between any two parallel wires and parasitic capacitances resulted from the proximity effect between wires.
{"title":"A comprehensive model for on-chip spiral inductors","authors":"B. K. Hosseinieh, N. Masoumi","doi":"10.1109/IWSOC.2005.6","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.6","url":null,"abstract":"The accurate modeling of on-chip inductors is very important and a necessity in today's RF circuit design. This paper presents an accurate modeling method for on-chip inductors which includes various parameters and parasitic. A number of important parameters are the skin effect, mutual inductance between any two parallel wires and parasitic capacitances resulted from the proximity effect between wires.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132595597","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Performance estimation of processor is important to select the right processor for an application. Poorly chosen processors can either under perform very badly or over perform but with high cost. Most previous work on performance estimation are based on generating the development tools, i.e., compilers, assemblers etc from a processor description file and then additionally generating an instruction set simulator to get the performance. In this work we present a simpler strategy for performance estimation. We propose an estimation technique based on the intermediate format of an application. The estimation process does not require the generation of all the development tools as in the prevalent methods. As a result our method is not only cheaper but also faster.
{"title":"Practical techniques for performance estimation of processors","authors":"A. Ray, T. Srikanthan, W. Jigang","doi":"10.1109/IWSOC.2005.94","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.94","url":null,"abstract":"Performance estimation of processor is important to select the right processor for an application. Poorly chosen processors can either under perform very badly or over perform but with high cost. Most previous work on performance estimation are based on generating the development tools, i.e., compilers, assemblers etc from a processor description file and then additionally generating an instruction set simulator to get the performance. In this work we present a simpler strategy for performance estimation. We propose an estimation technique based on the intermediate format of an application. The estimation process does not require the generation of all the development tools as in the prevalent methods. As a result our method is not only cheaper but also faster.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130499237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Design verification is taking an increasing proportion of the design cycle of system-on-chip (SoC) designs. Designers spend up to 70% of their time developing and running tests to verify the functionality of their systems based in 2004 IC/ASIC Functional Verification Study (2005). Running regression suites against the design can take up to several years of CPU time to complete. In this paper we show how existing software code bases can be used to reduce the time to develop and execute verification tests. These techniques can be applied to both unit and system level verification. As shown in various hardware/software co-verification tools as stated in R. Klein (1996) and M. Stanbro (1998), the overall load on a simulation can be reduced by eliminating code and data references from the set of bus cycles generated by the processor model. These same techniques can be applied by hardware designers and verification engineers to use firmware, hardware diagnostics, and other software as a basis for creating functional verification tests. This software is often available from prior versions of the design or other groups on the design team. Simulation run-times can be reduced by partitioning the processor's memory space between the logic simulation and the processor model.
{"title":"Accelerating functional simulation for processor based designs","authors":"R. Klein, Tomasz Piekarz","doi":"10.1109/IWSOC.2005.34","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.34","url":null,"abstract":"Design verification is taking an increasing proportion of the design cycle of system-on-chip (SoC) designs. Designers spend up to 70% of their time developing and running tests to verify the functionality of their systems based in 2004 IC/ASIC Functional Verification Study (2005). Running regression suites against the design can take up to several years of CPU time to complete. In this paper we show how existing software code bases can be used to reduce the time to develop and execute verification tests. These techniques can be applied to both unit and system level verification. As shown in various hardware/software co-verification tools as stated in R. Klein (1996) and M. Stanbro (1998), the overall load on a simulation can be reduced by eliminating code and data references from the set of bus cycles generated by the processor model. These same techniques can be applied by hardware designers and verification engineers to use firmware, hardware diagnostics, and other software as a basis for creating functional verification tests. This software is often available from prior versions of the design or other groups on the design team. Simulation run-times can be reduced by partitioning the processor's memory space between the logic simulation and the processor model.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123502317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper analyzes the conversion time of a time domain digital pixel sensor based on pulse width modulation scheme. Two quantization schemes are studied namely the uniform time domain (UQ) and the non uniform time domain (NUQ) quantizers. It is shown that the latter scheme not only permits to linearize the non-linear response of a PWM vision sensor but also allows to significantly speed-up the conversion time particularly for wide dynamic range and lower coding resolution. The VLSI architecture of a reconfigurable DPS for variable spatial and coding resolutions is proposed in 1-poly, 5 metal CMOS 0.35/spl mu/m n-well process.
{"title":"Conversion time analysis of time domain digital pixel sensor in uniform and non-uniform quantizers","authors":"A. Bermak","doi":"10.1109/IWSOC.2005.47","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.47","url":null,"abstract":"This paper analyzes the conversion time of a time domain digital pixel sensor based on pulse width modulation scheme. Two quantization schemes are studied namely the uniform time domain (UQ) and the non uniform time domain (NUQ) quantizers. It is shown that the latter scheme not only permits to linearize the non-linear response of a PWM vision sensor but also allows to significantly speed-up the conversion time particularly for wide dynamic range and lower coding resolution. The VLSI architecture of a reconfigurable DPS for variable spatial and coding resolutions is proposed in 1-poly, 5 metal CMOS 0.35/spl mu/m n-well process.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123547476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
An ultra low-voltage (0.65 V), 5 GHz low noise amplifier (LNA) has been designed, laid out and simulated using Spectre simulator in a standard TSMC 0.18/spl mu/m CMOS technology. The proposed LNA achieves better performance than conventional cascode topology and are confirmed by simulation results. The LNA provides a high gain of 20 dB, a noise figure of 1.4 dB, power dissipation of 1.9 mW from a 0.65 V power supply. To the best of author's knowledge this is the lowest voltage supply CMOS LNA design reported to date.
{"title":"A 0.65V, 1.9mW CMOS low-noise amplifier at 5GHz","authors":"Yanjie Wang, M. Z. Khan, K. Iniewski","doi":"10.1109/IWSOC.2005.2","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.2","url":null,"abstract":"An ultra low-voltage (0.65 V), 5 GHz low noise amplifier (LNA) has been designed, laid out and simulated using Spectre simulator in a standard TSMC 0.18/spl mu/m CMOS technology. The proposed LNA achieves better performance than conventional cascode topology and are confirmed by simulation results. The LNA provides a high gain of 20 dB, a noise figure of 1.4 dB, power dissipation of 1.9 mW from a 0.65 V power supply. To the best of author's knowledge this is the lowest voltage supply CMOS LNA design reported to date.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116511854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a case study of a single-chip 3G WCDMA/FDD base station implementation based on a circuit-switched network on chip. As the amount of transistors on a chip continues to increase, so does the possibility to integrate more functionality onto every chip. By combining general-purpose and application-specific hardware, it is possible to integrate the complete baseband part of a 3G base station on a single chip. Such a single-chip base station has been modeled from a communication perspective without full implementations of the processing elements. The system has been scheduled and implemented as a traffic model for a network on chip simulator. Simulation results show perfect adherence to the schedule already at a network clock frequency of 75 MHz. The overall network usage is relatively low except for the area closest to the radio interfaces. This allows for other messages, e.g. control related, to be transported over the network during the gaps in the communication schedule.
{"title":"Design, mapping, and simulations of a 3G WCDMA/FDD base station using network on chip","authors":"D. Wiklund, Dake Liu","doi":"10.1109/IWSOC.2005.50","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.50","url":null,"abstract":"This paper presents a case study of a single-chip 3G WCDMA/FDD base station implementation based on a circuit-switched network on chip. As the amount of transistors on a chip continues to increase, so does the possibility to integrate more functionality onto every chip. By combining general-purpose and application-specific hardware, it is possible to integrate the complete baseband part of a 3G base station on a single chip. Such a single-chip base station has been modeled from a communication perspective without full implementations of the processing elements. The system has been scheduled and implemented as a traffic model for a network on chip simulator. Simulation results show perfect adherence to the schedule already at a network clock frequency of 75 MHz. The overall network usage is relatively low except for the area closest to the radio interfaces. This allows for other messages, e.g. control related, to be transported over the network during the gaps in the communication schedule.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127745433","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a design of 8-bit /spl times/ 8-bit unsigned multiplier for high-speed digital signal processing (DSP) applications. High-speed is achieved by a new architecture implementing our earlier multiplication technique based in A. Khatibzadeh et a. (2005) in conventional register pipelining at the bit level. The multiplier is designed employing 0.18-/spl mu/m CMOS process. HSPICE simulation results indicate that the proposed design performs multiplication rates up to 6 GHz under the supply voltage of 1.8V or 3.3 GHz under 1.4 V with about 25% times less power consumption. The comparison with Baugh-Wooley multiplier with same topology of the common elements shows that our multiplier consumes only 63% of the power of Baugh-Wooley multiplier with 40% reduction in latency.
本文提出了一种用于高速数字信号处理(DSP)应用的8位/ sp1倍/ 8位无符号乘法器的设计。高速是通过一种新的架构实现的，该架构基于a. Khatibzadeh等人(2005)在位级的传统寄存器流水线中实现了我们早期的乘法技术。该乘法器采用0.18-/spl μ m CMOS工艺设计。HSPICE仿真结果表明，该设计在电源电压为1.8V或3.3 GHz时可实现高达6 GHz的倍增速率，功耗降低约25%。与具有相同公共元素拓扑的Baugh-Wooley乘法器的比较表明，我们的乘法器功耗仅为Baugh-Wooley乘法器的63%，延迟减少40%。
{"title":"A novel design of a 6-GHz 8 /spl times/ 8-b pipelined multiplier","authors":"A. Khatibzadeh, K. Raahemifar","doi":"10.1109/IWSOC.2005.20","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.20","url":null,"abstract":"This paper presents a design of 8-bit /spl times/ 8-bit unsigned multiplier for high-speed digital signal processing (DSP) applications. High-speed is achieved by a new architecture implementing our earlier multiplication technique based in A. Khatibzadeh et a. (2005) in conventional register pipelining at the bit level. The multiplier is designed employing 0.18-/spl mu/m CMOS process. HSPICE simulation results indicate that the proposed design performs multiplication rates up to 6 GHz under the supply voltage of 1.8V or 3.3 GHz under 1.4 V with about 25% times less power consumption. The comparison with Baugh-Wooley multiplier with same topology of the common elements shows that our multiplier consumes only 63% of the power of Baugh-Wooley multiplier with 40% reduction in latency.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128000807","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
C. Chiu, Chun-Chieh Chang, Shihua Chen, Hou-Cheng Tzeng, Ming-Chang Du, Yu-Ho Hsu, Jen-Ming Wu, K. Feng
For the first time, we implemented a reconfigurable load-balanced TDM switch for high speed networking applications. An N/spl times/N TDM switch could be constructed recursively from the proposed switch modules to achieve switching capacity of hundred gigabits per second or higher. Two architectures were implemented. One was an 8/spl times/8 TDM switch with serial input/output ports and embedded 8/10B CODECs for Ethernet applications. The other was a dual-mode 8/spl times/8 or 64/spl times/64 TDM switch with parallel ports. A novel testing circuit was also implemented to easily verify switching results. Our results showed a 20 Gbps switching capacity for the 8/spl times/8 TDM switch with parallel input and output ports and a 640 Gbps capacity for the 64/spl times/64 switch. All implementation were based on the 0.18 /spl mu/m CMOS technology.
{"title":"A 20 Gbps scalable load-balanced TDM switch with CODEC for high speed networking applications","authors":"C. Chiu, Chun-Chieh Chang, Shihua Chen, Hou-Cheng Tzeng, Ming-Chang Du, Yu-Ho Hsu, Jen-Ming Wu, K. Feng","doi":"10.1109/IWSOC.2005.4","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.4","url":null,"abstract":"For the first time, we implemented a reconfigurable load-balanced TDM switch for high speed networking applications. An N/spl times/N TDM switch could be constructed recursively from the proposed switch modules to achieve switching capacity of hundred gigabits per second or higher. Two architectures were implemented. One was an 8/spl times/8 TDM switch with serial input/output ports and embedded 8/10B CODECs for Ethernet applications. The other was a dual-mode 8/spl times/8 or 64/spl times/64 TDM switch with parallel ports. A novel testing circuit was also implemented to easily verify switching results. Our results showed a 20 Gbps switching capacity for the 8/spl times/8 TDM switch with parallel input and output ports and a 640 Gbps capacity for the 64/spl times/64 switch. All implementation were based on the 0.18 /spl mu/m CMOS technology.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126660970","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
It is a challenge to debug the software and hardware in the SOC for that neither the software nor the hardware is error-free. By combining the emulator and the simulator, with the new software debug engine, the new bus status monitor, and the new checkpoint technology, the high speed, easy-used software/hardware co-debugging environment is presented in this paper.
{"title":"The software-hardware co-debug environment with emulator","authors":"Baodong Yu, X. Zou","doi":"10.1109/IWSOC.2005.105","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.105","url":null,"abstract":"It is a challenge to debug the software and hardware in the SOC for that neither the software nor the hardware is error-free. By combining the emulator and the simulator, with the new software debug engine, the new bus status monitor, and the new checkpoint technology, the high speed, easy-used software/hardware co-debugging environment is presented in this paper.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130378497","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The open model for solutions development is quickly extending from software to other technology areas, such as hardware and services. Specifically, just as open source has spawned a revolution in the technical, business, and legal model for software, open hardware will provide a swell of collaborative innovation that will create entirely new markets and provide significant business benefits to the most creative, most reliable, and most adaptable semiconductor, EDA, system-on-chip (SoC) and systems houses. The open-source software stack with Linux as its cornerstone is increasingly the preferred choice for newly venture-funded companies. Open hardware will also change the world of SoC venture investing. While the degree of openness and the business model may vary, SoC products have to be increasingly developed through a collaborative model that helps assemble IP blocks and services from multiple sources. In this paper we describe the open standards model for hardware, chip, and tool innovation, and we argue the a systematic IP valuation methodology will help the success of this environment, in that it will allow each member of the value chain - especially small VC-backed companies - to capture enough value to desire to participate.
{"title":"Open HW, open design SW, and the VC ecosystem dilemma","authors":"J. Carballo","doi":"10.1109/IWSOC.2005.88","DOIUrl":"https://doi.org/10.1109/IWSOC.2005.88","url":null,"abstract":"The open model for solutions development is quickly extending from software to other technology areas, such as hardware and services. Specifically, just as open source has spawned a revolution in the technical, business, and legal model for software, open hardware will provide a swell of collaborative innovation that will create entirely new markets and provide significant business benefits to the most creative, most reliable, and most adaptable semiconductor, EDA, system-on-chip (SoC) and systems houses. The open-source software stack with Linux as its cornerstone is increasingly the preferred choice for newly venture-funded companies. Open hardware will also change the world of SoC venture investing. While the degree of openness and the business model may vary, SoC products have to be increasingly developed through a collaborative model that helps assemble IP blocks and services from multiple sources. In this paper we describe the open standards model for hardware, chip, and tool innovation, and we argue the a systematic IP valuation methodology will help the success of this environment, in that it will allow each member of the value chain - especially small VC-backed companies - to capture enough value to desire to participate.","PeriodicalId":328550,"journal":{"name":"Fifth International Workshop on System-on-Chip for Real-Time Applications (IWSOC'05)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-07-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127154247","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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