Pub Date : 2018-04-10DOI: 10.1109/DTIS.2018.8368561
E. Valea, M. D. Silva, G. D. Natale, M. Flottes, Sophie Dupuis, B. Rouzeyre
Energy consumption of IoT devices is a very important issue. For this reason, many techniques have been developed to allow IoT nodes to be aware of the amount of available energy. When energy is missing, the device halts and saves its state. One of those techniques is context saving, relying on the use of Non-Volatile Memories (NVM) to store and restore the state of the device. However, this information, as far as IoT devices deal with security, might be the target of attacks, including tampering and theft of confidential data. In this paper, we propose a SECure Context Saving (SECCS) approach that provides a context saving procedure and a hardware module easy to implement inside a System on Chip (SoC). This approach provides both confidentiality and integrity to all the CPU content saved into the target NVM.
{"title":"SI ECCS: SECure context saving for IoT devices","authors":"E. Valea, M. D. Silva, G. D. Natale, M. Flottes, Sophie Dupuis, B. Rouzeyre","doi":"10.1109/DTIS.2018.8368561","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368561","url":null,"abstract":"Energy consumption of IoT devices is a very important issue. For this reason, many techniques have been developed to allow IoT nodes to be aware of the amount of available energy. When energy is missing, the device halts and saves its state. One of those techniques is context saving, relying on the use of Non-Volatile Memories (NVM) to store and restore the state of the device. However, this information, as far as IoT devices deal with security, might be the target of attacks, including tampering and theft of confidential data. In this paper, we propose a SECure Context Saving (SECCS) approach that provides a context saving procedure and a hardware module easy to implement inside a System on Chip (SoC). This approach provides both confidentiality and integrity to all the CPU content saved into the target NVM.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125125856","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-04-09DOI: 10.1109/DTIS.2018.8368585
P. Fiser, Václav Simek
Polymorphic circuits represent a newly emerging computation paradigm, where one hardware structure is capable to perform two or more different intended functions, depending on instantaneous conditions in the target operating environment. Due to the peculiarity of this paradigm, design of these circuits also calls for a novel approach to logic synthesis procedures. Several attempts to enhance the design of such circuits have already been made, producing highly suboptimal solutions. As an ingenious attempt to set lower bounds on complexity and support designers of sophisticated logic synthesis algorithms, a method with the prospect to facilitate the generation of optimum-size polymorphic circuits is presented in this paper. The core of the proposed method is based on a purposeful exploitation of formal techniques, comprising SAT and PBO in the first place.
{"title":"Optimum polymorphic circuits synthesis method","authors":"P. Fiser, Václav Simek","doi":"10.1109/DTIS.2018.8368585","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368585","url":null,"abstract":"Polymorphic circuits represent a newly emerging computation paradigm, where one hardware structure is capable to perform two or more different intended functions, depending on instantaneous conditions in the target operating environment. Due to the peculiarity of this paradigm, design of these circuits also calls for a novel approach to logic synthesis procedures. Several attempts to enhance the design of such circuits have already been made, producing highly suboptimal solutions. As an ingenious attempt to set lower bounds on complexity and support designers of sophisticated logic synthesis algorithms, a method with the prospect to facilitate the generation of optimum-size polymorphic circuits is presented in this paper. The core of the proposed method is based on a purposeful exploitation of formal techniques, comprising SAT and PBO in the first place.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116892849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-04-09DOI: 10.1109/DTIS.2018.8368566
Dennis Noll, U. Schwalke
By transfer-free in situ catalytic chemical vapor deposition (CCVD) hundreds of nanocrystalline graphene field-effect transistors (ncGFETs) have been fabricated on a single 2″ silicon substrate. Raman spectroscopic analysis of the grown nanocrystalline graphene shows a clear signature of the G and a weak 2D peak in accoordance with the Raman spectra of nanocrystalline graphene from Schmidt et al. [1]. Using a grounded backgate ncGFET, the detection of ammonia (NH3) is demonstrated for room temperature (300 K) and 425 K, achieving detection down to a volume concentration of 100 parts-per-billion-volume (ppbv). By this method, a sensitivity of S4ppm, 425 k = 80.6% can be found for a volume concentration of 4 parts-per-million-volume (ppmv) of NH3 at a temperature of 425 K. In addition, by evaluation of the input characteristics of our ncGFET under different volume concentrations of ammonia we observe a global increase in the conductivity, which influences the sensitivity of our devices as well as of the negative shift of the charge neutrality point.
利用无转移原位催化化学气相沉积(CCVD)技术，在2″硅衬底上制备了数百个纳米晶石墨烯场效应晶体管(ncgfet)。对生长的纳米晶石墨烯的拉曼光谱分析显示，与Schmidt等人[1]的纳米晶石墨烯的拉曼光谱一致，有明显的G特征和弱的2D峰。使用接地后门ncGFET，演示了在室温(300 K)和425 K下对氨(NH3)的检测，实现了低至百万分之一体积(ppbv)的检测。在425 k温度下，当NH3的体积浓度为百万分之4 (ppmv)时，灵敏度为S4ppm, 425 k = 80.6%。此外，通过评估我们的ncGFET在不同体积浓度的氨下的输入特性，我们观察到电导率的整体增加，这影响了我们的器件的灵敏度以及电荷中性点的负移。
{"title":"Ammonia sensors based on in situ fabricated nanocrystalline graphene field-effect devices","authors":"Dennis Noll, U. Schwalke","doi":"10.1109/DTIS.2018.8368566","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368566","url":null,"abstract":"By transfer-free in situ catalytic chemical vapor deposition (CCVD) hundreds of nanocrystalline graphene field-effect transistors (ncGFETs) have been fabricated on a single 2″ silicon substrate. Raman spectroscopic analysis of the grown nanocrystalline graphene shows a clear signature of the G and a weak 2D peak in accoordance with the Raman spectra of nanocrystalline graphene from Schmidt et al. [1]. Using a grounded backgate ncGFET, the detection of ammonia (NH3) is demonstrated for room temperature (300 K) and 425 K, achieving detection down to a volume concentration of 100 parts-per-billion-volume (ppbv). By this method, a sensitivity of S4ppm, 425 k = 80.6% can be found for a volume concentration of 4 parts-per-million-volume (ppmv) of NH3 at a temperature of 425 K. In addition, by evaluation of the input characteristics of our ncGFET under different volume concentrations of ammonia we observe a global increase in the conductivity, which influences the sensitivity of our devices as well as of the negative shift of the charge neutrality point.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131183621","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-04-09DOI: 10.1109/DTIS.2018.8368563
J. Sini, A. Mugoni, M. Violante, A. Quario, C. Argiri, F. Fusetti
Software is today dominating the development of novel automotive applications, and it is more and more responsible for critical functionalities, from battery management in hybrid vehicles to active safety, to autonomous driving. To guarantee the proper level of quality a strict development process such as that described in the ISO26262 shall be adopted, which requires intensive test activities, being integration test one of them. To successfully reach the goals of integration test, testers shall excite the software running on the target hardware with stimuli representative of those produced once the design under test (DUT) is integrated in the vehicle, and observe the produced response looking for deviations with respect to the expected outputs. In this paper, we propose an innovative approach to automate the test stimuli generation, application, and output response evaluation, making possible developing higher quality test with respect to a relevant industrial use case.
{"title":"An automatic approach to integration testing for critical automotive software","authors":"J. Sini, A. Mugoni, M. Violante, A. Quario, C. Argiri, F. Fusetti","doi":"10.1109/DTIS.2018.8368563","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368563","url":null,"abstract":"Software is today dominating the development of novel automotive applications, and it is more and more responsible for critical functionalities, from battery management in hybrid vehicles to active safety, to autonomous driving. To guarantee the proper level of quality a strict development process such as that described in the ISO26262 shall be adopted, which requires intensive test activities, being integration test one of them. To successfully reach the goals of integration test, testers shall excite the software running on the target hardware with stimuli representative of those produced once the design under test (DUT) is integrated in the vehicle, and observe the produced response looking for deviations with respect to the expected outputs. In this paper, we propose an innovative approach to automate the test stimuli generation, application, and output response evaluation, making possible developing higher quality test with respect to a relevant industrial use case.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115417412","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-04-09DOI: 10.1109/DTIS.2018.8368569
M. Grosso, S. Rinaudo, E. Patti, A. Acquaviva
Internet-of-things enabled applications are increasingly popular and are expected to spread even more in the next few years. Energy efficiency is fundamental to support the widespread use of such systems. This paper presents a practical framework for the development and the evaluation of low-power Wireless Sensor Networks equipped with energy harvesting, aiming at energy-autonomous applications. An experimental case study demonstrates the capabilities of the solution.
{"title":"An energy-autonomous wireless sensor network development platform","authors":"M. Grosso, S. Rinaudo, E. Patti, A. Acquaviva","doi":"10.1109/DTIS.2018.8368569","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368569","url":null,"abstract":"Internet-of-things enabled applications are increasingly popular and are expected to spread even more in the next few years. Energy efficiency is fundamental to support the widespread use of such systems. This paper presents a practical framework for the development and the evaluation of low-power Wireless Sensor Networks equipped with energy harvesting, aiming at energy-autonomous applications. An experimental case study demonstrates the capabilities of the solution.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122036366","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-04-09DOI: 10.1109/DTIS.2018.8368557
Alessandro Vallero, Alberto Carelli, S. Carlo
Recent years have witnessed the rapid growth of heterogeneous systems, composed of CPUs and hardware accelerators, to face up the constant increase of computational performance demand of digital systems. In this scenario, FPGAs offer the possibility to implement high performance reconfigurable accelerators, able to speed up the intrinsically parallel portions of applications. The study of reconfigurable heterogeneous systems is still maturing and, while some contributions about performance and power consumption are available, in literature there are few works addressing reliability. This paper analyzes reconfigurable heterogeneous systems in presence of permanent faults occurring in the FPGA. In this context, a reconfigurable heterogeneous architecture, including a Run Time Manager responsible for the communication of software tasks and the FPGA, the scheduling and the placement of hardware tasks, is presented. In addition, the paper introduces a reconfigurable heterogeneous system simulator for the proposed architecture. This simulator is able to evaluate during the design phase the degradation of the system performance due to permanent faults and allows to explore the design space dimensions efficiently.
{"title":"Trading-off reliability and performance in FPGA-based reconfigurable heterogeneous systems","authors":"Alessandro Vallero, Alberto Carelli, S. Carlo","doi":"10.1109/DTIS.2018.8368557","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368557","url":null,"abstract":"Recent years have witnessed the rapid growth of heterogeneous systems, composed of CPUs and hardware accelerators, to face up the constant increase of computational performance demand of digital systems. In this scenario, FPGAs offer the possibility to implement high performance reconfigurable accelerators, able to speed up the intrinsically parallel portions of applications. The study of reconfigurable heterogeneous systems is still maturing and, while some contributions about performance and power consumption are available, in literature there are few works addressing reliability. This paper analyzes reconfigurable heterogeneous systems in presence of permanent faults occurring in the FPGA. In this context, a reconfigurable heterogeneous architecture, including a Run Time Manager responsible for the communication of software tasks and the FPGA, the scheduling and the placement of hardware tasks, is presented. In addition, the paper introduces a reconfigurable heterogeneous system simulator for the proposed architecture. This simulator is able to evaluate during the design phase the degradation of the system performance due to permanent faults and allows to explore the design space dimensions efficiently.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122736801","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-04-09DOI: 10.1109/DTIS.2018.8368549
Liang Wu, Mohammad Khizer Hussain, Saed Abughannam, W. Müller, C. Scheytt, W. Ecker
This paper presents an approach for analog fault effect simulation automation based on random fault selection with a high fault coverage of the circuit under test by means of fault injection and simulation based on advanced sampling techniques. The random fault selection utilizes the likelihood of the fault occurrence of different electrical components in the circuit with a confidence level. Defect models of different devices are analyzed for the calculation of the fault probability. A case study with our implemented tool demonstrates that likelihood calculation and fault simulation provides means for efficient fault effect simulation automation.
{"title":"Analog fault simulation automation at schematic level with random sampling techniques","authors":"Liang Wu, Mohammad Khizer Hussain, Saed Abughannam, W. Müller, C. Scheytt, W. Ecker","doi":"10.1109/DTIS.2018.8368549","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368549","url":null,"abstract":"This paper presents an approach for analog fault effect simulation automation based on random fault selection with a high fault coverage of the circuit under test by means of fault injection and simulation based on advanced sampling techniques. The random fault selection utilizes the likelihood of the fault occurrence of different electrical components in the circuit with a confidence level. Defect models of different devices are analyzed for the calculation of the fault probability. A case study with our implemented tool demonstrates that likelihood calculation and fault simulation provides means for efficient fault effect simulation automation.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116641567","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-04-09DOI: 10.1109/DTIS.2018.8368554
A. Finocchiaro, G. Girlando, Alessandro Motta, A. Pagani, G. Palmisano
A fully contactless wafer-level testing for 860–960 MHz RFID tags has been demonstrated. For the first time, an array of 30 RFID ICs with On-Chip-Antenna (OCA) has been simultaneously tested by inductive coupling. The anti-collision algorithm in combination with the insertion of x-y coordinates on the memory bank of each device during the EWS tests has allowed to identify each tag of the wafer. Moreover, a wafer scribe line pre-cutting has permitted to avoid undesired eddy currents generation at wafer level.
{"title":"A fully contactless wafer-level testing for UHF RFID tag with on-chip antenna","authors":"A. Finocchiaro, G. Girlando, Alessandro Motta, A. Pagani, G. Palmisano","doi":"10.1109/DTIS.2018.8368554","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368554","url":null,"abstract":"A fully contactless wafer-level testing for 860–960 MHz RFID tags has been demonstrated. For the first time, an array of 30 RFID ICs with On-Chip-Antenna (OCA) has been simultaneously tested by inductive coupling. The anti-collision algorithm in combination with the insertion of x-y coordinates on the memory bank of each device during the EWS tests has allowed to identify each tag of the wafer. Moreover, a wafer scribe line pre-cutting has permitted to avoid undesired eddy currents generation at wafer level.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"2008 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134628423","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-04-09DOI: 10.1109/DTIS.2018.8368558
A. Floridia, D. Piumatti, E. Sánchez, S. D. Luca, A. Sansonetti
In recent years the complexity of System-On-Chips have been grown exponentially, mainly due to the ever-increasing demand for more functionalities, even for embedded applications. In order to fulfil such requests, semiconductor vendors introduced in this market multi-core devices. However, despite the gain in terms of performance, the adoption of multi-core devices pose several issues from the testing viewpoint. In particular, it is required to evolve the in-field testing strategies (commonly used to increase the reliability level of a processor-based system) from the single-core to the multi-core case. In this paper, we present a possible approach for rapidly migrating a Software Test Library, developed according the Software-Based Self-Test approach for a single-core processor, to a multi-core processor. The proposed methodology relies on the usage of hardware semaphores in order to reduce memory utilization and control the access to shared resources among different cores. The experimental results were performed on a multi-core microcontroller manufactured by STMicroelectronics.
{"title":"Parallel software-based self-test suite for multi-core system-on-chip: Migration from single-core to multi-core automotive microcontrollers","authors":"A. Floridia, D. Piumatti, E. Sánchez, S. D. Luca, A. Sansonetti","doi":"10.1109/DTIS.2018.8368558","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368558","url":null,"abstract":"In recent years the complexity of System-On-Chips have been grown exponentially, mainly due to the ever-increasing demand for more functionalities, even for embedded applications. In order to fulfil such requests, semiconductor vendors introduced in this market multi-core devices. However, despite the gain in terms of performance, the adoption of multi-core devices pose several issues from the testing viewpoint. In particular, it is required to evolve the in-field testing strategies (commonly used to increase the reliability level of a processor-based system) from the single-core to the multi-core case. In this paper, we present a possible approach for rapidly migrating a Software Test Library, developed according the Software-Based Self-Test approach for a single-core processor, to a multi-core processor. The proposed methodology relies on the usage of hardware semaphores in order to reduce memory utilization and control the access to shared resources among different cores. The experimental results were performed on a multi-core microcontroller manufactured by STMicroelectronics.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"303 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134122356","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-04-09DOI: 10.1109/DTIS.2018.8368550
Fabian Speicher, Christoph Beyerstedt, M. Scholl, Tobias Saalfeld, V. Bonehi, M. Schrey, R. Wunderlich, S. Heinen
Digital assisted analog and RF concepts used in multi-standard multi-band wireless SoCs require a strong interaction between the analog and digital subsystems. Therefore functional verification of modern complex SoCs has evolved into a very challenging part in todays design flows. As an approach for an expedient verification process, an event-driven method based on SystemVerilog HDL is presented to perform time-efficient verification simulations of an entire RF transceiver frontend. To take into account signal properties, system behavior and certain error scenarios, methods like RF signal representation in the equivalent baseband, electrical signal modeling and true event-driven filter modeling are applied. A comparison to conventional simulation methodologies is given.
{"title":"Methodology for improved event-driven system-level simulation of an RF transceiver subsystem for wireless SoCs","authors":"Fabian Speicher, Christoph Beyerstedt, M. Scholl, Tobias Saalfeld, V. Bonehi, M. Schrey, R. Wunderlich, S. Heinen","doi":"10.1109/DTIS.2018.8368550","DOIUrl":"https://doi.org/10.1109/DTIS.2018.8368550","url":null,"abstract":"Digital assisted analog and RF concepts used in multi-standard multi-band wireless SoCs require a strong interaction between the analog and digital subsystems. Therefore functional verification of modern complex SoCs has evolved into a very challenging part in todays design flows. As an approach for an expedient verification process, an event-driven method based on SystemVerilog HDL is presented to perform time-efficient verification simulations of an entire RF transceiver frontend. To take into account signal properties, system behavior and certain error scenarios, methods like RF signal representation in the equivalent baseband, electrical signal modeling and true event-driven filter modeling are applied. A comparison to conventional simulation methodologies is given.","PeriodicalId":328650,"journal":{"name":"2018 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-04-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128076670","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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