Pub Date : 2017-04-01DOI: 10.1109/DTIS.2017.7930154
L. Marchetti, Y. Berg, M. Azadmehr
In this paper we propose a new front-end for resonating sensors which is based on a logic inverter working as amplifier. The front-end is compact and auto-zeroing which makes it a good candidate for integration and for low power applications. It has been simulated in AMS-350nm CMOS Technology and a prototype has been fabricated using discrete components on a PCB. The circuit was tested with a BvD load implemented in discrete components, which can be proved to be a good model for a resonant sensor. The components used to implement the BvD load are: Lm = 3mH, Rb = 200Ω, Cs = 560pF, Ce = 3.3nF which leads to a resonant frequency of 140 KHz. The bandwidth of the amplifier is 380kHz and the mid-band gain is 55V/V. The prototype has been tested with a power supply of 5V.
{"title":"An autozeroing inverter based front-end for resonating sensors","authors":"L. Marchetti, Y. Berg, M. Azadmehr","doi":"10.1109/DTIS.2017.7930154","DOIUrl":"https://doi.org/10.1109/DTIS.2017.7930154","url":null,"abstract":"In this paper we propose a new front-end for resonating sensors which is based on a logic inverter working as amplifier. The front-end is compact and auto-zeroing which makes it a good candidate for integration and for low power applications. It has been simulated in AMS-350nm CMOS Technology and a prototype has been fabricated using discrete components on a PCB. The circuit was tested with a BvD load implemented in discrete components, which can be proved to be a good model for a resonant sensor. The components used to implement the BvD load are: Lm = 3mH, Rb = 200Ω, Cs = 560pF, Ce = 3.3nF which leads to a resonant frequency of 140 KHz. The bandwidth of the amplifier is 380kHz and the mid-band gain is 55V/V. The prototype has been tested with a power supply of 5V.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126610675","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-04-01DOI: 10.1109/DTIS.2017.7930177
S. Bota, J. Verd, Joan Barceló, X. Gili, B. Alorda, G. Torrens, Carol de Benito, J. Segura
We analyze the benefits of replacing selected MOSFET transistors by nanoelectromechanical relays within conventional CMOS six transistor SRAM cells. Specifically, we evaluate a potential implementation that uses a cantilever designed with a 65 nm standard CMOS technology. The impact on various reliability metrics like static noise margin and write noise margin are evaluated from circuit simulations using a nanomechanical relay Verilog-A compact model. Comparisons are performed between a 65 nm CMOS 6T conventional SRAM cell and various hybrid memory cells constructed by replacing selected MOSFET transistors with cantilever relays. The impact on other important memory cell parameters such as area, timing performance and power consumption is also discussed.
{"title":"Cantilever NEMS relay-based SRAM devices for enhanced reliability","authors":"S. Bota, J. Verd, Joan Barceló, X. Gili, B. Alorda, G. Torrens, Carol de Benito, J. Segura","doi":"10.1109/DTIS.2017.7930177","DOIUrl":"https://doi.org/10.1109/DTIS.2017.7930177","url":null,"abstract":"We analyze the benefits of replacing selected MOSFET transistors by nanoelectromechanical relays within conventional CMOS six transistor SRAM cells. Specifically, we evaluate a potential implementation that uses a cantilever designed with a 65 nm standard CMOS technology. The impact on various reliability metrics like static noise margin and write noise margin are evaluated from circuit simulations using a nanomechanical relay Verilog-A compact model. Comparisons are performed between a 65 nm CMOS 6T conventional SRAM cell and various hybrid memory cells constructed by replacing selected MOSFET transistors with cantilever relays. The impact on other important memory cell parameters such as area, timing performance and power consumption is also discussed.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"53 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126640850","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-04-01DOI: 10.1109/DTIS.2017.7930164
J. Schat
Single Event Upsets (SEUs) are the most frequent source of temporary malfunctions in today's ICs. The automotive standard ISO 26262 demands detection and mitigation measures that cover at least 90 to 99 percent of the safety-critical malfunctions, depending on the safety level of the IC. In SOCs, different kinds of cores require different kinds of detection and mitigation measures. In many SOCs, Register Files are used to provide (quasi)static parameter settings to e.g. an analog core. For such Register Files, a circuitry that detects SEU-caused failures is presented.
{"title":"Soft-error detection in Register Files using circular scan","authors":"J. Schat","doi":"10.1109/DTIS.2017.7930164","DOIUrl":"https://doi.org/10.1109/DTIS.2017.7930164","url":null,"abstract":"Single Event Upsets (SEUs) are the most frequent source of temporary malfunctions in today's ICs. The automotive standard ISO 26262 demands detection and mitigation measures that cover at least 90 to 99 percent of the safety-critical malfunctions, depending on the safety level of the IC. In SOCs, different kinds of cores require different kinds of detection and mitigation measures. In many SOCs, Register Files are used to provide (quasi)static parameter settings to e.g. an analog core. For such Register Files, a circuitry that detects SEU-caused failures is presented.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128310417","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-04-01DOI: 10.1109/DTIS.2017.7930180
J. Nevoral, Václav Simek, R. Ruzicka
Main goal of this paper is to propose a compact library of polymorphic gates based on suitable type of reconfigurable transistors. In fact, their exploitation brings a significant advantage for space-efficient synthesis of complex polymorphic circuits. Actual behaviour of those transistors closely depends on so called ambipolar property. That particular aspect simply allows the selection of n- or p- channel operating mode of the transistor structures which is controlled by means of switching the voltage level at a dedicated control electrode. The gates were developed by an evolution approach using Cartesian genetic programming. Various discrete switch-level ambipolar transistor models extended by taking into account the threshold voltage drop degradation effect were used. A diverse range of polymorphic gates were designed, which clearly shows significant transistor savings compared to the conventional approaches. Finally, the individual components that belong to the library also suggest the opportunity how to considerably reduce the target size of complex polymorphic circuits.
{"title":"Compact library of efficient polymorphic gates based on ambipolar transistors","authors":"J. Nevoral, Václav Simek, R. Ruzicka","doi":"10.1109/DTIS.2017.7930180","DOIUrl":"https://doi.org/10.1109/DTIS.2017.7930180","url":null,"abstract":"Main goal of this paper is to propose a compact library of polymorphic gates based on suitable type of reconfigurable transistors. In fact, their exploitation brings a significant advantage for space-efficient synthesis of complex polymorphic circuits. Actual behaviour of those transistors closely depends on so called ambipolar property. That particular aspect simply allows the selection of n- or p- channel operating mode of the transistor structures which is controlled by means of switching the voltage level at a dedicated control electrode. The gates were developed by an evolution approach using Cartesian genetic programming. Various discrete switch-level ambipolar transistor models extended by taking into account the threshold voltage drop degradation effect were used. A diverse range of polymorphic gates were designed, which clearly shows significant transistor savings compared to the conventional approaches. Finally, the individual components that belong to the library also suggest the opportunity how to considerably reduce the target size of complex polymorphic circuits.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124005182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-04-01DOI: 10.1109/DTIS.2017.7930155
Tillmann A. Krauss, Frank Wessely, U. Schwalke
In this paper, we illustrate by simulation and extend our previous work by demonstration of fabricated devices of electrostatically doped, reconfigurable planar field-effect-transistors with dual work function metal gates. The technological cornerstones for this dual-gated general purpose FET contain Schottky S/D junctions on a silicon-on-insulator substrate. The transistor type, i.e. n-type or p-type FET, is electrically selectable in operation by applying a control-gate voltage which significantly increases the versatility and flexibility in the design of digital integrated circuits.
{"title":"Fabrication and simulation of electrically reconfigurable dual metal-gate planar field-effect transistors for dopant-free CMOS","authors":"Tillmann A. Krauss, Frank Wessely, U. Schwalke","doi":"10.1109/DTIS.2017.7930155","DOIUrl":"https://doi.org/10.1109/DTIS.2017.7930155","url":null,"abstract":"In this paper, we illustrate by simulation and extend our previous work by demonstration of fabricated devices of electrostatically doped, reconfigurable planar field-effect-transistors with dual work function metal gates. The technological cornerstones for this dual-gated general purpose FET contain Schottky S/D junctions on a silicon-on-insulator substrate. The transistor type, i.e. n-type or p-type FET, is electrically selectable in operation by applying a control-gate voltage which significantly increases the versatility and flexibility in the design of digital integrated circuits.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122860781","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-04-01DOI: 10.1109/DTIS.2017.7930171
D. Venuto, V. Annese, G. Defazio, V. L. Gallo, G. Mezzina
This work addresses the rising need for a diagnostic tool for the evaluation of the effectiveness of a drug treatment in Parkinson disease, allowing the physician to monitor of the patient gait at home and to shape the treatment on the individual peculiarity. In aim, we present a cyber-physical system for real-time processing EEG and EMG signals. The wearable and wireless system extracts the following indexes: (i) typical activation and deactivation timing of single muscles and the duty cycle in a single step (ii) typical and maximum co-contractions, as well as number of co-contraction/s. The indexes are validated by using Movement Related Potentials (MRPs). The signal processing stage is implemented on Altera Cyclone V FPGA. In the paper, we show in vivo measurements by comparing responses before and after the drug (Levodopa) treatment. The system quantifies the effect of the Levodopa treatment detecting: (i) a 17% reduction in typical agonist-antagonist co-contractions time (ii) 23.6% decrease in the maximum co-contraction time (iii) 33% decrease in number of critical co-contraction. Brain implications shows a mean reduction of 5% on the evaluated potentials.
这项工作解决了对帕金森病药物治疗有效性评估的诊断工具的日益增长的需求，使医生能够在家中监测患者的步态，并根据个人特点制定治疗方案。为此，我们提出了一个实时处理脑电和肌电信号的网络物理系统。可穿戴无线系统提取以下指标:(i)单个肌肉的典型激活和失活时间以及单步占空比;(ii)典型和最大共收缩，以及共收缩次数/s。采用运动相关电位(MRPs)对指标进行验证。信号处理阶段在Altera Cyclone V FPGA上实现。在本文中，我们通过比较药物(左旋多巴)治疗前后的反应来显示体内测量。该系统量化了左旋多巴治疗检测的效果:(i)典型激动剂-拮抗剂共收缩时间减少17% (ii)最大共收缩时间减少23.6% (iii)临界共收缩次数减少33%。脑暗示显示在评估电位上平均减少5%。
{"title":"Gait analysis and quantitative drug effect evaluation in Parkinson disease by jointly EEG-EMG monitoring","authors":"D. Venuto, V. Annese, G. Defazio, V. L. Gallo, G. Mezzina","doi":"10.1109/DTIS.2017.7930171","DOIUrl":"https://doi.org/10.1109/DTIS.2017.7930171","url":null,"abstract":"This work addresses the rising need for a diagnostic tool for the evaluation of the effectiveness of a drug treatment in Parkinson disease, allowing the physician to monitor of the patient gait at home and to shape the treatment on the individual peculiarity. In aim, we present a cyber-physical system for real-time processing EEG and EMG signals. The wearable and wireless system extracts the following indexes: (i) typical activation and deactivation timing of single muscles and the duty cycle in a single step (ii) typical and maximum co-contractions, as well as number of co-contraction/s. The indexes are validated by using Movement Related Potentials (MRPs). The signal processing stage is implemented on Altera Cyclone V FPGA. In the paper, we show in vivo measurements by comparing responses before and after the drug (Levodopa) treatment. The system quantifies the effect of the Levodopa treatment detecting: (i) a 17% reduction in typical agonist-antagonist co-contractions time (ii) 23.6% decrease in the maximum co-contraction time (iii) 33% decrease in number of critical co-contraction. Brain implications shows a mean reduction of 5% on the evaluated potentials.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"368 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126332049","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-04-01DOI: 10.1109/DTIS.2017.7930165
Meghashyam Ashwathanarayan, G. Jayakrishna
Post-silicon validation is the last level of inspecting the silicon before it is delivered to the customer. Automotive microcontrollers use Direct Memory Access (DMA) extensively in safety critical applications. This article explains how post-silicon validation can be improved to address the needs of the growing complexity of microcontrollers with a large number of Intellectual Property (IP). With increasing design complexity, aggressive scaling, and decreasing time to market, it is imperative to test the robustness of the microcontroller. Traditional test cases follow directed approach to testing and do not guarantee complete functional coverage. The proposed methodology uses the concept of constraint based randomization that is used in pre-silicon verification. The main advantage of using constraint based randomization in post-silicon validation is that millions of seeds can be executed in a very short time. This also stresses the silicon, increasing the likelihood of uncovering a bug which would not have been humanly possible to uncover at the pre-silicon stage.
{"title":"A method/approach leading to controlled randomization in validation of an IP","authors":"Meghashyam Ashwathanarayan, G. Jayakrishna","doi":"10.1109/DTIS.2017.7930165","DOIUrl":"https://doi.org/10.1109/DTIS.2017.7930165","url":null,"abstract":"Post-silicon validation is the last level of inspecting the silicon before it is delivered to the customer. Automotive microcontrollers use Direct Memory Access (DMA) extensively in safety critical applications. This article explains how post-silicon validation can be improved to address the needs of the growing complexity of microcontrollers with a large number of Intellectual Property (IP). With increasing design complexity, aggressive scaling, and decreasing time to market, it is imperative to test the robustness of the microcontroller. Traditional test cases follow directed approach to testing and do not guarantee complete functional coverage. The proposed methodology uses the concept of constraint based randomization that is used in pre-silicon verification. The main advantage of using constraint based randomization in post-silicon validation is that millions of seeds can be executed in a very short time. This also stresses the silicon, increasing the likelihood of uncovering a bug which would not have been humanly possible to uncover at the pre-silicon stage.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115698259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-04-01DOI: 10.1109/DTIS.2017.7930176
Basma Hajri, Mohammad M. Mansour, A. Chehab, H. Aziza
Recently, Oxide-based random access memory devices (OxRAM) have shown the potential to outperform non-volatile memories due to their high scalability, high-speed, high-density, and low-energy operation. A critical requirement for using OxRAM at circuit level is a predictive model for device behavior that can be used in simulations, as well as a guide for circuit designers. The proper choice of the memory device model leads to a better understanding of the memory cell behavior, and also to a better exploitation of its unique properties in novel systems. This work is intended to help designers decide on the most appropriate memory cell model for circuit design. We present a comparative study of the different major existing OxRAM models tested within the same simulation environment.
{"title":"Oxide-based RRAM models for circuit designers: A comparative analysis","authors":"Basma Hajri, Mohammad M. Mansour, A. Chehab, H. Aziza","doi":"10.1109/DTIS.2017.7930176","DOIUrl":"https://doi.org/10.1109/DTIS.2017.7930176","url":null,"abstract":"Recently, Oxide-based random access memory devices (OxRAM) have shown the potential to outperform non-volatile memories due to their high scalability, high-speed, high-density, and low-energy operation. A critical requirement for using OxRAM at circuit level is a predictive model for device behavior that can be used in simulations, as well as a guide for circuit designers. The proper choice of the memory device model leads to a better understanding of the memory cell behavior, and also to a better exploitation of its unique properties in novel systems. This work is intended to help designers decide on the most appropriate memory cell model for circuit design. We present a comparative study of the different major existing OxRAM models tested within the same simulation environment.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124460578","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-04-01DOI: 10.1109/DTIS.2017.7930174
Mahroo Zandrahimi, P. Debaud, Armand Castillejo, Z. Al-Ars
Process variation occurring during fabrication of complex VLSI devices induce uncertainties in operation parameters (e.g., supply voltage) to be applied to each device in order for it to fit within the allowed power budget and get the optimum power efficiency. Therefore, an efficient post manufacturing performance estimation mechanism is needed in order to tune operation parameters for each device during production. The current state-of-the-art approach of using Process Monitoring Boxes (PMBs) have shown some limitations in terms of cost and accuracy that limit their benefit. Simulation results on ISCAS'99 benchmarks using 28nm FD-SOI library show that the accuracy of PMB approaches is design dependent, and requires up to 8.20% added design margin. To overcome those limitations, in this paper we propose an alternative solution using transition fault (TF) test patterns, which is able to eliminate the need for PMBs, while improving the accuracy of performance estimation. The paper discusses a case study on real silicon comparing the performance estimation using functional test patterns and the TF based approach on a 28nm FD-SOI CPU. The results show a very close correlation between TF test patterns and functional patterns.
{"title":"Using transition fault test patterns for cost effective offline performance estimation","authors":"Mahroo Zandrahimi, P. Debaud, Armand Castillejo, Z. Al-Ars","doi":"10.1109/DTIS.2017.7930174","DOIUrl":"https://doi.org/10.1109/DTIS.2017.7930174","url":null,"abstract":"Process variation occurring during fabrication of complex VLSI devices induce uncertainties in operation parameters (e.g., supply voltage) to be applied to each device in order for it to fit within the allowed power budget and get the optimum power efficiency. Therefore, an efficient post manufacturing performance estimation mechanism is needed in order to tune operation parameters for each device during production. The current state-of-the-art approach of using Process Monitoring Boxes (PMBs) have shown some limitations in terms of cost and accuracy that limit their benefit. Simulation results on ISCAS'99 benchmarks using 28nm FD-SOI library show that the accuracy of PMB approaches is design dependent, and requires up to 8.20% added design margin. To overcome those limitations, in this paper we propose an alternative solution using transition fault (TF) test patterns, which is able to eliminate the need for PMBs, while improving the accuracy of performance estimation. The paper discusses a case study on real silicon comparing the performance estimation using functional test patterns and the TF based approach on a 28nm FD-SOI CPU. The results show a very close correlation between TF test patterns and functional patterns.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123529203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-04-01DOI: 10.1109/DTIS.2017.7930163
M. Renovell
With today manufacturing technology, it is not possible to eliminate all defects and ensure every manufactured unit is perfect. Instead, each manufactured unit must be tested so that defective parts are not shipped to a customer. Different Test Strategies are commonly used since none is considered as optimal in terms of low defect level. Most companies use some but not all of the following three Test Strategies: the Static Voltage strategy, the Dynamic Voltage or Delay strategy, the Static or Dynamic Current (I_DDX) strategy. While using different approaches, these different test strategies have a common objective: reveal the presence in the chip of defects or deviations that may create a dysfunction. Knowing the complexity of today defects, it is admitted that the classical fault models used for test generation cannot guarantee a satisfactory detection of defects. This implies that new test generation technique specifically oriented to defects have to be defined. So, we must analyze and understand the electrical behavior of the defect and describe its behavior through an adequate ‘defect model’. Then, defect simulation techniques and defect-oriented ATPG techniques must be proposed to allow specific test generation for these defects. This presentation focuses on spot defects that manifest themselves as shorts or opens in the interconnect or in the MOS transistors: ‘Interconnect open’, ‘Interconnect short’, ‘Floating gate’, and ‘Gate-Oxide-Short’ are analyzed in detail using different model levels. For every defect, it is shown that the electrical behavior is in fact not predictable due to the presence of random parameters. In order to tackle the problem of unpredictability, unified concepts are proposed that allow new test generation techniques guaranteeing coverage of unpredictable defects.
{"title":"Spot defect modeling: Past and evolution","authors":"M. Renovell","doi":"10.1109/DTIS.2017.7930163","DOIUrl":"https://doi.org/10.1109/DTIS.2017.7930163","url":null,"abstract":"With today manufacturing technology, it is not possible to eliminate all defects and ensure every manufactured unit is perfect. Instead, each manufactured unit must be tested so that defective parts are not shipped to a customer. Different Test Strategies are commonly used since none is considered as optimal in terms of low defect level. Most companies use some but not all of the following three Test Strategies: the Static Voltage strategy, the Dynamic Voltage or Delay strategy, the Static or Dynamic Current (I_DDX) strategy. While using different approaches, these different test strategies have a common objective: reveal the presence in the chip of defects or deviations that may create a dysfunction. Knowing the complexity of today defects, it is admitted that the classical fault models used for test generation cannot guarantee a satisfactory detection of defects. This implies that new test generation technique specifically oriented to defects have to be defined. So, we must analyze and understand the electrical behavior of the defect and describe its behavior through an adequate ‘defect model’. Then, defect simulation techniques and defect-oriented ATPG techniques must be proposed to allow specific test generation for these defects. This presentation focuses on spot defects that manifest themselves as shorts or opens in the interconnect or in the MOS transistors: ‘Interconnect open’, ‘Interconnect short’, ‘Floating gate’, and ‘Gate-Oxide-Short’ are analyzed in detail using different model levels. For every defect, it is shown that the electrical behavior is in fact not predictable due to the presence of random parameters. In order to tackle the problem of unpredictability, unified concepts are proposed that allow new test generation techniques guaranteeing coverage of unpredictable defects.","PeriodicalId":328905,"journal":{"name":"2017 12th International Conference on Design & Technology of Integrated Systems In Nanoscale Era (DTIS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2017-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131411591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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