Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352165
Edip Demirbilek, Jean-Charles Grégoire, Ahmad Vakili, L. Reyero
We evaluated the power consumption of an industry-grade IMS/RCS application that periodically updates and retrieves the availability status as well as inbox query task to/from the server over Wi-Fi interface. Our aim was to find out the amount of additional energy consumed for each unique tasks. We modelled the battery usage of always-on features and identified each feature's contribution to the whole consumption. While presenting the work we also paid attention to the process we went through and provided a methodology for similar future work.
{"title":"Modelling and improving the battery performance of a mobile phone application: A methodology","authors":"Edip Demirbilek, Jean-Charles Grégoire, Ahmad Vakili, L. Reyero","doi":"10.1109/ICEAC.2015.7352165","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352165","url":null,"abstract":"We evaluated the power consumption of an industry-grade IMS/RCS application that periodically updates and retrieves the availability status as well as inbox query task to/from the server over Wi-Fi interface. Our aim was to find out the amount of additional energy consumed for each unique tasks. We modelled the battery usage of always-on features and identified each feature's contribution to the whole consumption. While presenting the work we also paid attention to the process we went through and provided a methodology for similar future work.","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129970395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352204
S. Chamanian, Ö. Zorlu, H. Kulah, A. Muhtaroğlu
This paper presents a fully self-powered interface circuit with a novel peak detector for piezoelectric energy harvesters (PEH). This circuit can be utilized to scavenge energy from low power environmental vibrations in 10s of μW range. Synchronous switching technique is used to extract maximum available power where switching instants are detected independently from excitation changes of the PEH. The proposed peak detector senses voltages higher than power supply for a wide frequency range of input vibration. The simulations with an output voltage range of 1 to 3.3 V show power conversion efficiency between 79% and 88% for an input power of 13.2 μW.
{"title":"An adaptive piezoelectric energy harvesting interface circuit with a novel peak detector","authors":"S. Chamanian, Ö. Zorlu, H. Kulah, A. Muhtaroğlu","doi":"10.1109/ICEAC.2015.7352204","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352204","url":null,"abstract":"This paper presents a fully self-powered interface circuit with a novel peak detector for piezoelectric energy harvesters (PEH). This circuit can be utilized to scavenge energy from low power environmental vibrations in 10s of μW range. Synchronous switching technique is used to extract maximum available power where switching instants are detected independently from excitation changes of the PEH. The proposed peak detector senses voltages higher than power supply for a wide frequency range of input vibration. The simulations with an output voltage range of 1 to 3.3 V show power conversion efficiency between 79% and 88% for an input power of 13.2 μW.","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123064058","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352199
W. Pathirana, H. Jayaweera, A. Muhtaroğlu
This paper presents a low input voltage and high step-up fully integrated DC-DC regulator in 0.18 μm standard CMOS technology for thermoelectric micro-power generation. The circuit avoids off-chip components, non-standard processes, and is thus suitable for ultra-low voltage low profile system-on-chip applications. The proposed system can deliver a regulated output voltage of 1.5 V at 31 μW output power with an input voltage as low as 0.2 V. The maximum simulated efficiency is 22% at the given step-up range. The design methodology of an integrated inductor layout and oscillator has been reported in detail for the standard process. At the ultra-low voltage range of interest, the regulator is estimated to have lower cost, higher integration, and improved efficiency compared to the alternatives reported in literature, including the 90 nm and 0.18 μm two-stage charge pump designs previously reported by our team.
{"title":"Low input voltage and high step-up integrated regulator for thermoelectric energy harvesting","authors":"W. Pathirana, H. Jayaweera, A. Muhtaroğlu","doi":"10.1109/ICEAC.2015.7352199","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352199","url":null,"abstract":"This paper presents a low input voltage and high step-up fully integrated DC-DC regulator in 0.18 μm standard CMOS technology for thermoelectric micro-power generation. The circuit avoids off-chip components, non-standard processes, and is thus suitable for ultra-low voltage low profile system-on-chip applications. The proposed system can deliver a regulated output voltage of 1.5 V at 31 μW output power with an input voltage as low as 0.2 V. The maximum simulated efficiency is 22% at the given step-up range. The design methodology of an integrated inductor layout and oscillator has been reported in detail for the standard process. At the ultra-low voltage range of interest, the regulator is estimated to have lower cost, higher integration, and improved efficiency compared to the alternatives reported in literature, including the 90 nm and 0.18 μm two-stage charge pump designs previously reported by our team.","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"287 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133989297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352168
R. Tadros, A. H. Abdelrahman, M. Ghoneima, Y. Ismail
This paper presents a 24 Gbps SerDes transceiver circuit for on-chip high speed serial links for on-chip networks. The transceiver uses a proposed almost-differential self-timed 3-level signaling scheme, which works using a frequency of half the data rate for relaxing the design. Also, the third voltage level is created without the need for an external Vdd/2 supply source. Moreover, a 3-level inverter is proposed for the use in the front-end of both the TX and the RX. The transceiver is designed for a 5mm long lossy on-chip differential interconnect in GF 65nm CMOS technology. It serializes the parallel 3 Gbps 8-bit, and multiplexes them with the 12 GHz input clock. A simple RX extracts both the data and the clock from the same signals.
{"title":"A 24 Gbps SerDes transceiver for on-chip networks using a new half-data-rate self-timed 3-level signaling scheme","authors":"R. Tadros, A. H. Abdelrahman, M. Ghoneima, Y. Ismail","doi":"10.1109/ICEAC.2015.7352168","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352168","url":null,"abstract":"This paper presents a 24 Gbps SerDes transceiver circuit for on-chip high speed serial links for on-chip networks. The transceiver uses a proposed almost-differential self-timed 3-level signaling scheme, which works using a frequency of half the data rate for relaxing the design. Also, the third voltage level is created without the need for an external Vdd/2 supply source. Moreover, a 3-level inverter is proposed for the use in the front-end of both the TX and the RX. The transceiver is designed for a 5mm long lossy on-chip differential interconnect in GF 65nm CMOS technology. It serializes the parallel 3 Gbps 8-bit, and multiplexes them with the 12 GHz input clock. A simple RX extracts both the data and the clock from the same signals.","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125180378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352203
A. Rezk, A. Helmy, Y. Ismail
This paper presents the VHDL implementation of a novel power management algorithm for standalone PV-battery system. The algorithm performs two tasks, Maximum Power Point Tracking (MPPT) and dual load regulation. The MPPT is used to maximize the PV cells' output power, and is achieved by the “fractional open circuit voltage” method. The dual load regulation distributes the PV cells' output power among the loads, and delivers any surplus or deficit power to or from the battery. The proposed VHDL design has been synthesized on Xilinx using “5vlx50tff1136” as the target FPGA. The proposed design has utilized only 1% of the resources (slice registers and look-up-tables). This result has been found to be 23% lower than a previously implemented MPPT controller..
{"title":"VHDL implementation of a power management algorithm for PV-battery system","authors":"A. Rezk, A. Helmy, Y. Ismail","doi":"10.1109/ICEAC.2015.7352203","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352203","url":null,"abstract":"This paper presents the VHDL implementation of a novel power management algorithm for standalone PV-battery system. The algorithm performs two tasks, Maximum Power Point Tracking (MPPT) and dual load regulation. The MPPT is used to maximize the PV cells' output power, and is achieved by the “fractional open circuit voltage” method. The dual load regulation distributes the PV cells' output power among the loads, and delivers any surplus or deficit power to or from the battery. The proposed VHDL design has been synthesized on Xilinx using “5vlx50tff1136” as the target FPGA. The proposed design has utilized only 1% of the resources (slice registers and look-up-tables). This result has been found to be 23% lower than a previously implemented MPPT controller..","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130037605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352166
Furkan Ercan, A. Muhtaroğlu
Recent focus in energy efficiency is motivated with diminishing conventional energy resources, and increasing demand in low power applications with shrinking platform sizes. In this work, various threshold logic technologies are compared with each other in terms of power-delay-product (PDP). Compound CMOS, complementary pass transistor, static NAND gate, full adder, capacitive and differential threshold logic technologies are compared within a developed comparison scenario. Results in UMC180nm technology indicate that complementary pass transistor based threshold logic proves at least 2.5% more efficient than the rest in terms of PDP, while NAND based implementation has 29.2% better in terms of delay performance.
{"title":"Comparative power-delay performance analysis of threshold logic technologies","authors":"Furkan Ercan, A. Muhtaroğlu","doi":"10.1109/ICEAC.2015.7352166","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352166","url":null,"abstract":"Recent focus in energy efficiency is motivated with diminishing conventional energy resources, and increasing demand in low power applications with shrinking platform sizes. In this work, various threshold logic technologies are compared with each other in terms of power-delay-product (PDP). Compound CMOS, complementary pass transistor, static NAND gate, full adder, capacitive and differential threshold logic technologies are compared within a developed comparison scenario. Results in UMC180nm technology indicate that complementary pass transistor based threshold logic proves at least 2.5% more efficient than the rest in terms of PDP, while NAND based implementation has 29.2% better in terms of delay performance.","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122114305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352193
Yasmine El-Sayed, Amr Wageeh, Tawfik Ismail, H. Mostafa
All-Optical Clock and Data Recovery (OCDR) is an important function for future optical networks and optical signal processing. The OCDR realizes a long-distance optical data transmission system by restoring the incoming data and then retransmitting. The Self-Pulsating (SP) lasers are the promising technologies to enable fast and high-speed data recovery system in an optical domain. In this paper, we design and implement the OCDR based on two SP laser types, Amplified Feedback Laser (AFL) and Distributed Bragg Reflector Laser (DBRL). A comparative study and measurement of the network performance for the two types have been presented.
{"title":"All-optical clock and data recovery using self-pulsating lasers for high-speed optical networks","authors":"Yasmine El-Sayed, Amr Wageeh, Tawfik Ismail, H. Mostafa","doi":"10.1109/ICEAC.2015.7352193","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352193","url":null,"abstract":"All-Optical Clock and Data Recovery (OCDR) is an important function for future optical networks and optical signal processing. The OCDR realizes a long-distance optical data transmission system by restoring the incoming data and then retransmitting. The Self-Pulsating (SP) lasers are the promising technologies to enable fast and high-speed data recovery system in an optical domain. In this paper, we design and implement the OCDR based on two SP laser types, Amplified Feedback Laser (AFL) and Distributed Bragg Reflector Laser (DBRL). A comparative study and measurement of the network performance for the two types have been presented.","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122326601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352164
Khaled M. Ali, H. Mostafa, Tawfik Ismail
In this paper, a high-performance priority encoder is presented by using full custom approach. The proposed encoder provides both high- and low-priority functional with scalable design structure through a parallel look-ahead structure. A prefixing architecture is applied to minimize the critical path propagation delay and maximize the operating frequency. As a result, the proposed encoder is significant reduce the total critical delay by 53%, and the number of transistors by 7%, in addition it provides a regulated in building higher-order encoders. The results are conducted for different encoder inputs through TSMC 130nm CMOS technology.
{"title":"High performance layout-friendly 64-bit priority encoder utilizing parallel priority look-ahead","authors":"Khaled M. Ali, H. Mostafa, Tawfik Ismail","doi":"10.1109/ICEAC.2015.7352164","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352164","url":null,"abstract":"In this paper, a high-performance priority encoder is presented by using full custom approach. The proposed encoder provides both high- and low-priority functional with scalable design structure through a parallel look-ahead structure. A prefixing architecture is applied to minimize the critical path propagation delay and maximize the operating frequency. As a result, the proposed encoder is significant reduce the total critical delay by 53%, and the number of transistors by 7%, in addition it provides a regulated in building higher-order encoders. The results are conducted for different encoder inputs through TSMC 130nm CMOS technology.","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122660507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352163
Mazen Al Haddad, M. Bayoumi
Mobile data traffic has skyrocketed in recent years and will continue to grow and demand more capacity. Continued heterogeneous networks' evolution and the utilization of massive Femtocell deployments will facilitate the meeting of capacity demands as expected towards 5G and telecom 2020-vision. The CO2 footprint of power usage is becoming spotlighted and energy-aware solutions are required. This paper reviews recent Femtocell downlink power control frameworks and proposes a novel comprehensive one taking into consideration issues like intra-interference (Femto-Femto), dense-deployments and environmental impact. Simulation results show up to 68% user throughput improvement and up to 20.69kg/year CO2-emission reduction for one Femtocell.
{"title":"Green energy solution for femtocell power control in massive deployments","authors":"Mazen Al Haddad, M. Bayoumi","doi":"10.1109/ICEAC.2015.7352163","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352163","url":null,"abstract":"Mobile data traffic has skyrocketed in recent years and will continue to grow and demand more capacity. Continued heterogeneous networks' evolution and the utilization of massive Femtocell deployments will facilitate the meeting of capacity demands as expected towards 5G and telecom 2020-vision. The CO2 footprint of power usage is becoming spotlighted and energy-aware solutions are required. This paper reviews recent Femtocell downlink power control frameworks and proposes a novel comprehensive one taking into consideration issues like intra-interference (Femto-Femto), dense-deployments and environmental impact. Simulation results show up to 68% user throughput improvement and up to 20.69kg/year CO2-emission reduction for one Femtocell.","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133083646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352196
Fassahat U. Qureshi, A. Muhtaroğlu, K. Tuncay
Batteries are commonly used to power sensors, a fact that carries severe drawbacks such as limited lifetime and regular replacement. Battery powered sensors are particularly impractical in under-water pipelines due to limited access. Therefore, harvesting of ambient energy to power embedded sensors is an attractive option for such systems. A method is proposed, in this paper, to power in-pipe wireless sensor nodes based on energy harvesting techniques, with minimal impact to the pipe performance. Based on the initial analysis presented in the paper, models will be developed next to facilitate the design of an energy harvester system for Turkey-Cyprus water pipeline project currently under construction.
{"title":"A method to integrate energy harvesters into wireless sensor nodes for embedded in-pipe monitoring applications","authors":"Fassahat U. Qureshi, A. Muhtaroğlu, K. Tuncay","doi":"10.1109/ICEAC.2015.7352196","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352196","url":null,"abstract":"Batteries are commonly used to power sensors, a fact that carries severe drawbacks such as limited lifetime and regular replacement. Battery powered sensors are particularly impractical in under-water pipelines due to limited access. Therefore, harvesting of ambient energy to power embedded sensors is an attractive option for such systems. A method is proposed, in this paper, to power in-pipe wireless sensor nodes based on energy harvesting techniques, with minimal impact to the pipe performance. Based on the initial analysis presented in the paper, models will be developed next to facilitate the design of an energy harvester system for Turkey-Cyprus water pipeline project currently under construction.","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125620458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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