Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352167
Furkan Ercan, A. Muhtaroğlu
ABACUS parallel architecture was previously proposed as an alternate integer multiplication approach with column compression and parallel carry futures. This paper presents a VLSI implementation for ABACUS and benchmarks it against the conventional Wallace Tree Multiplier (WTM). Simulations are conducted with UMC180nm technology in Cadence environment. Although WTM implementation results in 26.6% fewer devices, ABACUS implementation has 8.6% less power dissipation with matched delay performance, due to 27.8% lower average activity.
{"title":"Power-delay analysis of an ABACUS parallel integer multiplier VLSI implementation","authors":"Furkan Ercan, A. Muhtaroğlu","doi":"10.1109/ICEAC.2015.7352167","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352167","url":null,"abstract":"ABACUS parallel architecture was previously proposed as an alternate integer multiplication approach with column compression and parallel carry futures. This paper presents a VLSI implementation for ABACUS and benchmarks it against the conventional Wallace Tree Multiplier (WTM). Simulations are conducted with UMC180nm technology in Cadence environment. Although WTM implementation results in 26.6% fewer devices, ABACUS implementation has 8.6% less power dissipation with matched delay performance, due to 27.8% lower average activity.","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"150 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116304895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352199
W. Pathirana, H. Jayaweera, A. Muhtaroğlu
This paper presents a low input voltage and high step-up fully integrated DC-DC regulator in 0.18 μm standard CMOS technology for thermoelectric micro-power generation. The circuit avoids off-chip components, non-standard processes, and is thus suitable for ultra-low voltage low profile system-on-chip applications. The proposed system can deliver a regulated output voltage of 1.5 V at 31 μW output power with an input voltage as low as 0.2 V. The maximum simulated efficiency is 22% at the given step-up range. The design methodology of an integrated inductor layout and oscillator has been reported in detail for the standard process. At the ultra-low voltage range of interest, the regulator is estimated to have lower cost, higher integration, and improved efficiency compared to the alternatives reported in literature, including the 90 nm and 0.18 μm two-stage charge pump designs previously reported by our team.
{"title":"Low input voltage and high step-up integrated regulator for thermoelectric energy harvesting","authors":"W. Pathirana, H. Jayaweera, A. Muhtaroğlu","doi":"10.1109/ICEAC.2015.7352199","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352199","url":null,"abstract":"This paper presents a low input voltage and high step-up fully integrated DC-DC regulator in 0.18 μm standard CMOS technology for thermoelectric micro-power generation. The circuit avoids off-chip components, non-standard processes, and is thus suitable for ultra-low voltage low profile system-on-chip applications. The proposed system can deliver a regulated output voltage of 1.5 V at 31 μW output power with an input voltage as low as 0.2 V. The maximum simulated efficiency is 22% at the given step-up range. The design methodology of an integrated inductor layout and oscillator has been reported in detail for the standard process. At the ultra-low voltage range of interest, the regulator is estimated to have lower cost, higher integration, and improved efficiency compared to the alternatives reported in literature, including the 90 nm and 0.18 μm two-stage charge pump designs previously reported by our team.","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"287 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133989297","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352169
S. Muhammad, M. El-Moursy, A. El-Moursy, A. M. Refaat
Low leakage power with maintained high throughput NoC is achieved. Traffic-based Virtual channel Activation (TVA) algorithm is presented to determine traffic load status at the NoC switch ports. Consequently adaptation signals are sent to activate or deactivate switch port VC groups. The algorithm is optimized to minimize power dissipation for a target throughput. TVA algorithm optimally utilizes VCs by deactivating idle VCs groups to guarantee high leakage power saving without affecting the NoC throughput. Network average leakage power has been reduced for different topologies (such as 2D-Mesh and 2D-Torus).
{"title":"Optimization for traffic-based virtual channel activation low-power NoC","authors":"S. Muhammad, M. El-Moursy, A. El-Moursy, A. M. Refaat","doi":"10.1109/ICEAC.2015.7352169","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352169","url":null,"abstract":"Low leakage power with maintained high throughput NoC is achieved. Traffic-based Virtual channel Activation (TVA) algorithm is presented to determine traffic load status at the NoC switch ports. Consequently adaptation signals are sent to activate or deactivate switch port VC groups. The algorithm is optimized to minimize power dissipation for a target throughput. TVA algorithm optimally utilizes VCs by deactivating idle VCs groups to guarantee high leakage power saving without affecting the NoC throughput. Network average leakage power has been reduced for different topologies (such as 2D-Mesh and 2D-Torus).","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"340 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133674758","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352168
R. Tadros, A. H. Abdelrahman, M. Ghoneima, Y. Ismail
This paper presents a 24 Gbps SerDes transceiver circuit for on-chip high speed serial links for on-chip networks. The transceiver uses a proposed almost-differential self-timed 3-level signaling scheme, which works using a frequency of half the data rate for relaxing the design. Also, the third voltage level is created without the need for an external Vdd/2 supply source. Moreover, a 3-level inverter is proposed for the use in the front-end of both the TX and the RX. The transceiver is designed for a 5mm long lossy on-chip differential interconnect in GF 65nm CMOS technology. It serializes the parallel 3 Gbps 8-bit, and multiplexes them with the 12 GHz input clock. A simple RX extracts both the data and the clock from the same signals.
{"title":"A 24 Gbps SerDes transceiver for on-chip networks using a new half-data-rate self-timed 3-level signaling scheme","authors":"R. Tadros, A. H. Abdelrahman, M. Ghoneima, Y. Ismail","doi":"10.1109/ICEAC.2015.7352168","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352168","url":null,"abstract":"This paper presents a 24 Gbps SerDes transceiver circuit for on-chip high speed serial links for on-chip networks. The transceiver uses a proposed almost-differential self-timed 3-level signaling scheme, which works using a frequency of half the data rate for relaxing the design. Also, the third voltage level is created without the need for an external Vdd/2 supply source. Moreover, a 3-level inverter is proposed for the use in the front-end of both the TX and the RX. The transceiver is designed for a 5mm long lossy on-chip differential interconnect in GF 65nm CMOS technology. It serializes the parallel 3 Gbps 8-bit, and multiplexes them with the 12 GHz input clock. A simple RX extracts both the data and the clock from the same signals.","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125180378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352203
A. Rezk, A. Helmy, Y. Ismail
This paper presents the VHDL implementation of a novel power management algorithm for standalone PV-battery system. The algorithm performs two tasks, Maximum Power Point Tracking (MPPT) and dual load regulation. The MPPT is used to maximize the PV cells' output power, and is achieved by the “fractional open circuit voltage” method. The dual load regulation distributes the PV cells' output power among the loads, and delivers any surplus or deficit power to or from the battery. The proposed VHDL design has been synthesized on Xilinx using “5vlx50tff1136” as the target FPGA. The proposed design has utilized only 1% of the resources (slice registers and look-up-tables). This result has been found to be 23% lower than a previously implemented MPPT controller..
{"title":"VHDL implementation of a power management algorithm for PV-battery system","authors":"A. Rezk, A. Helmy, Y. Ismail","doi":"10.1109/ICEAC.2015.7352203","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352203","url":null,"abstract":"This paper presents the VHDL implementation of a novel power management algorithm for standalone PV-battery system. The algorithm performs two tasks, Maximum Power Point Tracking (MPPT) and dual load regulation. The MPPT is used to maximize the PV cells' output power, and is achieved by the “fractional open circuit voltage” method. The dual load regulation distributes the PV cells' output power among the loads, and delivers any surplus or deficit power to or from the battery. The proposed VHDL design has been synthesized on Xilinx using “5vlx50tff1136” as the target FPGA. The proposed design has utilized only 1% of the resources (slice registers and look-up-tables). This result has been found to be 23% lower than a previously implemented MPPT controller..","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130037605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352166
Furkan Ercan, A. Muhtaroğlu
Recent focus in energy efficiency is motivated with diminishing conventional energy resources, and increasing demand in low power applications with shrinking platform sizes. In this work, various threshold logic technologies are compared with each other in terms of power-delay-product (PDP). Compound CMOS, complementary pass transistor, static NAND gate, full adder, capacitive and differential threshold logic technologies are compared within a developed comparison scenario. Results in UMC180nm technology indicate that complementary pass transistor based threshold logic proves at least 2.5% more efficient than the rest in terms of PDP, while NAND based implementation has 29.2% better in terms of delay performance.
{"title":"Comparative power-delay performance analysis of threshold logic technologies","authors":"Furkan Ercan, A. Muhtaroğlu","doi":"10.1109/ICEAC.2015.7352166","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352166","url":null,"abstract":"Recent focus in energy efficiency is motivated with diminishing conventional energy resources, and increasing demand in low power applications with shrinking platform sizes. In this work, various threshold logic technologies are compared with each other in terms of power-delay-product (PDP). Compound CMOS, complementary pass transistor, static NAND gate, full adder, capacitive and differential threshold logic technologies are compared within a developed comparison scenario. Results in UMC180nm technology indicate that complementary pass transistor based threshold logic proves at least 2.5% more efficient than the rest in terms of PDP, while NAND based implementation has 29.2% better in terms of delay performance.","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122114305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352164
Khaled M. Ali, H. Mostafa, Tawfik Ismail
In this paper, a high-performance priority encoder is presented by using full custom approach. The proposed encoder provides both high- and low-priority functional with scalable design structure through a parallel look-ahead structure. A prefixing architecture is applied to minimize the critical path propagation delay and maximize the operating frequency. As a result, the proposed encoder is significant reduce the total critical delay by 53%, and the number of transistors by 7%, in addition it provides a regulated in building higher-order encoders. The results are conducted for different encoder inputs through TSMC 130nm CMOS technology.
{"title":"High performance layout-friendly 64-bit priority encoder utilizing parallel priority look-ahead","authors":"Khaled M. Ali, H. Mostafa, Tawfik Ismail","doi":"10.1109/ICEAC.2015.7352164","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352164","url":null,"abstract":"In this paper, a high-performance priority encoder is presented by using full custom approach. The proposed encoder provides both high- and low-priority functional with scalable design structure through a parallel look-ahead structure. A prefixing architecture is applied to minimize the critical path propagation delay and maximize the operating frequency. As a result, the proposed encoder is significant reduce the total critical delay by 53%, and the number of transistors by 7%, in addition it provides a regulated in building higher-order encoders. The results are conducted for different encoder inputs through TSMC 130nm CMOS technology.","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122660507","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352193
Yasmine El-Sayed, Amr Wageeh, Tawfik Ismail, H. Mostafa
All-Optical Clock and Data Recovery (OCDR) is an important function for future optical networks and optical signal processing. The OCDR realizes a long-distance optical data transmission system by restoring the incoming data and then retransmitting. The Self-Pulsating (SP) lasers are the promising technologies to enable fast and high-speed data recovery system in an optical domain. In this paper, we design and implement the OCDR based on two SP laser types, Amplified Feedback Laser (AFL) and Distributed Bragg Reflector Laser (DBRL). A comparative study and measurement of the network performance for the two types have been presented.
{"title":"All-optical clock and data recovery using self-pulsating lasers for high-speed optical networks","authors":"Yasmine El-Sayed, Amr Wageeh, Tawfik Ismail, H. Mostafa","doi":"10.1109/ICEAC.2015.7352193","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352193","url":null,"abstract":"All-Optical Clock and Data Recovery (OCDR) is an important function for future optical networks and optical signal processing. The OCDR realizes a long-distance optical data transmission system by restoring the incoming data and then retransmitting. The Self-Pulsating (SP) lasers are the promising technologies to enable fast and high-speed data recovery system in an optical domain. In this paper, we design and implement the OCDR based on two SP laser types, Amplified Feedback Laser (AFL) and Distributed Bragg Reflector Laser (DBRL). A comparative study and measurement of the network performance for the two types have been presented.","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122326601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352163
Mazen Al Haddad, M. Bayoumi
Mobile data traffic has skyrocketed in recent years and will continue to grow and demand more capacity. Continued heterogeneous networks' evolution and the utilization of massive Femtocell deployments will facilitate the meeting of capacity demands as expected towards 5G and telecom 2020-vision. The CO2 footprint of power usage is becoming spotlighted and energy-aware solutions are required. This paper reviews recent Femtocell downlink power control frameworks and proposes a novel comprehensive one taking into consideration issues like intra-interference (Femto-Femto), dense-deployments and environmental impact. Simulation results show up to 68% user throughput improvement and up to 20.69kg/year CO2-emission reduction for one Femtocell.
{"title":"Green energy solution for femtocell power control in massive deployments","authors":"Mazen Al Haddad, M. Bayoumi","doi":"10.1109/ICEAC.2015.7352163","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352163","url":null,"abstract":"Mobile data traffic has skyrocketed in recent years and will continue to grow and demand more capacity. Continued heterogeneous networks' evolution and the utilization of massive Femtocell deployments will facilitate the meeting of capacity demands as expected towards 5G and telecom 2020-vision. The CO2 footprint of power usage is becoming spotlighted and energy-aware solutions are required. This paper reviews recent Femtocell downlink power control frameworks and proposes a novel comprehensive one taking into consideration issues like intra-interference (Femto-Femto), dense-deployments and environmental impact. Simulation results show up to 68% user throughput improvement and up to 20.69kg/year CO2-emission reduction for one Femtocell.","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133083646","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352197
Karim O. Ragab, H. Mostafa, A. Eladawy
This paper introduces a new algorithm and circuit design of Time-to-Digital Converter(TDC) with modified Successive Approximation Register(SAR) algorithm. This design enables continuous pulse disassemble. The input pulse is absolutely compared to pulses of widths proportional to Vfs/2, Vfs/4..Vfs/N, and each bit is evaluated independent of the previous bit result. Then bits correction is applied after the sample evaluation. A 4bit case study circuit is realized using TSMC CMOS 65nm design technology. The design demonstrated 3.67 Effective Number Of Bits (ENOB) for a sampling frequency of 666 MSs.
本文介绍了一种基于改进逐次逼近寄存器(SAR)算法的时间-数字转换器(TDC)的新算法和电路设计。这种设计可以实现连续脉冲拆卸。输入脉冲绝对与宽度与Vfs/2, Vfs/4成正比的脉冲进行比较。Vfs/N，并且每个位的求值与前一位的结果无关。然后在样本评估后进行比特校正。采用台积电CMOS 65nm设计技术，实现了一个4bit的案例研究电路。该设计在666 MS / s的采样频率下实现了3.67有效比特数(ENOB)。
{"title":"TDC SAR algorithm with continuous disassembly (SAR-CD) for time-based ADCs","authors":"Karim O. Ragab, H. Mostafa, A. Eladawy","doi":"10.1109/ICEAC.2015.7352197","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352197","url":null,"abstract":"This paper introduces a new algorithm and circuit design of Time-to-Digital Converter(TDC) with modified Successive Approximation Register(SAR) algorithm. This design enables continuous pulse disassemble. The input pulse is absolutely compared to pulses of widths proportional to Vfs/2, Vfs/4..Vfs/N, and each bit is evaluated independent of the previous bit result. Then bits correction is applied after the sample evaluation. A 4bit case study circuit is realized using TSMC CMOS 65nm design technology. The design demonstrated 3.67 Effective Number Of Bits (ENOB) for a sampling frequency of 666 MSs.","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124538896","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：