Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352196
Fassahat U. Qureshi, A. Muhtaroğlu, K. Tuncay
Batteries are commonly used to power sensors, a fact that carries severe drawbacks such as limited lifetime and regular replacement. Battery powered sensors are particularly impractical in under-water pipelines due to limited access. Therefore, harvesting of ambient energy to power embedded sensors is an attractive option for such systems. A method is proposed, in this paper, to power in-pipe wireless sensor nodes based on energy harvesting techniques, with minimal impact to the pipe performance. Based on the initial analysis presented in the paper, models will be developed next to facilitate the design of an energy harvester system for Turkey-Cyprus water pipeline project currently under construction.
{"title":"A method to integrate energy harvesters into wireless sensor nodes for embedded in-pipe monitoring applications","authors":"Fassahat U. Qureshi, A. Muhtaroğlu, K. Tuncay","doi":"10.1109/ICEAC.2015.7352196","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352196","url":null,"abstract":"Batteries are commonly used to power sensors, a fact that carries severe drawbacks such as limited lifetime and regular replacement. Battery powered sensors are particularly impractical in under-water pipelines due to limited access. Therefore, harvesting of ambient energy to power embedded sensors is an attractive option for such systems. A method is proposed, in this paper, to power in-pipe wireless sensor nodes based on energy harvesting techniques, with minimal impact to the pipe performance. Based on the initial analysis presented in the paper, models will be developed next to facilitate the design of an energy harvester system for Turkey-Cyprus water pipeline project currently under construction.","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125620458","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352208
D. Guttman, M. Kandemir, Meenakshi Arunachalam, R. Khanna
With the advent of teraflop-scale computing on both a single coprocessor and many-core designs, there is tremendous need for techniques to fully utilize the compute power by keeping cores fed with data. Data prefetching has been used as a popular method to hide memory latencies by fetching data proactively before the processor needs the data. Fetching data ahead of time from the memory subsystem into faster caches reduces observable latencies or wait times on the processor end and this improves overall program execution times. We study two types of prefetching techniques that are available on a 61-core Intel Xeon Phi co-processor, namely software (compiler-guided) prefetching and hardware prefetching on a variety of workloads. Using machine learning techniques, we synthesize workload phases and the sequence of phase patterns using raw performance data from hardware counters such as memory bandwidth, miss ratios, prefetches issued, etc. Furthermore, we use performance data from workloads with different impacts and behaviors under various prefetcher settings. Our contribution can help in future prefetching design in the following ways: (1) to identify phases within workloads that have different characteristics and behaviors and help dynamically modify prefetch types and intensities to suit the phase; (2) to manage auto setting of prefetcher knobs without great effort from the user; (3) to influence software and hardware prefetching interaction designs in future processors; and (4) to use valuable insights and performance data in many areas such as power provisioning for the nodes in a large cluster to maximize both energy and performance efficiencies.
{"title":"Machine learning techniques for improved data prefetching","authors":"D. Guttman, M. Kandemir, Meenakshi Arunachalam, R. Khanna","doi":"10.1109/ICEAC.2015.7352208","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352208","url":null,"abstract":"With the advent of teraflop-scale computing on both a single coprocessor and many-core designs, there is tremendous need for techniques to fully utilize the compute power by keeping cores fed with data. Data prefetching has been used as a popular method to hide memory latencies by fetching data proactively before the processor needs the data. Fetching data ahead of time from the memory subsystem into faster caches reduces observable latencies or wait times on the processor end and this improves overall program execution times. We study two types of prefetching techniques that are available on a 61-core Intel Xeon Phi co-processor, namely software (compiler-guided) prefetching and hardware prefetching on a variety of workloads. Using machine learning techniques, we synthesize workload phases and the sequence of phase patterns using raw performance data from hardware counters such as memory bandwidth, miss ratios, prefetches issued, etc. Furthermore, we use performance data from workloads with different impacts and behaviors under various prefetcher settings. Our contribution can help in future prefetching design in the following ways: (1) to identify phases within workloads that have different characteristics and behaviors and help dynamically modify prefetch types and intensities to suit the phase; (2) to manage auto setting of prefetcher knobs without great effort from the user; (3) to influence software and hardware prefetching interaction designs in future processors; and (4) to use valuable insights and performance data in many areas such as power provisioning for the nodes in a large cluster to maximize both energy and performance efficiencies.","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"90 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125394935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352200
M. Abo-Zahhad, M. Farrag, Abdelhay Ali, Osama Amin
Energy consumption and energy modeling are important issues in designing and implementing of Wireless Sensor Networks (WSNs), which help the designers to optimize the energy consumption in WSN nodes. Good knowledge of the sources of energy consumption in WSNs is the first step to reduce energy consumption. Therefore, an accurate energy model is required for the evaluation of communication protocols. In this paper, we provide an energy model for WSNs considering the physical layer and MAC layer parameters by determining the energy consumed per payload bit transferred without error over AWGN channel. We show how the transmission power must be chosen in order to achieve energy-efficient communications over AWGN channel. We also find that, for each modulation scheme, there are optimal transmission power at which the energy consumption is minimized. Moreover, we investigated the energy saving gained from optimizing the constellation size.
{"title":"An energy consumption model for wireless sensor networks","authors":"M. Abo-Zahhad, M. Farrag, Abdelhay Ali, Osama Amin","doi":"10.1109/ICEAC.2015.7352200","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352200","url":null,"abstract":"Energy consumption and energy modeling are important issues in designing and implementing of Wireless Sensor Networks (WSNs), which help the designers to optimize the energy consumption in WSN nodes. Good knowledge of the sources of energy consumption in WSNs is the first step to reduce energy consumption. Therefore, an accurate energy model is required for the evaluation of communication protocols. In this paper, we provide an energy model for WSNs considering the physical layer and MAC layer parameters by determining the energy consumed per payload bit transferred without error over AWGN channel. We show how the transmission power must be chosen in order to achieve energy-efficient communications over AWGN channel. We also find that, for each modulation scheme, there are optimal transmission power at which the energy consumption is minimized. Moreover, we investigated the energy saving gained from optimizing the constellation size.","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125070804","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352201
Mainul Hassan, Mengshen Zhao, Seong‐Ho Son, Hyung-seok Lee, Hyung-Geun Kim, B. Jang
Face detection is one of the most popular computer vision applications on mobile platforms. It is a compute-intensive task that consumes significant energy. In this paper, we present an energy efficient face detection implementation that offloads data- and compute-intensive portions of the application onto low-power mobile GPU to save overall power consumption without sacrificing performance. Our experiment on a state-of-the-art mobile processor demonstrates that our proposed approach saves power consumption up to 14.3% and improves performance by 87% over traditional CPU only execution.
{"title":"A low power and high performance face detection on mobile GPU","authors":"Mainul Hassan, Mengshen Zhao, Seong‐Ho Son, Hyung-seok Lee, Hyung-Geun Kim, B. Jang","doi":"10.1109/ICEAC.2015.7352201","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352201","url":null,"abstract":"Face detection is one of the most popular computer vision applications on mobile platforms. It is a compute-intensive task that consumes significant energy. In this paper, we present an energy efficient face detection implementation that offloads data- and compute-intensive portions of the application onto low-power mobile GPU to save overall power consumption without sacrificing performance. Our experiment on a state-of-the-art mobile processor demonstrates that our proposed approach saves power consumption up to 14.3% and improves performance by 87% over traditional CPU only execution.","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116820123","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352171
Hoda Abdelsalam, E. Hegazi, H. Mostafa, Y. Ismail
This paper presents a digitally controlled RF charge sampling receiver font-end architecture for multiband multi standard RF receivers. A time-varying matching network is proposed instead of traditional ones. The receiver operates in charge domain to produce a band pass Sinc filter centered at the desired local oscillator frequency. A time varying matching network provides tunable matching and selectivity to support multi-bands. This receiver architecture targets LTE band (0.7-2.7) GHz making use of its programmability. Based on a verilogA model, the receiver conversion gain is 33 dB at 2 GHz; the resulting noise figure is 7.3dB, and P1dB and IIP3 of -10dBm are 0 dBm respectively.
{"title":"A tunable receiver architecture utilizing time-varying matching network for a universal receiver","authors":"Hoda Abdelsalam, E. Hegazi, H. Mostafa, Y. Ismail","doi":"10.1109/ICEAC.2015.7352171","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352171","url":null,"abstract":"This paper presents a digitally controlled RF charge sampling receiver font-end architecture for multiband multi standard RF receivers. A time-varying matching network is proposed instead of traditional ones. The receiver operates in charge domain to produce a band pass Sinc filter centered at the desired local oscillator frequency. A time varying matching network provides tunable matching and selectivity to support multi-bands. This receiver architecture targets LTE band (0.7-2.7) GHz making use of its programmability. Based on a verilogA model, the receiver conversion gain is 33 dB at 2 GHz; the resulting noise figure is 7.3dB, and P1dB and IIP3 of -10dBm are 0 dBm respectively.","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130294222","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352194
Osama Abdelkader, H. Mostafa, H. A. Elhamid, A. Soliman
Comparisons of FinFET based ring oscillator (RO) metrics are evaluated with technology scaling from 20nm to 7nm technology. Simulations are based on predictive technology models (PTM) developed by Arizona state university. The impact of process and temperature variations on frequency, power, and power delay product is reported. Performance and power of the RO are improved with technology scaling, however performance is degraded after 14nm technology.
{"title":"The impact of FinFET technology scaling on critical path performance under process variations","authors":"Osama Abdelkader, H. Mostafa, H. A. Elhamid, A. Soliman","doi":"10.1109/ICEAC.2015.7352194","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352194","url":null,"abstract":"Comparisons of FinFET based ring oscillator (RO) metrics are evaluated with technology scaling from 20nm to 7nm technology. Simulations are based on predictive technology models (PTM) developed by Arizona state university. The impact of process and temperature variations on frequency, power, and power delay product is reported. Performance and power of the RO are improved with technology scaling, however performance is degraded after 14nm technology.","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"169 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132291995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352205
Abdullah Abdulslam, Y. Ismail
In this paper, a 5-level buck converter is proposed. The circuit structure and the working principle are illustrated. The circuit is capable of providing five different voltage levels at the inductor input with the help of two flying capacitors. The 5-level buck converter can work at different operation regions covering wide range of output voltage values. By reducing the voltage difference at the inductor input, the 5-level buck converter can use smaller inductor compared to both 3-level and conventional buck converters which makes it more suitable for on-chip DC-DC conversion. A test circuit has been implemented in TSMC 65nm technology using 0.5nH on-chip spiral inductor and simulation results show better performance as compared to conventional and 3-level buck converters. For same switching frequency and inductor size, the 5-level buck converter achieves more than a 15% efficiency improvement over a 3-level buck converter at certain output voltage ranges.
{"title":"5-Level buck converter with reduced inductor size suitable for on-chip integration","authors":"Abdullah Abdulslam, Y. Ismail","doi":"10.1109/ICEAC.2015.7352205","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352205","url":null,"abstract":"In this paper, a 5-level buck converter is proposed. The circuit structure and the working principle are illustrated. The circuit is capable of providing five different voltage levels at the inductor input with the help of two flying capacitors. The 5-level buck converter can work at different operation regions covering wide range of output voltage values. By reducing the voltage difference at the inductor input, the 5-level buck converter can use smaller inductor compared to both 3-level and conventional buck converters which makes it more suitable for on-chip DC-DC conversion. A test circuit has been implemented in TSMC 65nm technology using 0.5nH on-chip spiral inductor and simulation results show better performance as compared to conventional and 3-level buck converters. For same switching frequency and inductor size, the 5-level buck converter achieves more than a 15% efficiency improvement over a 3-level buck converter at certain output voltage ranges.","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132932689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352198
H. Uluşan, Ö. Zorlu, H. Kulah, A. Muhtaroğlu
This paper presents a performance enhancement feature for a novel power management circuit to generate 1.8 V from the low DC voltage rectified at the output of the vibration-based electromagnetic (EM) energy harvesters. The proposed 180 nm circuit utilizes a low voltage charge pump based boost converter with variable output-stages, and an autonomous regulator circuit with negative feedback topology. 2 and 3 stage charge pump options in the variable stage configuration has been validated to extend the supported input voltage range at the same load, or alternatively maintain higher efficiency operation at a higher load range. The simulation results showed that under no-load condition the output voltage reached to 1.8 V for input voltage of 0.65 V and 0.48 V with 2 and 3 stage outputs, respectively. The power conversion efficiency of the power management circuit can be kept stable around 55% by switching from 2 to 3 stages after 3.5 μA.
{"title":"Stage optimization in regulated step-up for low voltage electromagnetic energy harvesters","authors":"H. Uluşan, Ö. Zorlu, H. Kulah, A. Muhtaroğlu","doi":"10.1109/ICEAC.2015.7352198","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352198","url":null,"abstract":"This paper presents a performance enhancement feature for a novel power management circuit to generate 1.8 V from the low DC voltage rectified at the output of the vibration-based electromagnetic (EM) energy harvesters. The proposed 180 nm circuit utilizes a low voltage charge pump based boost converter with variable output-stages, and an autonomous regulator circuit with negative feedback topology. 2 and 3 stage charge pump options in the variable stage configuration has been validated to extend the supported input voltage range at the same load, or alternatively maintain higher efficiency operation at a higher load range. The simulation results showed that under no-load condition the output voltage reached to 1.8 V for input voltage of 0.65 V and 0.48 V with 2 and 3 stage outputs, respectively. The power conversion efficiency of the power management circuit can be kept stable around 55% by switching from 2 to 3 stages after 3.5 μA.","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122389444","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352172
A. Salaheldin, Karim Abdallah, N. Gamal, H. Mostafa
Nowadays, FPGAs serve as Fields Programmable Systems on Chip (FPSoC) and are widely used to implement computationally intensive world applications. As the number of components in FPSoCs increases, the interconnect schemes based on Network on Chip (NoC) approach are increasingly used to overcome the problems of traditional bus based and point-to-point interconnect scheme. In this paper, we review several designs based on their contributions, architectures, implementations and future works. We also made our comparison between three of these routes to analyze the effect of varying the number of Virtual Channels (VCs), flit data width and buffer depth on the operating frequency, Logic Look-Up Tables (LUTs) and registers to help choosing the appropriate NoC based on system requirements.
如今，fpga作为现场可编程芯片系统(FPSoC)被广泛用于实现计算密集型的世界应用。随着fpsoc中元器件数量的增加，基于片上网络(Network on Chip, NoC)的互连方案越来越多地用于克服传统的基于总线和点对点的互连方案所存在的问题。在本文中，我们根据他们的贡献、架构、实现和未来的工作来回顾几种设计。我们还对这三种路由进行了比较，以分析改变虚拟通道(vc)数量、飞行数据宽度和缓冲区深度对工作频率、逻辑查找表(lut)和寄存器的影响，以帮助根据系统要求选择适当的NoC。
{"title":"Review of NoC-based FPGAs architectures","authors":"A. Salaheldin, Karim Abdallah, N. Gamal, H. Mostafa","doi":"10.1109/ICEAC.2015.7352172","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352172","url":null,"abstract":"Nowadays, FPGAs serve as Fields Programmable Systems on Chip (FPSoC) and are widely used to implement computationally intensive world applications. As the number of components in FPSoCs increases, the interconnect schemes based on Network on Chip (NoC) approach are increasingly used to overcome the problems of traditional bus based and point-to-point interconnect scheme. In this paper, we review several designs based on their contributions, architectures, implementations and future works. We also made our comparison between three of these routes to analyze the effect of varying the number of Virtual Channels (VCs), flit data width and buffer depth on the operating frequency, Logic Look-Up Tables (LUTs) and registers to help choosing the appropriate NoC based on system requirements.","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130334452","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-03-24DOI: 10.1109/ICEAC.2015.7352170
K. Ali, E. Yahya, A. El-Rouby, Y. Ismail
This paper presents characterization for coupling capacitance in through silicon Vias (TSV) arrays. Two scenarios are proposed to estimate the coupling capacitance between TSVs in TSVs array. First scenario is by using a closed form expression that accounts for the shielding effect resulted by TSVs. Second scenario is based on the existence of initial measured capacitance value at certain dimensions, thereafter the capacitance values can be obtained at other dimensions using scaling equations.
{"title":"Different scenarios for estimating coupling capacitances of through silicon via (TSV) arrays","authors":"K. Ali, E. Yahya, A. El-Rouby, Y. Ismail","doi":"10.1109/ICEAC.2015.7352170","DOIUrl":"https://doi.org/10.1109/ICEAC.2015.7352170","url":null,"abstract":"This paper presents characterization for coupling capacitance in through silicon Vias (TSV) arrays. Two scenarios are proposed to estimate the coupling capacitance between TSVs in TSVs array. First scenario is by using a closed form expression that accounts for the shielding effect resulted by TSVs. Second scenario is based on the existence of initial measured capacitance value at certain dimensions, thereafter the capacitance values can be obtained at other dimensions using scaling equations.","PeriodicalId":334594,"journal":{"name":"5th International Conference on Energy Aware Computing Systems & Applications","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2015-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115269360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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