Jones O. Albuquerque, C. Coelho, C. F. Cavalcanti, D. Silva, A. O. Fernandes
Several models and algorithms have been proposed in the past to generate HW/SW components for system-level designs. However, they were focused on a single designer who had a throughout knowledge of the design. In other words, the decision trade-offs were simplified to a stand-alone developer who did not have to consider individual skills, concurrent development for portions of the design, risk analysis for time-to-market development, nor team load and assignment. In this paper, we propose a design management approach associated with a partitioning methodology to deal with the concurrent design problems of system-level specifications. This methodology allows one to incorporate the uncertainties related to development at the very early stages of the design, and to follow up during the development of a final product.
{"title":"System-level partitioning with uncertainty","authors":"Jones O. Albuquerque, C. Coelho, C. F. Cavalcanti, D. Silva, A. O. Fernandes","doi":"10.1145/301177.301531","DOIUrl":"https://doi.org/10.1145/301177.301531","url":null,"abstract":"Several models and algorithms have been proposed in the past to generate HW/SW components for system-level designs. However, they were focused on a single designer who had a throughout knowledge of the design. In other words, the decision trade-offs were simplified to a stand-alone developer who did not have to consider individual skills, concurrent development for portions of the design, risk analysis for time-to-market development, nor team load and assignment. In this paper, we propose a design management approach associated with a partitioning methodology to deal with the concurrent design problems of system-level specifications. This methodology allows one to incorporate the uncertainties related to development at the very early stages of the design, and to follow up during the development of a final product.","PeriodicalId":344739,"journal":{"name":"Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130455668","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We describe an approach for application-specific processor design based on an extendible microprocessor core. Core-based design allows to derive application-specific instruction processors from a common base architecture with low non-recurring engineering cost. The results of this application-specific customization of a common base architecture are families of related and largely compatible processor families. These families can share support tools and even binary compatible code which has been written for the common base architecture. Critical code portions are customized using the application-specific instruction set extensions. We describe a hardware/software co-design methodology which can be used with this design approach. The presented approach uses the processor core to allow early evaluation of ASIP design options using rapid prototyping techniques. We demonstrate this approach with two case studies, based on the implementation and evaluation of application-specific processor extensions for Prolog program execution, and memory prefetching for vector and matrix operations.
{"title":"Instruction set selection for ASIP design","authors":"M. Gschwind","doi":"10.1145/301177.301187","DOIUrl":"https://doi.org/10.1145/301177.301187","url":null,"abstract":"We describe an approach for application-specific processor design based on an extendible microprocessor core. Core-based design allows to derive application-specific instruction processors from a common base architecture with low non-recurring engineering cost. The results of this application-specific customization of a common base architecture are families of related and largely compatible processor families. These families can share support tools and even binary compatible code which has been written for the common base architecture. Critical code portions are customized using the application-specific instruction set extensions. We describe a hardware/software co-design methodology which can be used with this design approach. The presented approach uses the processor core to allow early evaluation of ASIP design options using rapid prototyping techniques. We demonstrate this approach with two case studies, based on the implementation and evaluation of application-specific processor extensions for Prolog program execution, and memory prefetching for vector and matrix operations.","PeriodicalId":344739,"journal":{"name":"Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450)","volume":"191 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128195430","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper addresses the problem of exploring tradeoffs between program memory, data memory and execution time requirements (3D) for DSP algorithms specified by data flow graphs. Such an exploration is of utmost importance for being able to analyse the feasibility and range of possible software solutions as part of a hardware/software codesign methodology where the target processor and the code generation style may lead to complete different solutions of the same specification. For solving this multi-objective optimization problem, an Evolutionary Algorithm approach is applied. In particular, a new Pareto-optimization algorithm is introduced. For different well-known target DSP processors, the Pareto-fronts are analyzed and compared.
{"title":"3D exploration of software schedules for DSP algorithms","authors":"J. Teich, E. Zitzler, S. Bhattacharyya","doi":"10.1145/301177.301522","DOIUrl":"https://doi.org/10.1145/301177.301522","url":null,"abstract":"This paper addresses the problem of exploring tradeoffs between program memory, data memory and execution time requirements (3D) for DSP algorithms specified by data flow graphs. Such an exploration is of utmost importance for being able to analyse the feasibility and range of possible software solutions as part of a hardware/software codesign methodology where the target processor and the code generation style may lead to complete different solutions of the same specification. For solving this multi-objective optimization problem, an Evolutionary Algorithm approach is applied. In particular, a new Pareto-optimization algorithm is introduced. For different well-known target DSP processors, the Pareto-fronts are analyzed and compared.","PeriodicalId":344739,"journal":{"name":"Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120955296","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we present experimental results obtained during the modelling, design and implementation of a full set of versions of SPARC v8 integer unit core aimed for embedded applications in digital media products. VHDL has been the description language, Synopsis tools those for the logical synthesis, and Duet Technologies' Epoch has been used for the physical layout of the final circuits. They have been mapped to a 0.35 /spl mu/m, three metal layers process. The quantitative results given characterize suitable points in the design space. They show how much microarchitecture, design, datapath granularity and module decisions affect performance and cost functions. Design space exploration down to physical layouts is made possible by modelling techniques based on configurable VHDL descriptions.
{"title":"Flexible design of SPARC cores: a quantitative study","authors":"T. Bautista, A. Núñez","doi":"10.1145/301177.301200","DOIUrl":"https://doi.org/10.1145/301177.301200","url":null,"abstract":"In this paper we present experimental results obtained during the modelling, design and implementation of a full set of versions of SPARC v8 integer unit core aimed for embedded applications in digital media products. VHDL has been the description language, Synopsis tools those for the logical synthesis, and Duet Technologies' Epoch has been used for the physical layout of the final circuits. They have been mapped to a 0.35 /spl mu/m, three metal layers process. The quantitative results given characterize suitable points in the design space. They show how much microarchitecture, design, datapath granularity and module decisions affect performance and cost functions. Design space exploration down to physical layouts is made possible by modelling techniques based on configurable VHDL descriptions.","PeriodicalId":344739,"journal":{"name":"Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126301565","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Karsten Strehl, L. Thiele, D. Ziegenbein, R. Ernst, J. Teich
In this paper, a scheduling method for heterogeneous embedded systems is developed. At first, an internal representation model called FunState is presented which enables the explicit representation of non-determinism and scheduling using a combination of functions and state machines. The new scheduling method is able to deal with mixed data/control flow specifications and takes into account different mechanisms of non-determinism as occurring in the design of embedded systems. Constraints imposed by other already implemented components are respected. The scheduling approach avoids the explicit enumeration of execution paths by using symbolic techniques and guarantees to find a deadlock-free and bounded schedule if one exists. The generated schedule consists of statically scheduled basic blocks which are dynamically called at run time.
{"title":"Scheduling hardware/software systems using symbolic techniques","authors":"Karsten Strehl, L. Thiele, D. Ziegenbein, R. Ernst, J. Teich","doi":"10.1145/301177.301523","DOIUrl":"https://doi.org/10.1145/301177.301523","url":null,"abstract":"In this paper, a scheduling method for heterogeneous embedded systems is developed. At first, an internal representation model called FunState is presented which enables the explicit representation of non-determinism and scheduling using a combination of functions and state machines. The new scheduling method is able to deal with mixed data/control flow specifications and takes into account different mechanisms of non-determinism as occurring in the design of embedded systems. Constraints imposed by other already implemented components are respected. The scheduling approach avoids the explicit enumeration of execution paths by using symbolic techniques and guarantees to find a deadlock-free and bounded schedule if one exists. The generated schedule consists of statically scheduled basic blocks which are dynamically called at run time.","PeriodicalId":344739,"journal":{"name":"Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130647770","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tomorrow's silicon chips will hold more transistors than most embedded system designers could possibly use under the prevalent "describe-and-synthesize" design paradigm. Many have thus re-proposed the once popular "capture-and-simulate" paradigm, wherein pre-designed Intellectual Property software and hardware components are connected and co-simulated, to reduce this gap. However, major hurdles limit this paradigm to only very high-cost embedded systems. In this paper, we describe those hurdles and present a case for a new "configure-and-execute" paradigm for mainstream embedded systems, based on the idea of deconstructing rather than constructing systems, which takes advantage of the surplus transistors in a way that can overcome the hurdles and significantly reduce time-to-market.
{"title":"The case for a configure-and-execute paradigm","authors":"F. Vahid, T. Givargis","doi":"10.1145/301177.301211","DOIUrl":"https://doi.org/10.1145/301177.301211","url":null,"abstract":"Tomorrow's silicon chips will hold more transistors than most embedded system designers could possibly use under the prevalent \"describe-and-synthesize\" design paradigm. Many have thus re-proposed the once popular \"capture-and-simulate\" paradigm, wherein pre-designed Intellectual Property software and hardware components are connected and co-simulated, to reduce this gap. However, major hurdles limit this paradigm to only very high-cost embedded systems. In this paper, we describe those hurdles and present a case for a new \"configure-and-execute\" paradigm for mainstream embedded systems, based on the idea of deconstructing rather than constructing systems, which takes advantage of the surplus transistors in a way that can overcome the hurdles and significantly reduce time-to-market.","PeriodicalId":344739,"journal":{"name":"Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450)","volume":"447 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132995796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the growth of System on a Chip (SoC), the functionality of analog components must also be considered in the design process. This paper describes some of the design implementation partitioning issues and experiences using analog and digital techniques for embedded systems. To achieve a quick turn around for new embedded system development, a design methodology was extended for analog codesign based on the specify-explore-refine paradigm and system-level design methodology. Many system-level issues were addressed including hardware/software codesign trade-offs.
{"title":"Using codesign techniques to support analog functionality","authors":"F. Wolff, M. Knieser, D. Weyer, C. Papachristou","doi":"10.1145/301177.301492","DOIUrl":"https://doi.org/10.1145/301177.301492","url":null,"abstract":"With the growth of System on a Chip (SoC), the functionality of analog components must also be considered in the design process. This paper describes some of the design implementation partitioning issues and experiences using analog and digital techniques for embedded systems. To achieve a quick turn around for new embedded system development, a design methodology was extended for analog codesign based on the specify-explore-refine paradigm and system-level design methodology. Many system-level issues were addressed including hardware/software codesign trade-offs.","PeriodicalId":344739,"journal":{"name":"Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132611060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a concept called hierarchically grouped message to improve the performance of geographically distributed timed cosimulation. In the proposed method, messages which are transferred between simulators in a short period of simulated time are hierarchically grouped into a physical message to reduce the number of rollbacks in optimistic simulation as well as the communication overhead of message transfer. Experiments show the efficiency of the proposed method in an internationally distributed cosimulation environment.
{"title":"Optimizing geographically distributed timed cosimulation by hierarchically grouped messages","authors":"S. Yoo, Kiyoung Choi","doi":"10.1109/HSC.1999.777401","DOIUrl":"https://doi.org/10.1109/HSC.1999.777401","url":null,"abstract":"This paper presents a concept called hierarchically grouped message to improve the performance of geographically distributed timed cosimulation. In the proposed method, messages which are transferred between simulators in a short period of simulated time are hierarchically grouped into a physical message to reduce the number of rollbacks in optimistic simulation as well as the communication overhead of message transfer. Experiments show the efficiency of the proposed method in an internationally distributed cosimulation environment.","PeriodicalId":344739,"journal":{"name":"Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130871847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we propose a fast and simple heuristic for the cosynthesis problem targeting the system-on-chip (SOC) design. The proposed algorithm covers from implementation selection and resource sharing problem in SOC design to PE selection problems in distributed heterogeneous embedded (DHE) system design. The proposed solution also considers multiple design objectives. Through benchmark experimentation, it is proven that the proposed solution produces solutions of equivalent quality to the previously published results in the DHE design. Its execution speed is several orders of magnitude smaller for large examples. We envision that the proposed approach will be one of significant cosynthesis researches in the SOC design. In the DHE design, the proposed approach could be used as an initial solution to a probabilistic algorithm guaranteeing to obtain a better solution.
{"title":"A hardware-software cosynthesis technique based on heterogeneous multiprocessor scheduling","authors":"Hyunok Oh, S. Ha","doi":"10.1109/HSC.1999.777429","DOIUrl":"https://doi.org/10.1109/HSC.1999.777429","url":null,"abstract":"In this paper, we propose a fast and simple heuristic for the cosynthesis problem targeting the system-on-chip (SOC) design. The proposed algorithm covers from implementation selection and resource sharing problem in SOC design to PE selection problems in distributed heterogeneous embedded (DHE) system design. The proposed solution also considers multiple design objectives. Through benchmark experimentation, it is proven that the proposed solution produces solutions of equivalent quality to the previously published results in the DHE design. Its execution speed is several orders of magnitude smaller for large examples. We envision that the proposed approach will be one of significant cosynthesis researches in the SOC design. In the DHE design, the proposed approach could be used as an initial solution to a probabilistic algorithm guaranteeing to obtain a better solution.","PeriodicalId":344739,"journal":{"name":"Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450)","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115717514","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we develop a formal framework to widen the scope of retargetable compilation. The goal is achieved by the unification of architectural models for both the processor architecture and the ASIC architecture. This framework enables the unified treatment of code generation and behavioral synthesis, and is being used in our experimental codesign environment to drive system-on-a-chip synthesis from an object oriented language.
{"title":"A unified formal model of ISA and FSMD","authors":"Jianwen Zhu, D. Gajski","doi":"10.1145/301177.301504","DOIUrl":"https://doi.org/10.1145/301177.301504","url":null,"abstract":"In this paper, we develop a formal framework to widen the scope of retargetable compilation. The goal is achieved by the unification of architectural models for both the processor architecture and the ASIC architecture. This framework enables the unified treatment of code generation and behavioral synthesis, and is being used in our experimental codesign environment to drive system-on-a-chip synthesis from an object oriented language.","PeriodicalId":344739,"journal":{"name":"Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122029512","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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