This paper introduces a flexible code generation framework dedicated to the design of application specific programmable processors. This tool allows the user to build specific compilation flows, using a library of modules, implementing flexible compilation passes such as code generation, resource allocation, scheduling, etc. Retargeting is performed at two levels: minor changes in the target processor architecture are handled by a retargeting of the modules of the defined compilation flow, while major modifications require a structural modification of the flow. To build a compiler for a target processor, the user selects modules from the library, and links them together. While the global compiler structure is user-defined, the retargeting of modules is automatically performed by the framework. Target processors are described using ARMOR, a programmable processor modeling language especially defined for design space exploration. The proposed tool is then suitable for a large range of instruction set architectures.
{"title":"A flexible code generation framework for the design of application specific programmable processors","authors":"François Charot, V. Messé","doi":"10.1145/301177.301194","DOIUrl":"https://doi.org/10.1145/301177.301194","url":null,"abstract":"This paper introduces a flexible code generation framework dedicated to the design of application specific programmable processors. This tool allows the user to build specific compilation flows, using a library of modules, implementing flexible compilation passes such as code generation, resource allocation, scheduling, etc. Retargeting is performed at two levels: minor changes in the target processor architecture are handled by a retargeting of the modules of the defined compilation flow, while major modifications require a structural modification of the flow. To build a compiler for a target processor, the user selects modules from the library, and links them together. While the global compiler structure is user-defined, the retargeting of modules is automatically performed by the framework. Target processors are described using ARMOR, a programmable processor modeling language especially defined for design space exploration. The proposed tool is then suitable for a large range of instruction set architectures.","PeriodicalId":344739,"journal":{"name":"Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450)","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132405979","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes a new design flow that significantly reduces time-to-market for highly complex multiprocessor-based system-on-chip (SOC) designs. This flow, put in place within STMicroelectronics and which is called fast prototyping, allows concurrent hardware and software development, early verification and enables the productive re-use of intellectual property. We describe how using this innovative system design flow, that combines different technologies, such as C modeling, emulation, hard virtual component re-use and CoWare N2C, we achieve better productivity on a multiprocessor SOC design.
{"title":"Fast prototyping: a system design flow for fast design, prototyping and efficient IP reuse","authors":"F. Pogodalla, R. Hersemeule, P. Coulomb","doi":"10.1145/301177.301215","DOIUrl":"https://doi.org/10.1145/301177.301215","url":null,"abstract":"This paper describes a new design flow that significantly reduces time-to-market for highly complex multiprocessor-based system-on-chip (SOC) designs. This flow, put in place within STMicroelectronics and which is called fast prototyping, allows concurrent hardware and software development, early verification and enables the productive re-use of intellectual property. We describe how using this innovative system design flow, that combines different technologies, such as C modeling, emulation, hard virtual component re-use and CoWare N2C, we achieve better productivity on a multiprocessor SOC design.","PeriodicalId":344739,"journal":{"name":"Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114759756","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The hard real-time schedulability of dependent task-graphs is studied for single bus homogeneous multiprocessor systems. A model which includes interrupts and context switching as well as bus contention is developed. The model captures real-time operating system effects aimed at realistically modeling both intra-processor and inter-processor communications. A robust scheduler is used to assess the impact of interrupt service time (IST) and context switching time (CST) on schedulability. For the class of task-graphs studied, it is shown that schedulability is a nonlinear function of only the weighted sum of IST and CST.
{"title":"Overhead effects in real-time preemptive schedules","authors":"D. Rhodes, W. Wolf","doi":"10.1145/301177.301529","DOIUrl":"https://doi.org/10.1145/301177.301529","url":null,"abstract":"The hard real-time schedulability of dependent task-graphs is studied for single bus homogeneous multiprocessor systems. A model which includes interrupts and context switching as well as bus contention is developed. The model captures real-time operating system effects aimed at realistically modeling both intra-processor and inter-processor communications. A robust scheduler is used to assess the impact of interrupt service time (IST) and context switching time (CST) on schedulability. For the class of task-graphs studied, it is shown that schedulability is a nonlinear function of only the weighted sum of IST and CST.","PeriodicalId":344739,"journal":{"name":"Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450)","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133876548","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper addresses issues in code generation of time critical loops for VLIW ASIPs with heterogenous distributed register structures. We discuss a code generation phasing whereby one first considers binding options that minimize the significant delays that may be incurred on such processors. Given such a binding we consider retiming, subject to code size constraints, so as to enhance performance. Finally a compatible schedule, minimizing latency, is sought. Our main focus in this paper is on the role retiming plays in this complex code generation problem. We propose heuristic algorithms for exploring code size/performance tradeoffs through retiming. Experimental results are presented indicating that the heuristics perform well on a sample of dataflows.
{"title":"Resource constrained dataflow retiming heuristics for VLIW ASIPs","authors":"M. Jacome, G. Veciana, C. Akturan","doi":"10.1109/HSC.1999.777383","DOIUrl":"https://doi.org/10.1109/HSC.1999.777383","url":null,"abstract":"This paper addresses issues in code generation of time critical loops for VLIW ASIPs with heterogenous distributed register structures. We discuss a code generation phasing whereby one first considers binding options that minimize the significant delays that may be incurred on such processors. Given such a binding we consider retiming, subject to code size constraints, so as to enhance performance. Finally a compatible schedule, minimizing latency, is sought. Our main focus in this paper is on the role retiming plays in this complex code generation problem. We propose heuristic algorithms for exploring code size/performance tradeoffs through retiming. Experimental results are presented indicating that the heuristics perform well on a sample of dataflows.","PeriodicalId":344739,"journal":{"name":"Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450)","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125014538","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hardware-software codesign results of concurrent embedded real-time systems are often not easily verifiable. The main difficulty lies in the different time-scales of the embedded hardware, of the embedded software, and of the environment. This rate difference causes state-space explosions and hence coverification has been mostly restricted to the initial system specifications. Currently, most codesign tools or methodologies only support validation in the form of cosimulation and testing. Here, we propose a new formal coverification method based on linear hybrid automata. The basic problems found in most coverification tasks are presented and solved. For complex systems, a simplification strategy is proposed to attack state-space explosions in formal coverification. Experimental results show the feasibility of our approach and the increase in verification scalability through the application of the proposed method.
{"title":"Timing coverification of concurrent embedded real-time systems","authors":"Pao-Ann Hsiung","doi":"10.1109/HSC.1999.777403","DOIUrl":"https://doi.org/10.1109/HSC.1999.777403","url":null,"abstract":"Hardware-software codesign results of concurrent embedded real-time systems are often not easily verifiable. The main difficulty lies in the different time-scales of the embedded hardware, of the embedded software, and of the environment. This rate difference causes state-space explosions and hence coverification has been mostly restricted to the initial system specifications. Currently, most codesign tools or methodologies only support validation in the form of cosimulation and testing. Here, we propose a new formal coverification method based on linear hybrid automata. The basic problems found in most coverification tasks are presented and solved. For complex systems, a simplification strategy is proposed to attack state-space explosions in formal coverification. Experimental results show the feasibility of our approach and the increase in verification scalability through the application of the proposed method.","PeriodicalId":344739,"journal":{"name":"Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130302661","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Task structuring is the process of determining the individual tasks of a system, leading to the system's description as a task graph. This paper shows that RADHA-RATAN, our rate derivation algorithms, can be used to validate various tradeoffs made during task structuring, making this step timing aware. We show how RADHA-RATAN enables construction of a high-level timing model of the system leading to a process timing simulation of the entire system. An interesting aspect of process timing simulation is that it provides the ability to observe system level timing behavior based on timing requirements and analysis before an implementation of the tasks has been carried out. Based on task structuring and process timing simulation we propose a codesign methodology by which a system designer can gain insight into the system's timing performance. This approach enables the designer to reduce expensive timing driven design iterations. We have implemented this methodology in the RADHA-RATAN framework. We illustrate its application by an example.
{"title":"Timing-driven HW/SW codesign based on task structuring and process timing simulation","authors":"Dinesh Ramanathan, Ali Dasdan, Rajesh K. Gupta","doi":"10.1145/301177.301532","DOIUrl":"https://doi.org/10.1145/301177.301532","url":null,"abstract":"Task structuring is the process of determining the individual tasks of a system, leading to the system's description as a task graph. This paper shows that RADHA-RATAN, our rate derivation algorithms, can be used to validate various tradeoffs made during task structuring, making this step timing aware. We show how RADHA-RATAN enables construction of a high-level timing model of the system leading to a process timing simulation of the entire system. An interesting aspect of process timing simulation is that it provides the ability to observe system level timing behavior based on timing requirements and analysis before an implementation of the tasks has been carried out. Based on task structuring and process timing simulation we propose a codesign methodology by which a system designer can gain insight into the system's timing performance. This approach enables the designer to reduce expensive timing driven design iterations. We have implemented this methodology in the RADHA-RATAN framework. We illustrate its application by an example.","PeriodicalId":344739,"journal":{"name":"Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129537237","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we present our approach to automate the development process of co-design tools. We demonstrate with a non-trivial real world example how we can accelerate the tool design process using the software prototyping environment APICES. In a very short time we constructed the tool Dual Dynamics Designer (DDD) which supports a novel methodology in robot software development, DDD allows to edit a complex differential equation-based specification of dynamic robot behavior via an intuitive graphical interface and automatically generates microcontroller code in C as well as a simulation model in Java from it. Speed-up of the tool design process is primarily achieved by a rigorous top-down tool modeling approach in combination with a highly configurable tool frame generator.
{"title":"Co-design tool construction using APICES","authors":"A. Bredenfeld","doi":"10.1109/HSC.1999.777406","DOIUrl":"https://doi.org/10.1109/HSC.1999.777406","url":null,"abstract":"In this paper, we present our approach to automate the development process of co-design tools. We demonstrate with a non-trivial real world example how we can accelerate the tool design process using the software prototyping environment APICES. In a very short time we constructed the tool Dual Dynamics Designer (DDD) which supports a novel methodology in robot software development, DDD allows to edit a complex differential equation-based specification of dynamic robot behavior via an intuitive graphical interface and automatically generates microcontroller code in C as well as a simulation model in Java from it. Speed-up of the tool design process is primarily achieved by a rigorous top-down tool modeling approach in combination with a highly configurable tool frame generator.","PeriodicalId":344739,"journal":{"name":"Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450)","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123100076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. Kenter, C. Passerone, W. Smits, Yosinori Watanabe, A. Sangiovanni-Vincentelli
An advanced Digital Video Broadcasting (DVB) system is used as a design driver for an IF-based real-time design methodology explored in the ESPRIT/OMI COSY project. The design methodology is supported by the Felix VCC environment, provided by a COSY partner Cadence, and tool-set developed for COSY. In this paper, we focus on two key aspects of the design: behavior modeling and code generation. For the behavior modeling, we present the model of computation used to represent the DVB and the technique for expressing this particular model with the more general model of computation supported by the Felix technology. In a companion paper, the architecture selection and communication refinement are described. Once the architecture is selected and a partitioning has been decided, the implementation phase starts. In this phase, for most system designs, a great deal of software has to be written to "customize" the programmable components of the architecture. Obtaining an optimized and correct-by-construction software implementation is fundamental in an effective design methodology. Here we focus on a software generation technique which aims to reduce run-time overhead for functions executed on a single CPU, by generating a minimal number of run-time tasks.
{"title":"Designing digital video systems: Modeling and scheduling","authors":"H. Kenter, C. Passerone, W. Smits, Yosinori Watanabe, A. Sangiovanni-Vincentelli","doi":"10.1145/301177.301212","DOIUrl":"https://doi.org/10.1145/301177.301212","url":null,"abstract":"An advanced Digital Video Broadcasting (DVB) system is used as a design driver for an IF-based real-time design methodology explored in the ESPRIT/OMI COSY project. The design methodology is supported by the Felix VCC environment, provided by a COSY partner Cadence, and tool-set developed for COSY. In this paper, we focus on two key aspects of the design: behavior modeling and code generation. For the behavior modeling, we present the model of computation used to represent the DVB and the technique for expressing this particular model with the more general model of computation supported by the Felix technology. In a companion paper, the architecture selection and communication refinement are described. Once the architecture is selected and a partitioning has been decided, the implementation phase starts. In this phase, for most system designs, a great deal of software has to be written to \"customize\" the programmable components of the architecture. Obtaining an optimized and correct-by-construction software implementation is fundamental in an effective design methodology. Here we focus on a software generation technique which aims to reduce run-time overhead for functions executed on a single CPU, by generating a minimal number of run-time tasks.","PeriodicalId":344739,"journal":{"name":"Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450)","volume":"183 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127031099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recently, a methodology for worst-case analysis of systems with discrete observable signals has been proposed. We extend this methodology to make use of conditional system abstractions that are valid only in some system states. We show that the response-time analysis for single-processor systems is particularly well suited for use of such abstractions. We use an example to demonstrate that significantly better response-time bounds can be obtained using conditional abstractions.
{"title":"Worst-case analysis of discrete systems based on conditional abstractions","authors":"F. Balarin","doi":"10.1145/301177.301502","DOIUrl":"https://doi.org/10.1145/301177.301502","url":null,"abstract":"Recently, a methodology for worst-case analysis of systems with discrete observable signals has been proposed. We extend this methodology to make use of conditional system abstractions that are valid only in some system states. We show that the response-time analysis for single-processor systems is particularly well suited for use of such abstractions. We use an example to demonstrate that significantly better response-time bounds can be obtained using conditional abstractions.","PeriodicalId":344739,"journal":{"name":"Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450)","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121578719","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
At the system level design of a real-time embedded system, a major issue is to identify from alternative architectures the best one which satisfies the timing constraints. This issue leads to the need of a metric that is capable of evaluating the overall system timing performance. Some of the previous work in the related areas focus on predicting the system's timing performance based on a fixed computation time model. These approaches are often too pessimistic. Those that do consider varying computation times for each task are only concerned with the timing behavior of each individual task. Such predictions may not properly capture the timing behavior of the entire system. In this paper, we introduce a metric that reflects the overall timing behavior of RTES. Applying this metric allows a comprehensive comparison of alternative system level designs.
{"title":"A probabilistic performance metric for real-time system design","authors":"Tao Zhou, X. Hu, E. Sha","doi":"10.1145/301177.301494","DOIUrl":"https://doi.org/10.1145/301177.301494","url":null,"abstract":"At the system level design of a real-time embedded system, a major issue is to identify from alternative architectures the best one which satisfies the timing constraints. This issue leads to the need of a metric that is capable of evaluating the overall system timing performance. Some of the previous work in the related areas focus on predicting the system's timing performance based on a fixed computation time model. These approaches are often too pessimistic. Those that do consider varying computation times for each task are only concerned with the timing behavior of each individual task. Such predictions may not properly capture the timing behavior of the entire system. In this paper, we introduce a metric that reflects the overall timing behavior of RTES. Applying this metric allows a comprehensive comparison of alternative system level designs.","PeriodicalId":344739,"journal":{"name":"Proceedings of the Seventh International Workshop on Hardware/Software Codesign (CODES'99) (IEEE Cat. No.99TH8450)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1999-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128164111","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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