Matthias Hiller, Michael Weiner, Leandro Rodrigues Lima, Maximilian Birkner, G. Sigl
Secret key generation with Physical Unclonable Functions (PUFs) is an alternative to conventional secure key storage with non-volatile memory. In a PUF, secret bits are generated by evaluating the internal state of a physical source. Typically, error correction is applied in two stages to remove the instability in the measurement that is caused by environmental influences. We present a new syndrome coding scheme, called Differential Sequence Coding (DSC), for the first error correction stage. DSC applies a fixed reliability criterion and searches the PUF output sequence sequentially until a number of suitable PUF outputs is found. This permits to guarantee the reliability of the indexed PUF outputs. Our analysis demonstrates that DSC is information theoretically secure and highly efficient. To the best of our knowledge, we are the first to propose a convolutional code with Viterbi decoder as second stage error correction for PUFs. We adapt an existing bounding technique for the output bit error probability to our scenario to make reliability statements without the need of laborious simulations. Aiming for a low implementation overhead in hardware, a serialized low complexity FPGA implementation of DSC and the Viterbi decoder is used in this work. For a reference SRAM PUF scenario, PUF size is reduced by 20% and the helper data size decreases by over 40% compared to the best referenced FPGA implementations in each class with a minor increase in the number of slices.
{"title":"Breaking through fixed PUF block limitations with differential sequence coding and convolutional codes","authors":"Matthias Hiller, Michael Weiner, Leandro Rodrigues Lima, Maximilian Birkner, G. Sigl","doi":"10.1145/2517300.2517304","DOIUrl":"https://doi.org/10.1145/2517300.2517304","url":null,"abstract":"Secret key generation with Physical Unclonable Functions (PUFs) is an alternative to conventional secure key storage with non-volatile memory.\u0000 In a PUF, secret bits are generated by evaluating the internal state of a physical source. Typically, error correction is applied in two stages to remove the instability in the measurement that is caused by environmental influences.\u0000 We present a new syndrome coding scheme, called Differential Sequence Coding (DSC), for the first error correction stage. DSC applies a fixed reliability criterion and searches the PUF output sequence sequentially until a number of suitable PUF outputs is found. This permits to guarantee the reliability of the indexed PUF outputs. Our analysis demonstrates that DSC is information theoretically secure and highly efficient.\u0000 To the best of our knowledge, we are the first to propose a convolutional code with Viterbi decoder as second stage error correction for PUFs. We adapt an existing bounding technique for the output bit error probability to our scenario to make reliability statements without the need of laborious simulations.\u0000 Aiming for a low implementation overhead in hardware, a serialized low complexity FPGA implementation of DSC and the Viterbi decoder is used in this work.\u0000 For a reference SRAM PUF scenario, PUF size is reduced by 20% and the helper data size decreases by over 40% compared to the best referenced FPGA implementations in each class with a minor increase in the number of slices.","PeriodicalId":350304,"journal":{"name":"Workshop on Trustworthy Embedded Devices","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131107894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The Welch-Gong (WG) stream cipher family was designed based on the WG transformation and is able to generate keystreams with mathematically proven randomness properties such as long period, balance, ideal tuple distribution, ideal two-level autocorrelation and high and exact linear complexity. In this paper, we present a compact hardware architecture and its pipelined implementation of the stream cipher WG-16, an efficient instance of the WG stream cipher family, using composite field arithmetic and a newly proposed property of the trace function in tower field representation. Instead of using the original binary field F2^16, we demonstrate that its isomorphic tower field F(((2^2)^2)^2)^2 can lead to a more efficient hardware implementation. Efficient conversion matrices connecting the binary field F2^16 and the tower field F(((2^2)^2)^2)^2 are also derived. Our implementation results show that the pipelined WG-16 hardware core can achieve the throughput of 124 MHz at the cost of 478 slices in an FPGA and 552 MHz at the cost of 12,031 GEs in a 65 nm ASIC, respectively.
{"title":"Efficient hardware implementation of the stream cipher WG-16 with composite field arithmetic","authors":"Xinxin Fan, N. Zidarič, M. Aagaard, G. Gong","doi":"10.1145/2517300.2517305","DOIUrl":"https://doi.org/10.1145/2517300.2517305","url":null,"abstract":"The Welch-Gong (WG) stream cipher family was designed based on the WG transformation and is able to generate keystreams with mathematically proven randomness properties such as long period, balance, ideal tuple distribution, ideal two-level autocorrelation and high and exact linear complexity. In this paper, we present a compact hardware architecture and its pipelined implementation of the stream cipher WG-16, an efficient instance of the WG stream cipher family, using composite field arithmetic and a newly proposed property of the trace function in tower field representation. Instead of using the original binary field F2^16, we demonstrate that its isomorphic tower field F(((2^2)^2)^2)^2 can lead to a more efficient hardware implementation. Efficient conversion matrices connecting the binary field F2^16 and the tower field F(((2^2)^2)^2)^2 are also derived. Our implementation results show that the pipelined WG-16 hardware core can achieve the throughput of 124 MHz at the cost of 478 slices in an FPGA and 552 MHz at the cost of 12,031 GEs in a 65 nm ASIC, respectively.","PeriodicalId":350304,"journal":{"name":"Workshop on Trustworthy Embedded Devices","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127948272","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Physically Unclonable Functions (PUF) are continuously being integrated into next generation security products. Nevertheless, their implementations and algorithms are the subject of much debate amongst the security community. One proposed use application for PUFs is replacing secure key storage. Yet the full unique PUF response of the most common type of PUFs can be recovered by using standard failure analysis equipment. SRAM PUFs used as key storage can only be considered to marginally improve security over conventional non-volatile key storage.
{"title":"Feasibly clonable functions","authors":"C. Boit, Clemens Helfmeier, Dmitry Nedospasov","doi":"10.1145/2517300.2528523","DOIUrl":"https://doi.org/10.1145/2517300.2528523","url":null,"abstract":"Physically Unclonable Functions (PUF) are continuously being integrated into next generation security products. Nevertheless, their implementations and algorithms are the subject of much debate amongst the security community. One proposed use application for PUFs is replacing secure key storage. Yet the full unique PUF response of the most common type of PUFs can be recovered by using standard failure analysis equipment. SRAM PUFs used as key storage can only be considered to marginally improve security over conventional non-volatile key storage.","PeriodicalId":350304,"journal":{"name":"Workshop on Trustworthy Embedded Devices","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126057325","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The concept of the Physical Unclonable Function (PUF) is exhaustively characerised as an information storage device with a security mechanism that shall impede the duplication of its specified functionality and that is indivisible from its storage mechanism. Thereby, in analogy to cryptography (security mechanisms indivisible from the writing), PUF research and development is identified as the new security-engineering discipline of "cryptostorage". Previous PUF architectures are shown to conform to this framework. A preliminary classification scheme to organize future research and security evaluation of PUF-like primitives is developed.
{"title":"Physical unclonable functions: devices for cryptostorage","authors":"D. Merli, R. Plaga","doi":"10.1145/2517300.2528524","DOIUrl":"https://doi.org/10.1145/2517300.2528524","url":null,"abstract":"The concept of the Physical Unclonable Function (PUF) is exhaustively characerised as an information storage device with a security mechanism that shall impede the duplication of its specified functionality and that is indivisible from its storage mechanism. Thereby, in analogy to cryptography (security mechanisms indivisible from the writing), PUF research and development is identified as the new security-engineering discipline of \"cryptostorage\". Previous PUF architectures are shown to conform to this framework. A preliminary classification scheme to organize future research and security evaluation of PUF-like primitives is developed.","PeriodicalId":350304,"journal":{"name":"Workshop on Trustworthy Embedded Devices","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128475261","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Robbert van den Berg, B. Škorić, Vincent van der Leest
Physical Unclonable Functions (PUFs) are increasingly becoming a well-known security primitive for secure key storage and anti-counterfeiting. For both applications it is imperative that PUFs provide enough entropy. The aim of this paper is to propose a new model for binary-output PUFs such as SRAM, DFF, Latch and Buskeeper PUFs, and a method to accurately estimate their entropy. In our model the measurable property of a PUF is its set of cell biases. We determine an upper bound on the "extractable entropy", i.e. the number of key bits that can be robustly extracted, by calculating the mutual information between the bias measurements done at enrollment and reconstruction. In previously known methods only uniqueness was studied using information-theoretic measures, while robustness was typically expressed in terms of error probabilities or distances. It is not always straightforward to use a combination of these two metrics in order to make an informed decision about the performance of different PUF types. Our new approach has the advantage that it simultaneously captures both of properties that are vital for key storage: uniqueness and robustness. Therefore it will be possible to fairly compare performance of PUF implementations using our new method. Statistical validation of the new methodology shows that it clearly captures both of these properties of PUFs. In other words: if one of these aspects (either uniqueness or robustness) is less than optimal, the extractable entropy decreases. Analysis on a large database of PUF measurement data shows very high entropy for SRAM PUFs, but rather poor results for all other memory-based PUFs in this database.
{"title":"Bias-based modeling and entropy analysis of PUFs","authors":"Robbert van den Berg, B. Škorić, Vincent van der Leest","doi":"10.1145/2517300.2517301","DOIUrl":"https://doi.org/10.1145/2517300.2517301","url":null,"abstract":"Physical Unclonable Functions (PUFs) are increasingly becoming a well-known security primitive for secure key storage and anti-counterfeiting. For both applications it is imperative that PUFs provide enough entropy. The aim of this paper is to propose a new model for binary-output PUFs such as SRAM, DFF, Latch and Buskeeper PUFs, and a method to accurately estimate their entropy. In our model the measurable property of a PUF is its set of cell biases. We determine an upper bound on the \"extractable entropy\", i.e. the number of key bits that can be robustly extracted, by calculating the mutual information between the bias measurements done at enrollment and reconstruction.\u0000 In previously known methods only uniqueness was studied using information-theoretic measures, while robustness was typically expressed in terms of error probabilities or distances. It is not always straightforward to use a combination of these two metrics in order to make an informed decision about the performance of different PUF types. Our new approach has the advantage that it simultaneously captures both of properties that are vital for key storage: uniqueness and robustness. Therefore it will be possible to fairly compare performance of PUF implementations using our new method. Statistical validation of the new methodology shows that it clearly captures both of these properties of PUFs. In other words: if one of these aspects (either uniqueness or robustness) is less than optimal, the extractable entropy decreases. Analysis on a large database of PUF measurement data shows very high entropy for SRAM PUFs, but rather poor results for all other memory-based PUFs in this database.","PeriodicalId":350304,"journal":{"name":"Workshop on Trustworthy Embedded Devices","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129012161","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. V. Herrewege, Vincent van der Leest, André Schaller, S. Katzenbeisser, I. Verbauwhede
The generation of high quality random numbers is crucial to many cryptographic applications, including cryptographic protocols, secret of keys, nonces or salts. Their values must contain enough randomness to be unpredictable to attackers. Pseudo-random number generators require initial data with high entropy as a seed to produce a large stream of high quality random data. Yet, despite the importance of randomness, proper high quality random number generation is often ignored. Primarily embedded devices often suffer from weak random number generators. In this work, we focus on identifying and evaluating SRAM in commercial off-the-shelf microcontrollers as an entropy source for PRNG seeding. We measure and evaluate the SRAM start-up patterns of two popular types of microcontrollers, a STMicroelectronics STM32F100R8 and a Microchip PIC16F1825. We also present an efficient software-only architecture for secure PRNG seeding. After analyzing over 1000000 measurements in total, we conclude that of these two devices, the PIC16F1825 cannot be used to securely seed a PRNG. The STM32F100R8, however, has the ability to generate very strong seeds from the noise in its SRAM start-up pattern. These seeds can then be used to ensure a PRNG generates high quality data.
{"title":"Secure PRNG seeding on commercial off-the-shelf microcontrollers","authors":"A. V. Herrewege, Vincent van der Leest, André Schaller, S. Katzenbeisser, I. Verbauwhede","doi":"10.1145/2517300.2517306","DOIUrl":"https://doi.org/10.1145/2517300.2517306","url":null,"abstract":"The generation of high quality random numbers is crucial to many cryptographic applications, including cryptographic protocols, secret of keys, nonces or salts. Their values must contain enough randomness to be unpredictable to attackers. Pseudo-random number generators require initial data with high entropy as a seed to produce a large stream of high quality random data. Yet, despite the importance of randomness, proper high quality random number generation is often ignored. Primarily embedded devices often suffer from weak random number generators.\u0000 In this work, we focus on identifying and evaluating SRAM in commercial off-the-shelf microcontrollers as an entropy source for PRNG seeding. We measure and evaluate the SRAM start-up patterns of two popular types of microcontrollers, a STMicroelectronics STM32F100R8 and a Microchip PIC16F1825. We also present an efficient software-only architecture for secure PRNG seeding. After analyzing over 1000000 measurements in total, we conclude that of these two devices, the PIC16F1825 cannot be used to securely seed a PRNG. The STM32F100R8, however, has the ability to generate very strong seeds from the noise in its SRAM start-up pattern. These seeds can then be used to ensure a PRNG generates high quality data.","PeriodicalId":350304,"journal":{"name":"Workshop on Trustworthy Embedded Devices","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129148488","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Ellouze, M. Allouche, H. B. Ahmed, S. Rekhis, N. Boudriga
Implantable Medical Devices (IMDs) are surgically implanted into a human body to collect physiological data and perform medical therapeutic functions. They are increasingly being used to improve the quality of life of patients by treating chronic ailments such as cardiac arrhythmia, diabetes, and Parkinson's disease. Wireless IMDs have shown recently important security concerns. In particular, it has been stated that lethal attacks can be launched on these devices. In this paper, we propose a solution to secure IMDs against unauthorized access, battery depletion, and denial of service attacks. A Radio Frequency energy harvesting solution is used to design a powerless mutual authentication protocol. A technique for dynamic biometric keys extraction from electrocardiogram signals collected at both sides (the programmer and the IMD) is used, allowing to secure access to the IMD devices in regular and emergency situations.
{"title":"Securing implantable cardiac medical devices: use of radio frequency energy harvesting","authors":"N. Ellouze, M. Allouche, H. B. Ahmed, S. Rekhis, N. Boudriga","doi":"10.1145/2517300.2517307","DOIUrl":"https://doi.org/10.1145/2517300.2517307","url":null,"abstract":"Implantable Medical Devices (IMDs) are surgically implanted into a human body to collect physiological data and perform medical therapeutic functions. They are increasingly being used to improve the quality of life of patients by treating chronic ailments such as cardiac arrhythmia, diabetes, and Parkinson's disease. Wireless IMDs have shown recently important security concerns. In particular, it has been stated that lethal attacks can be launched on these devices. In this paper, we propose a solution to secure IMDs against unauthorized access, battery depletion, and denial of service attacks. A Radio Frequency energy harvesting solution is used to design a powerless mutual authentication protocol. A technique for dynamic biometric keys extraction from electrocardiogram signals collected at both sides (the programmer and the IMD) is used, allowing to secure access to the IMD devices in regular and emergency situations.","PeriodicalId":350304,"journal":{"name":"Workshop on Trustworthy Embedded Devices","volume":"267 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133091907","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hypervisors are low level execution platforms that provide isolated partitions on shared resources, allowing to design secure systems without using dedicated hardware devices. A key requirement of this kind of solution is the formal verification of the software trusted computing base, preferably at the binary level. We accomplish a detailed verification of an ARMv7 tiny hypervisor, proving its correctness at the machine code level. We present our verification strategy, which mixes the usage of the theorem prover HOL4, the computation of weakest preconditions, and the use of SMT solvers to largely automate the verification process. The automation relies on an integration of HOL4 with BAP, the Binary Analysis Platform developed at CMU. To enable the adoption of the BAP back-ends to compute weakest preconditions and control flow graphs, a HOL4-based tool was implemented that transforms ARMv7 assembly programs to the BAP Intermediate Language. Since verifying contracts by computing the weakest precondition depends on resolving indirect jumps, we implemented a procedure that integrates SMT solvers and BAP to discover all the possible assignments to the indirect jumps under the contract precondition.
{"title":"Machine code verification of a tiny ARM hypervisor","authors":"M. Dam, R. Guanciale, Hamed Nemati","doi":"10.1145/2517300.2517302","DOIUrl":"https://doi.org/10.1145/2517300.2517302","url":null,"abstract":"Hypervisors are low level execution platforms that provide isolated partitions on shared resources, allowing to design secure systems without using dedicated hardware devices. A key requirement of this kind of solution is the formal verification of the software trusted computing base, preferably at the binary level. We accomplish a detailed verification of an ARMv7 tiny hypervisor, proving its correctness at the machine code level. We present our verification strategy, which mixes the usage of the theorem prover HOL4, the computation of weakest preconditions, and the use of SMT solvers to largely automate the verification process. The automation relies on an integration of HOL4 with BAP, the Binary Analysis Platform developed at CMU. To enable the adoption of the BAP back-ends to compute weakest preconditions and control flow graphs, a HOL4-based tool was implemented that transforms ARMv7 assembly programs to the BAP Intermediate Language. Since verifying contracts by computing the weakest precondition depends on resolving indirect jumps, we implemented a procedure that integrates SMT solvers and BAP to discover all the possible assignments to the indirect jumps under the contract precondition.","PeriodicalId":350304,"journal":{"name":"Workshop on Trustworthy Embedded Devices","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-11-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131511727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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