Pub Date : 2011-10-09DOI: 10.1109/ICCD.2011.6081396
M. A. Haque, Hakan Aydin, Dakai Zhu
In this paper, we present an energy-aware standby-sparing technique for periodic real-time applications. A standby-sparing system consists of a primary processor where the application tasks are executed using Dynamic Voltage Scaling (DVS) to save energy, and a spare processor where the backup tasks are executed at maximum voltage/frequency, should there be a need. In our framework, we employ Earliest-Deadline-First (EDF) and Earliest-Deadline-Late (EDL) scheduling policies on the primary and spare CPUs, respectively. The use of EDL on the spare CPU allows delaying the backup tasks on the spare CPU as much as possible, enabling energy savings. We develop static and dynamic algorithms based on these principles, and evaluate their performance experimentally. Our simulation results show significant energy savings compared to existing reliability-aware power management (RAPM) techniques for most execution scenarios.
{"title":"Energy-aware Standby-Sparing Technique for periodic real-time applications","authors":"M. A. Haque, Hakan Aydin, Dakai Zhu","doi":"10.1109/ICCD.2011.6081396","DOIUrl":"https://doi.org/10.1109/ICCD.2011.6081396","url":null,"abstract":"In this paper, we present an energy-aware standby-sparing technique for periodic real-time applications. A standby-sparing system consists of a primary processor where the application tasks are executed using Dynamic Voltage Scaling (DVS) to save energy, and a spare processor where the backup tasks are executed at maximum voltage/frequency, should there be a need. In our framework, we employ Earliest-Deadline-First (EDF) and Earliest-Deadline-Late (EDL) scheduling policies on the primary and spare CPUs, respectively. The use of EDL on the spare CPU allows delaying the backup tasks on the spare CPU as much as possible, enabling energy savings. We develop static and dynamic algorithms based on these principles, and evaluate their performance experimentally. Our simulation results show significant energy savings compared to existing reliability-aware power management (RAPM) techniques for most execution scenarios.","PeriodicalId":354015,"journal":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123884063","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-09DOI: 10.1109/ICCD.2011.6081442
Fahimeh Jafari, A. Jantsch, Zhonghai Lu
In NoCs often several flows are merged into one aggregate flow due to heavy resource sharing. For strengthening formal performance analysis, we propose an improved model for an output flow of a FIFO multiplexer under aggregate scheduling. The model of the aggregate flow is formally proven and can serve as the basis for a stringent worst case delay and buffer analysis.
{"title":"Output process of variable bit-rate flows in on-chip networks based on aggregate scheduling","authors":"Fahimeh Jafari, A. Jantsch, Zhonghai Lu","doi":"10.1109/ICCD.2011.6081442","DOIUrl":"https://doi.org/10.1109/ICCD.2011.6081442","url":null,"abstract":"In NoCs often several flows are merged into one aggregate flow due to heavy resource sharing. For strengthening formal performance analysis, we propose an improved model for an output flow of a FIFO multiplexer under aggregate scheduling. The model of the aggregate flow is formally proven and can serve as the basis for a stringent worst case delay and buffer analysis.","PeriodicalId":354015,"journal":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126386632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-09DOI: 10.1109/ICCD.2011.6081404
Deepak Gangadharan, Haiyang Ma, S. Chakraborty, Roger Zimmermann
We study the impact of a novel prioritized frame dropping scheme in buffer-constrained multiprocessor system-on-chip (MPSoC) platforms. Accurate buffer dimensioning has attracted lot of research interest as large on-chip buffers result in increased silicon area and higher costs. Multimedia applications present the flexibility of trading off quality for buffer space without any noticeable deterioration in video quality. The frame dropping scheme is crucial here to drop frames appropriately such that the required buffer size is reduced and target quality requirement is satisfied. Towards this, we propose a simple prioritized frame dropping mechanism which reduces the required buffer space more than existing frame dropping policies. We also provide a fast iterative procedure to find the minimum buffer size for a video clip with O(log(Ndrop)) number of iterations, where Ndrop is the maximum number of frames that can be dropped for a video clip so that a prespecified quality in terms of peak signal to noise ratio (PSNR) value is satisfied.
{"title":"Video quality-driven buffer dimensioning in MPSoC platforms via prioritized frame drops","authors":"Deepak Gangadharan, Haiyang Ma, S. Chakraborty, Roger Zimmermann","doi":"10.1109/ICCD.2011.6081404","DOIUrl":"https://doi.org/10.1109/ICCD.2011.6081404","url":null,"abstract":"We study the impact of a novel prioritized frame dropping scheme in buffer-constrained multiprocessor system-on-chip (MPSoC) platforms. Accurate buffer dimensioning has attracted lot of research interest as large on-chip buffers result in increased silicon area and higher costs. Multimedia applications present the flexibility of trading off quality for buffer space without any noticeable deterioration in video quality. The frame dropping scheme is crucial here to drop frames appropriately such that the required buffer size is reduced and target quality requirement is satisfied. Towards this, we propose a simple prioritized frame dropping mechanism which reduces the required buffer space more than existing frame dropping policies. We also provide a fast iterative procedure to find the minimum buffer size for a video clip with O(log(Ndrop)) number of iterations, where Ndrop is the maximum number of frames that can be dropped for a video clip so that a prespecified quality in terms of peak signal to noise ratio (PSNR) value is satisfied.","PeriodicalId":354015,"journal":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","volume":"17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126815201","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-09DOI: 10.1109/ICCD.2011.6081437
S. Chaudhuri, N. Jha
Among various multi-gate structures, FinFETs have emerged dominant owing to their ease of fabrication. Thus, characterization of FinFET devices/gates needs immediate attention for them to become the industry driver in this decade. Ideally, 3D device simulation should be done to enable accurate circuit synthesis. However, this is impractical due to the huge CPU times required. Simulating a 2D cross-section of the device yields 100–1000× reduction in CPU time. However, this introduces significant error, in the range of 10% to 50%, while evaluating the on/off current (ION/IOFF) for a single device and leakage current or propagation delay (ILEAK/tD) for logic gates. In this work, we develop accurate 2D models of FinFET devices to capture 3D simulation accuracy with 2D simulation efficiency. We report results for the 22nm FinFET technology node. As far as we know, this is the first such attempt. We establish the validity of the model even under process variations. We target variations in gate length (LG), workfunction (ΦG) and fin thickness (TSI) that are known to have the most impact on leakage and delay. We adjust their values in the 2D model in order to mimic the actual 3D device behavior. When the 2D models are employed in mixed-mode simulation of FinFET logic gates, the error in the evaluation of ILEAK/tD is quite small.
{"title":"3D vs. 2D analysis of FinFET logic gates under process variations","authors":"S. Chaudhuri, N. Jha","doi":"10.1109/ICCD.2011.6081437","DOIUrl":"https://doi.org/10.1109/ICCD.2011.6081437","url":null,"abstract":"Among various multi-gate structures, FinFETs have emerged dominant owing to their ease of fabrication. Thus, characterization of FinFET devices/gates needs immediate attention for them to become the industry driver in this decade. Ideally, 3D device simulation should be done to enable accurate circuit synthesis. However, this is impractical due to the huge CPU times required. Simulating a 2D cross-section of the device yields 100–1000× reduction in CPU time. However, this introduces significant error, in the range of 10% to 50%, while evaluating the on/off current (ION/IOFF) for a single device and leakage current or propagation delay (ILEAK/tD) for logic gates. In this work, we develop accurate 2D models of FinFET devices to capture 3D simulation accuracy with 2D simulation efficiency. We report results for the 22nm FinFET technology node. As far as we know, this is the first such attempt. We establish the validity of the model even under process variations. We target variations in gate length (LG), workfunction (ΦG) and fin thickness (TSI) that are known to have the most impact on leakage and delay. We adjust their values in the 2D model in order to mimic the actual 3D device behavior. When the 2D models are employed in mixed-mode simulation of FinFET logic gates, the error in the evaluation of ILEAK/tD is quite small.","PeriodicalId":354015,"journal":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","volume":"298 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134265279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-09DOI: 10.1109/ICCD.2011.6081384
Stefan Hoelldampf, D. Zaum, M. Olbrich, E. Barke
Analysis of mixed-signal circuits on system level demands for an accelerated simulation of analog blocks. We precompute state space representations that can be used to evaluate the circuit response and predict the occurrence of events triggered by analog components. Interfacing such models to SystemC digital simulation allows for very fast mixed-signal transient analysis. The key contribution of this paper is the dynamic generation of SystemC events from analog descriptions. We evaluate the performance of our approach using PWM (pulse width modulation) example circuits from the automotive domain which are interfaced to a SystemC microcontroller model. Accuracy and speed is compared to reference simulations utilizing traditional SPICE-like analog simulators. Our approach allows for a speedup of up to 70 for mixed-signal simulations compared to traditional analog and digital simulators.
{"title":"Using analog circuit behavior to generate SystemC events for an acceleration of mixed-signal simulation","authors":"Stefan Hoelldampf, D. Zaum, M. Olbrich, E. Barke","doi":"10.1109/ICCD.2011.6081384","DOIUrl":"https://doi.org/10.1109/ICCD.2011.6081384","url":null,"abstract":"Analysis of mixed-signal circuits on system level demands for an accelerated simulation of analog blocks. We precompute state space representations that can be used to evaluate the circuit response and predict the occurrence of events triggered by analog components. Interfacing such models to SystemC digital simulation allows for very fast mixed-signal transient analysis. The key contribution of this paper is the dynamic generation of SystemC events from analog descriptions. We evaluate the performance of our approach using PWM (pulse width modulation) example circuits from the automotive domain which are interfaced to a SystemC microcontroller model. Accuracy and speed is compared to reference simulations utilizing traditional SPICE-like analog simulators. Our approach allows for a speedup of up to 70 for mixed-signal simulations compared to traditional analog and digital simulators.","PeriodicalId":354015,"journal":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","volume":"39 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115568455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-09DOI: 10.1109/ICCD.2011.6081371
Minjeong Shin, John Kim
On-chip networks are becoming more important as the number of on-chip components continue to increase. 2D mesh topology is a commonly assumed topology for on-chip networks but in this work, we make the argument that 2D torus can provide a more cost-efficient on-chip network since the on-chip network datapath is reduced by 2× while providing the same bisection bandwidth as a mesh network. Our results show that 2D torus can achieve an improvement of up to 1.9× over a 2D mesh in performance per watt metric. However, routing deadlock can occur in a torus network with the wrap-around channel and requires additional virtual channels for deadlock avoidance. In this work, we propose deadlock recovery with tokens (DRT) in on-chip networks that exploits on-chip networks - exploiting the abundant wires available while minimizing the need for additional buffers. As a result, deadlocks can be exactly detected without having to rely on a timeout mechanism and when needed, recover from the deadlock. We show how DRT results in minimal loss in performance, compared with deadlock avoidance using virtual channels, while reducing the on-chip network complexity.
{"title":"Leveraging torus topology with deadlock recovery for cost-efficient on-chip network","authors":"Minjeong Shin, John Kim","doi":"10.1109/ICCD.2011.6081371","DOIUrl":"https://doi.org/10.1109/ICCD.2011.6081371","url":null,"abstract":"On-chip networks are becoming more important as the number of on-chip components continue to increase. 2D mesh topology is a commonly assumed topology for on-chip networks but in this work, we make the argument that 2D torus can provide a more cost-efficient on-chip network since the on-chip network datapath is reduced by 2× while providing the same bisection bandwidth as a mesh network. Our results show that 2D torus can achieve an improvement of up to 1.9× over a 2D mesh in performance per watt metric. However, routing deadlock can occur in a torus network with the wrap-around channel and requires additional virtual channels for deadlock avoidance. In this work, we propose deadlock recovery with tokens (DRT) in on-chip networks that exploits on-chip networks - exploiting the abundant wires available while minimizing the need for additional buffers. As a result, deadlocks can be exactly detected without having to rely on a timeout mechanism and when needed, recover from the deadlock. We show how DRT results in minimal loss in performance, compared with deadlock avoidance using virtual channels, while reducing the on-chip network complexity.","PeriodicalId":354015,"journal":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","volume":"238 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116176321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-09DOI: 10.1109/ICCD.2011.6081445
P. Lin, A. Ivanov, Bradley Johnson, S. Khatri
Recently, a secure key exchange technique was developed, in which both communicators (Alice and Bob) randomly select between two known resistors. By measuring the resulting thermal noise on a shared wire, they can each determine the resistor chosen by their counterpart, while the eavesdropper (Eve) cannot determine this. By repeating this transaction, they can create a common secure key, one bit a time. Although theoretically elegant, this approach is difficult to realize in practice. In this paper, we present a practical realization of a secure key exchange technique, intended for use over the Ethernet. Our approach is inspired by the above scheme with significant differences. In our approach, Alice and Bob utilize programmable resistors and exchange their resistance values securely. Our technique has been implemented in a hardware FPGA based platform, and was found to be able to exchange 4 secure bits per transaction over a 100ft CAT5 cable.
{"title":"A novel cryptographic key exchange scheme using resistors","authors":"P. Lin, A. Ivanov, Bradley Johnson, S. Khatri","doi":"10.1109/ICCD.2011.6081445","DOIUrl":"https://doi.org/10.1109/ICCD.2011.6081445","url":null,"abstract":"Recently, a secure key exchange technique was developed, in which both communicators (Alice and Bob) randomly select between two known resistors. By measuring the resulting thermal noise on a shared wire, they can each determine the resistor chosen by their counterpart, while the eavesdropper (Eve) cannot determine this. By repeating this transaction, they can create a common secure key, one bit a time. Although theoretically elegant, this approach is difficult to realize in practice. In this paper, we present a practical realization of a secure key exchange technique, intended for use over the Ethernet. Our approach is inspired by the above scheme with significant differences. In our approach, Alice and Bob utilize programmable resistors and exchange their resistance values securely. Our technique has been implemented in a hardware FPGA based platform, and was found to be able to exchange 4 secure bits per transaction over a 100ft CAT5 cable.","PeriodicalId":354015,"journal":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123392617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-09DOI: 10.1109/ICCD.2011.6081391
Peng Li, D. Lilja
As device scaling continues to nanoscale dimensions, circuit reliability will continue to become an ever greater problem. Stochastic computing, which performs computing with random bits (stochastic bits streams), can be used to enable reliable computation using those unreliable devices. However, one of the major issues of stochastic computing is that applications implemented with this technique are limited by the available computational elements. In this paper, first we will introduce and prove a stochastic absolute value function. Second, we will demonstrate a mathematical analysis of a stochastic tanh function, which is a key component used in a stochastic comparator. Third, we will present a quantitative analysis of a one-parameter linear gain function, and propose a new two-parameter version. The validity of the present stochastic computational elements is demonstrated through four basic digital image processing algorithms: edge detection, frame difference based image segmentation, median filter based noise reduction, and image contrast stretching. Our experimental results show that stochastic implementations tolerate more noise and consume less hardware than their conventional counterparts.
{"title":"Using stochastic computing to implement digital image processing algorithms","authors":"Peng Li, D. Lilja","doi":"10.1109/ICCD.2011.6081391","DOIUrl":"https://doi.org/10.1109/ICCD.2011.6081391","url":null,"abstract":"As device scaling continues to nanoscale dimensions, circuit reliability will continue to become an ever greater problem. Stochastic computing, which performs computing with random bits (stochastic bits streams), can be used to enable reliable computation using those unreliable devices. However, one of the major issues of stochastic computing is that applications implemented with this technique are limited by the available computational elements. In this paper, first we will introduce and prove a stochastic absolute value function. Second, we will demonstrate a mathematical analysis of a stochastic tanh function, which is a key component used in a stochastic comparator. Third, we will present a quantitative analysis of a one-parameter linear gain function, and propose a new two-parameter version. The validity of the present stochastic computational elements is demonstrated through four basic digital image processing algorithms: edge detection, frame difference based image segmentation, median filter based noise reduction, and image contrast stretching. Our experimental results show that stochastic implementations tolerate more noise and consume less hardware than their conventional counterparts.","PeriodicalId":354015,"journal":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114754071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-09DOI: 10.1109/ICCD.2011.6081418
Sheng Lin, Yong-Bin Kim, F. Lombardi
The occurrence of a multiple node upset is likely to increase significantly in nanoscale CMOS due to reduced device size and power supply voltage scaling. This paper presents a comprehensive treatment (model, analysis and design) for hardening a memory cell against a soft error resulting in a multiple node upset at 32nm feature size in CMOS. A novel 13T memory cell configuration is proposed, analyzed, and simulated to show a better tolerance to the likely multiple node upset, i.e. a transient or soft fault affecting any two nodes in a cell. The proposed hardened memory cell utilizes a Schmitt trigger design; simulation shows that the multiple node upset tolerance is improved by nearly twice as much over existing designs. Moreover the 13T cell achieves a 33% reduction in write delay and only a 5% increase in power consumption compared to the DICE cell (consisting of 12 transistors). Simulation results are provided using the predictive technology file for 32nm feature size in CMOS. Monte Carlo simulation confirms the excellent multiple node upset tolerance of the proposed memory cell in the presence of process, voltage, and temperature variations in their designs.
{"title":"Modeling and design of a nanoscale memory cell for hardening to a single event with multiple node upset","authors":"Sheng Lin, Yong-Bin Kim, F. Lombardi","doi":"10.1109/ICCD.2011.6081418","DOIUrl":"https://doi.org/10.1109/ICCD.2011.6081418","url":null,"abstract":"The occurrence of a multiple node upset is likely to increase significantly in nanoscale CMOS due to reduced device size and power supply voltage scaling. This paper presents a comprehensive treatment (model, analysis and design) for hardening a memory cell against a soft error resulting in a multiple node upset at 32nm feature size in CMOS. A novel 13T memory cell configuration is proposed, analyzed, and simulated to show a better tolerance to the likely multiple node upset, i.e. a transient or soft fault affecting any two nodes in a cell. The proposed hardened memory cell utilizes a Schmitt trigger design; simulation shows that the multiple node upset tolerance is improved by nearly twice as much over existing designs. Moreover the 13T cell achieves a 33% reduction in write delay and only a 5% increase in power consumption compared to the DICE cell (consisting of 12 transistors). Simulation results are provided using the predictive technology file for 32nm feature size in CMOS. Monte Carlo simulation confirms the excellent multiple node upset tolerance of the proposed memory cell in the presence of process, voltage, and temperature variations in their designs.","PeriodicalId":354015,"journal":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114425806","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2011-10-09DOI: 10.1109/ICCD.2011.6081433
Yong Zou, Yi Xiang, S. Pasricha
In Networks-on-Chip (NoC), with ever-increasing complexity and technology scaling, transient single-event upsets (SEUs) have become a key design challenge. In this work, we extend the concept of architectural vulnerability factor (AVF) from the microprocessor domain and propose a network vulnerability factor (NVF) to characterize the susceptibility of NoC components such as the Network Interface (NI) to transient faults. Our studies reveal that different NI buffers behave quite differently on transient faults and each buffer can have different levels of inherent fault-tolerant capability. Our analysis also considers the impact of thermal hotspot mitigation techniques such as frequency throttling on the NVF estimation.
{"title":"Analysis of on-chip interconnection network interface reliability in multicore systems","authors":"Yong Zou, Yi Xiang, S. Pasricha","doi":"10.1109/ICCD.2011.6081433","DOIUrl":"https://doi.org/10.1109/ICCD.2011.6081433","url":null,"abstract":"In Networks-on-Chip (NoC), with ever-increasing complexity and technology scaling, transient single-event upsets (SEUs) have become a key design challenge. In this work, we extend the concept of architectural vulnerability factor (AVF) from the microprocessor domain and propose a network vulnerability factor (NVF) to characterize the susceptibility of NoC components such as the Network Interface (NI) to transient faults. Our studies reveal that different NI buffers behave quite differently on transient faults and each buffer can have different levels of inherent fault-tolerant capability. Our analysis also considers the impact of thermal hotspot mitigation techniques such as frequency throttling on the NVF estimation.","PeriodicalId":354015,"journal":{"name":"2011 IEEE 29th International Conference on Computer Design (ICCD)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2011-10-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124158953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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