Pub Date : 2005-08-01DOI: 10.1109/HOTCHIPS.2005.7476571
S. Nassif
This article consists of a collection of slides from the author's conference presentation. It is concluded that: Power grid noise and its variability depends on both: Technology factors and Design specifics. Recent design trends result in a need to: (a) Perform early power delivery design; (b) Packaging technology and package selection;(c) Density and Distribution of routing resources; and (d)Decoupling capacitance allocation.
{"title":"Impact of variability on power","authors":"S. Nassif","doi":"10.1109/HOTCHIPS.2005.7476571","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2005.7476571","url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation. It is concluded that: Power grid noise and its variability depends on both: Technology factors and Design specifics. Recent design trends result in a need to: (a) Perform early power delivery design; (b) Packaging technology and package selection;(c) Density and Distribution of routing resources; and (d)Decoupling capacitance allocation.","PeriodicalId":357616,"journal":{"name":"2005 IEEE Hot Chips XVII Symposium (HCS)","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126083113","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-08-01DOI: 10.1109/HOTCHIPS.2005.7476567
J. E. Smith, Rich Uhlig
This article consists of a collection of slides from the author's conference presentation. Virtual machines have emerged as a powerful tool for computer systems designers. They can be used to enhance software interoperability, mobility, and security, as well as providing means for effective hardware resource management. We survey the spectrum of VM architectures and their applications. These range from the HLL VMs as exemplified by Java, to process VMs that permit cross-platform execution of conventional binaries, to system VMs which support multiple OS environments on a single platform. We then look at some of the important VM architectures and discuss their implementations and features. We will emphasize architecture and hardware mechanisms that provide efficient support for VMs. Several case studies will be discussed, chosen from both commercial implementations and research project.
{"title":"HOTCHIPS 17: Tutorial 1, part 1","authors":"J. E. Smith, Rich Uhlig","doi":"10.1109/HOTCHIPS.2005.7476567","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2005.7476567","url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation. Virtual machines have emerged as a powerful tool for computer systems designers. They can be used to enhance software interoperability, mobility, and security, as well as providing means for effective hardware resource management. We survey the spectrum of VM architectures and their applications. These range from the HLL VMs as exemplified by Java, to process VMs that permit cross-platform execution of conventional binaries, to system VMs which support multiple OS environments on a single platform. We then look at some of the important VM architectures and discuss their implementations and features. We will emphasize architecture and hardware mechanisms that provide efficient support for VMs. Several case studies will be discussed, chosen from both commercial implementations and research project.","PeriodicalId":357616,"journal":{"name":"2005 IEEE Hot Chips XVII Symposium (HCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115821378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-08-01DOI: 10.1109/HOTCHIPS.2005.7476576
M. Gschwind, P. Hofstee, B. Flachs, Martin E. Hopkins, Yukio Watanabe, T. Yamazaki
{"title":"A novel SIMD architecture for the cell heterogeneous chip-multiprocessor","authors":"M. Gschwind, P. Hofstee, B. Flachs, Martin E. Hopkins, Yukio Watanabe, T. Yamazaki","doi":"10.1109/HOTCHIPS.2005.7476576","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2005.7476576","url":null,"abstract":"","PeriodicalId":357616,"journal":{"name":"2005 IEEE Hot Chips XVII Symposium (HCS)","volume":"2003 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134475147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-08-01DOI: 10.1109/HOTCHIPS.2005.7476595
R. E. Gonzalez
This article consists of a collection of slides from the author's conference presentation on change system design for software configurable processors. Some of the specific topics discussed include: embedded system designs; processors that solve compute intensive problems; computer intensive markets and applications; a schema of application acceleration processes; development and debugging; pipeline scheduling; the ISEF architecture; and design considerations for future C/C++ programming.
{"title":"Software configurable processors change system design","authors":"R. E. Gonzalez","doi":"10.1109/HOTCHIPS.2005.7476595","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2005.7476595","url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation on change system design for software configurable processors. Some of the specific topics discussed include: embedded system designs; processors that solve compute intensive problems; computer intensive markets and applications; a schema of application acceleration processes; development and debugging; pipeline scheduling; the ISEF architecture; and design considerations for future C/C++ programming.","PeriodicalId":357616,"journal":{"name":"2005 IEEE Hot Chips XVII Symposium (HCS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124985221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-08-01DOI: 10.1109/hotchips.2005.7476604
S. Naffziger
Foxton is a system comprised of several key components: accurate power and temperature measurement; fine grained voltage control; dynamic fast-response frequency control; a microcontroller to manage the system. It can be wrapped around any processor or ASIC which can be virtually unchanged except: an asynchronous interface to the rest of the system; must support a wider range of operating voltages. The result is a self-optimizing chip dynamically delivering greatly improved performance/watt.
{"title":"Foxton technology","authors":"S. Naffziger","doi":"10.1109/hotchips.2005.7476604","DOIUrl":"https://doi.org/10.1109/hotchips.2005.7476604","url":null,"abstract":"Foxton is a system comprised of several key components: accurate power and temperature measurement; fine grained voltage control; dynamic fast-response frequency control; a microcontroller to manage the system. It can be wrapped around any processor or ASIC which can be virtually unchanged except: an asynchronous interface to the rest of the system; must support a wider range of operating voltages. The result is a self-optimizing chip dynamically delivering greatly improved performance/watt.","PeriodicalId":357616,"journal":{"name":"2005 IEEE Hot Chips XVII Symposium (HCS)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121604443","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-08-01DOI: 10.1109/HOTCHIPS.2005.7476580
B. Holt
{"title":"Facing the Hot Chiip challllenge (again)","authors":"B. Holt","doi":"10.1109/HOTCHIPS.2005.7476580","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2005.7476580","url":null,"abstract":"","PeriodicalId":357616,"journal":{"name":"2005 IEEE Hot Chips XVII Symposium (HCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121634481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-08-01DOI: 10.1109/HOTCHIPS.2005.7476568
J. E. Smith, Rich Uhlig
This article consists of a collection of slides from the author's conference presentation. Virtual machines have emerged as a powerful tool for computer systems designers. They can be used to enhance software interoperability, mobility, and security, as well as providing means for effective hardware resource management. We survey the spectrum of VM architectures and their applications. These range from the HLL VMs as exemplified by Java, to process VMs that permit cross-platform execution of conventional binaries, to system VMs which support multiple OS environments on a single platform. We then look at some of the important VM architectures and discuss their implementations and features. We will emphasize architecture and hardware mechanisms that provide efficient support for VMs. Several case studies will be discussed, chosen from both commercial implementations and research project
{"title":"HOTCHIPS 17: Tutorial 1, part 2","authors":"J. E. Smith, Rich Uhlig","doi":"10.1109/HOTCHIPS.2005.7476568","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2005.7476568","url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation. Virtual machines have emerged as a powerful tool for computer systems designers. They can be used to enhance software interoperability, mobility, and security, as well as providing means for effective hardware resource management. We survey the spectrum of VM architectures and their applications. These range from the HLL VMs as exemplified by Java, to process VMs that permit cross-platform execution of conventional binaries, to system VMs which support multiple OS environments on a single platform. We then look at some of the important VM architectures and discuss their implementations and features. We will emphasize architecture and hardware mechanisms that provide efficient support for VMs. Several case studies will be discussed, chosen from both commercial implementations and research project","PeriodicalId":357616,"journal":{"name":"2005 IEEE Hot Chips XVII Symposium (HCS)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134251169","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-08-01DOI: 10.1109/HOTCHIPS.2005.7476601
Chen Chang, J. Wawrzynek, B. Brodersen
This paper summarizes our effort to design and construct a high-end reconfigurable computer (HERC) system based solely on field programmable gate arrays (FPGAs) as the processing elements. FPGAs offer many important potential advantages over conventional microprocessors and digital signal processors (DSP), such as flexible arithmetic precision, higher computational density per unit silicon area, and lower power consumption. The programmable interconnect structure unique to FPGA technology makes it possible to tailor a HERC system, such as our BEE2 system, on a per-problem basis to best take advantage of task specific dataflow, memory access patterns, and node-to-node communication patterns. Our BEE2 project is a coordinated attack on the elements needed to demonstrate a practical, cost-effective, high-end reconfigurable computer: the design of a processing module to be used as the building block for a family of high-end reconfigurable computers; the development of several programming models; and the demonstration of the efficiency of the machine on a set of demanding applications, ranging from high-performance digital signal processing and communication systems to traditional scientific computing. On selected DSP applications, BEE2 can provide over 100 times more computing throughput than a microprocessor-based system with similar power consumption and cost. There are several computationally intensive problems central to the research objectives of BWRC that we are using as an application benchmark set and design drivers for the specification of the BEE2 machine architecture and its associated software mapping tools. These applications fall into four broad categories: high-performance real-time digital signal processing, emulation and design of novel wireless communications systems, real-time scientific computation and simulation, and acceleration of computer aided-design (CAD) tools. Due to the diverse application domains targeted by the BEE2 system, any single programming model would not be optimal for all applications; hence the need for domain specific programming models that can fully exploit the computing power of the BEE2 system. Currently the most mature programming model for the BEE2 system is the synchronous data flow model for DSP and communication applications. Commercial tools, including Mathworks Matlab/Simulink, Xilinx System Generator, along with automation tools developed at BWRC, provide automatic mapping from high-level block diagrams and state machine specifications to FPGA configurations. This programming model and tool flow has proven very successful on a variety of projects at BWRC, particularly in the areas of DSP and other datapath intensive streaming applications. To extend this model to support BEE2 specific hardware, stream-based design abstractions are currently being developed for external DRAMs and global communication networks. We have completed the design and fabrication of a compute module comprising five Xilinx X
{"title":"The design and applications of BEE2: A high end reconfigurable computing system","authors":"Chen Chang, J. Wawrzynek, B. Brodersen","doi":"10.1109/HOTCHIPS.2005.7476601","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2005.7476601","url":null,"abstract":"This paper summarizes our effort to design and construct a high-end reconfigurable computer (HERC) system based solely on field programmable gate arrays (FPGAs) as the processing elements. FPGAs offer many important potential advantages over conventional microprocessors and digital signal processors (DSP), such as flexible arithmetic precision, higher computational density per unit silicon area, and lower power consumption. The programmable interconnect structure unique to FPGA technology makes it possible to tailor a HERC system, such as our BEE2 system, on a per-problem basis to best take advantage of task specific dataflow, memory access patterns, and node-to-node communication patterns. Our BEE2 project is a coordinated attack on the elements needed to demonstrate a practical, cost-effective, high-end reconfigurable computer: the design of a processing module to be used as the building block for a family of high-end reconfigurable computers; the development of several programming models; and the demonstration of the efficiency of the machine on a set of demanding applications, ranging from high-performance digital signal processing and communication systems to traditional scientific computing. On selected DSP applications, BEE2 can provide over 100 times more computing throughput than a microprocessor-based system with similar power consumption and cost. There are several computationally intensive problems central to the research objectives of BWRC that we are using as an application benchmark set and design drivers for the specification of the BEE2 machine architecture and its associated software mapping tools. These applications fall into four broad categories: high-performance real-time digital signal processing, emulation and design of novel wireless communications systems, real-time scientific computation and simulation, and acceleration of computer aided-design (CAD) tools. Due to the diverse application domains targeted by the BEE2 system, any single programming model would not be optimal for all applications; hence the need for domain specific programming models that can fully exploit the computing power of the BEE2 system. Currently the most mature programming model for the BEE2 system is the synchronous data flow model for DSP and communication applications. Commercial tools, including Mathworks Matlab/Simulink, Xilinx System Generator, along with automation tools developed at BWRC, provide automatic mapping from high-level block diagrams and state machine specifications to FPGA configurations. This programming model and tool flow has proven very successful on a variety of projects at BWRC, particularly in the areas of DSP and other datapath intensive streaming applications. To extend this model to support BEE2 specific hardware, stream-based design abstractions are currently being developed for external DRAMs and global communication networks. We have completed the design and fabrication of a compute module comprising five Xilinx X","PeriodicalId":357616,"journal":{"name":"2005 IEEE Hot Chips XVII Symposium (HCS)","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129404450","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-08-01DOI: 10.1109/HOTCHIPS.2005.7476593
B. Murmann
This article consists of a collection of slides from the authors' conference presentation on digitally assisted analog circuits. The following topics are addressed: system performance for digital circuits versus analog circuits; the special features of digitally assisted A/D converters; the use of digital computing as the driver to improve A/D conversion; examples of digital assisted A/D converter technologies and performance evaluation; and next generation designs and technological developments.
{"title":"Digitally assisted analog circuits","authors":"B. Murmann","doi":"10.1109/HOTCHIPS.2005.7476593","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2005.7476593","url":null,"abstract":"This article consists of a collection of slides from the authors' conference presentation on digitally assisted analog circuits. The following topics are addressed: system performance for digital circuits versus analog circuits; the special features of digitally assisted A/D converters; the use of digital computing as the driver to improve A/D conversion; examples of digital assisted A/D converter technologies and performance evaluation; and next generation designs and technological developments.","PeriodicalId":357616,"journal":{"name":"2005 IEEE Hot Chips XVII Symposium (HCS)","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125965711","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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