Pub Date : 2005-08-01DOI: 10.1109/HOTCHIPS.2005.7476570
P. Bose
Presents a collection of slides covering the following: power breakdown data; power-performance efficiency metrics; and hierarchical power modeling (levels of abstraction).
展示一系列幻灯片，涵盖以下内容:电源故障数据;电源性能效率指标;分层权力建模(抽象层次)。
{"title":"Power-aware microarchitectures: Design, modeling and metrics","authors":"P. Bose","doi":"10.1109/HOTCHIPS.2005.7476570","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2005.7476570","url":null,"abstract":"Presents a collection of slides covering the following: power breakdown data; power-performance efficiency metrics; and hierarchical power modeling (levels of abstraction).","PeriodicalId":357616,"journal":{"name":"2005 IEEE Hot Chips XVII Symposium (HCS)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130611306","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-08-01DOI: 10.1109/HOTCHIPS.2005.7476583
J. van Lunteren, T. Engbersen
{"title":"High-performance pattern-matching engine for intrusion detection: A new approach for fast programmable accelerators","authors":"J. van Lunteren, T. Engbersen","doi":"10.1109/HOTCHIPS.2005.7476583","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2005.7476583","url":null,"abstract":"","PeriodicalId":357616,"journal":{"name":"2005 IEEE Hot Chips XVII Symposium (HCS)","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132117310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-08-01DOI: 10.1109/HOTCHIPS.2005.7476587
R. Kennedy, D. Petkov
This article consists of a collection of slides from the author's conference presentation. The authors report: Realistic configurations approaching 300 MHz, below 100k gates, below 1.5mW for MP3 decode; Excellent performance on broad set of audio applications, including future codecs; Rich audio instruction set with complete, extension-aware software tools support; Processor remains configurable to take on additional tasks; and Power, performance, and broad codec support that make HiFi2 appropriate for a wide range of consumer and automotive products.
{"title":"Next-generation audio engine","authors":"R. Kennedy, D. Petkov","doi":"10.1109/HOTCHIPS.2005.7476587","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2005.7476587","url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation. The authors report: Realistic configurations approaching 300 MHz, below 100k gates, below 1.5mW for MP3 decode; Excellent performance on broad set of audio applications, including future codecs; Rich audio instruction set with complete, extension-aware software tools support; Processor remains configurable to take on additional tasks; and Power, performance, and broad codec support that make HiFi2 appropriate for a wide range of consumer and automotive products.","PeriodicalId":357616,"journal":{"name":"2005 IEEE Hot Chips XVII Symposium (HCS)","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133588773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-08-01DOI: 10.1109/HOTCHIPS.2005.7476591
V. Lindenstruth
This article consists of a collection of slides from the author's conference presentation. The following slides give a brief overview of the scientific environment of the application for the MIMD Processor. One goal of the experiments under construction is the generation of a quark/gluon plasma, which can only be created by colliding nuclei at very high kinetic energies. The slides show a schematic overview of an appropriate experiment, capable of detecting the reaction products of such collisions. The photos show the experiment at its current state. It is scheduled to take first experimental data in Q2 2007.
{"title":"Low-power, networked MIMD processor for particle physics","authors":"V. Lindenstruth","doi":"10.1109/HOTCHIPS.2005.7476591","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2005.7476591","url":null,"abstract":"This article consists of a collection of slides from the author's conference presentation. The following slides give a brief overview of the scientific environment of the application for the MIMD Processor. One goal of the experiments under construction is the generation of a quark/gluon plasma, which can only be created by colliding nuclei at very high kinetic energies. The slides show a schematic overview of an appropriate experiment, capable of detecting the reaction products of such collisions. The photos show the experiment at its current state. It is scheduled to take first experimental data in Q2 2007.","PeriodicalId":357616,"journal":{"name":"2005 IEEE Hot Chips XVII Symposium (HCS)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127864154","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-08-01DOI: 10.1109/HOTCHIPS.2005.7476598
D. Kirk
{"title":"Multiple cores, multiple pipes, multiple threads - do we have more parallelism than we can handle?","authors":"D. Kirk","doi":"10.1109/HOTCHIPS.2005.7476598","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2005.7476598","url":null,"abstract":"","PeriodicalId":357616,"journal":{"name":"2005 IEEE Hot Chips XVII Symposium (HCS)","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123039416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-08-01DOI: 10.1109/HOTCHIPS.2005.7476578
Takayuki Mihara, H. Muroga, H. Doi, Tadashi Yabuta, Y. Iwagami, K. Ishii, Naohiko Okamoto, Kazuki Iwata, Y. Aoyama, Takeshi Takamiya, N. Sugawa
{"title":"Super companion chip with audio visual interface for cell processor","authors":"Takayuki Mihara, H. Muroga, H. Doi, Tadashi Yabuta, Y. Iwagami, K. Ishii, Naohiko Okamoto, Kazuki Iwata, Y. Aoyama, Takeshi Takamiya, N. Sugawa","doi":"10.1109/HOTCHIPS.2005.7476578","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2005.7476578","url":null,"abstract":"","PeriodicalId":357616,"journal":{"name":"2005 IEEE Hot Chips XVII Symposium (HCS)","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115020050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-08-01DOI: 10.1109/HOTCHIPS.2005.7476596
Tomoyoshi Sato
{"title":"DAPDNA-2 a dynamically reconfigurable processor with 376 32-bit processing elements","authors":"Tomoyoshi Sato","doi":"10.1109/HOTCHIPS.2005.7476596","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2005.7476596","url":null,"abstract":"","PeriodicalId":357616,"journal":{"name":"2005 IEEE Hot Chips XVII Symposium (HCS)","volume":"333 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122876738","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-08-01DOI: 10.1109/HOTCHIPS.2005.7476588
Luis Lucas
Presents a collection of slides covering the following topics: data cache; hardware prefetching; allocate-on-write cache miss policy; bandwidth availability sharing; system on chip; low cost; and low power.
{"title":"High speed low cost nexperia PNX1700 super-pipelined media-processor","authors":"Luis Lucas","doi":"10.1109/HOTCHIPS.2005.7476588","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2005.7476588","url":null,"abstract":"Presents a collection of slides covering the following topics: data cache; hardware prefetching; allocate-on-write cache miss policy; bandwidth availability sharing; system on chip; low cost; and low power.","PeriodicalId":357616,"journal":{"name":"2005 IEEE Hot Chips XVII Symposium (HCS)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123949064","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-08-01DOI: 10.1109/HOTCHIPS.2005.7476599
J. Ball
{"title":"The nios II family of configurable soft-core processors","authors":"J. Ball","doi":"10.1109/HOTCHIPS.2005.7476599","DOIUrl":"https://doi.org/10.1109/HOTCHIPS.2005.7476599","url":null,"abstract":"","PeriodicalId":357616,"journal":{"name":"2005 IEEE Hot Chips XVII Symposium (HCS)","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121482041","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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