Pub Date : 1996-03-18DOI: 10.1109/ASYNC.1996.494453
M. A. Peña, J. Cortadella
This paper presents a new methodology to automatically synthesize asynchronous circuits from descriptions based on process algebra. Traditionally, syntax-directed techniques have been used to generate a netlist of basic components previously implemented by skilled designers. However, the generality of the approach often involves the insertion of redundant functionality to the circuit. We propose a new approach based on the composition of Petri nets and the automatic synthesis through Signal Transition Graphs that allows to take advantage of logic synthesis methods to optimize the circuit and make it portable far different delay models and technologies. Some preliminary experimental results have shown the effectiveness of the approach to improve the quality of the circuits.
{"title":"Combining process algebras and Petri nets for the specification and synthesis of asynchronous circuits","authors":"M. A. Peña, J. Cortadella","doi":"10.1109/ASYNC.1996.494453","DOIUrl":"https://doi.org/10.1109/ASYNC.1996.494453","url":null,"abstract":"This paper presents a new methodology to automatically synthesize asynchronous circuits from descriptions based on process algebra. Traditionally, syntax-directed techniques have been used to generate a netlist of basic components previously implemented by skilled designers. However, the generality of the approach often involves the insertion of redundant functionality to the circuit. We propose a new approach based on the composition of Petri nets and the automatic synthesis through Signal Transition Graphs that allows to take advantage of logic synthesis methods to optimize the circuit and make it portable far different delay models and technologies. Some preliminary experimental results have shown the effectiveness of the approach to improve the quality of the circuits.","PeriodicalId":365358,"journal":{"name":"Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132261866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-03-18DOI: 10.1109/ASYNC.1996.494442
M. Bush, M. B. Josephs
Asynchronous circuits are often designed to operate correctly whatever the speeds of the elements (e.g., logic gates) out of which they are constructed. Sometimes, however, one finds that it is not possible to synthesise a speed-independent circuit that implements a given specification. The fundamental reason for these limitations to speed-independence is that certain local properties of elements manifest themselves as global properties of circuits, properties that may be incompatible with the specification to be implemented. This paper investigates several such properties (concerned with persistence, commutativity and inertia) by means of a formal analysis carried out using Josephs' Receptive Process Theory.
{"title":"Some limitations to speed-independence in asynchronous circuits","authors":"M. Bush, M. B. Josephs","doi":"10.1109/ASYNC.1996.494442","DOIUrl":"https://doi.org/10.1109/ASYNC.1996.494442","url":null,"abstract":"Asynchronous circuits are often designed to operate correctly whatever the speeds of the elements (e.g., logic gates) out of which they are constructed. Sometimes, however, one finds that it is not possible to synthesise a speed-independent circuit that implements a given specification. The fundamental reason for these limitations to speed-independence is that certain local properties of elements manifest themselves as global properties of circuits, properties that may be incompatible with the specification to be implemented. This paper investigates several such properties (concerned with persistence, commutativity and inertia) by means of a formal analysis carried out using Josephs' Receptive Process Theory.","PeriodicalId":365358,"journal":{"name":"Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125437257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1996-03-18DOI: 10.1109/ASYNC.1996.494454
T. Kolks, S. Vercauteren, Bill Lin
Syntax directed translation based compilation from high-level concurrent programs has matured significantly over the past few years. They have been applied to significant designs in the domains of digital signal processing and microprocessor designs. For data-path dominated designs, like those found in digital signal processing applications, syntax directed translation approaches have been shown to generate efficient asynchronous implementations. However for control-dominated designs where the data processing parts play a relatively minor role, we believe the solutions produced by pure syntax directed translation methods may be significantly improved. In this paper we consider the problem of resynthesizing the control parts of the syntax directed translation solutions by means of STG based algorithmic synthesis approaches. This involves a strategy for partitioning between the control and data processing parts, algorithms for reconstructing the STGs from the control partitions, and a strategy for resynthesizing these reconstructed STGs using existing STG-based synthesis approaches. We show with a realistic design experiment that our control resynthesis approach can offer significant improvements over pure syntax directed translation solutions.
{"title":"Control resynthesis for control-dominated asynchronous designs","authors":"T. Kolks, S. Vercauteren, Bill Lin","doi":"10.1109/ASYNC.1996.494454","DOIUrl":"https://doi.org/10.1109/ASYNC.1996.494454","url":null,"abstract":"Syntax directed translation based compilation from high-level concurrent programs has matured significantly over the past few years. They have been applied to significant designs in the domains of digital signal processing and microprocessor designs. For data-path dominated designs, like those found in digital signal processing applications, syntax directed translation approaches have been shown to generate efficient asynchronous implementations. However for control-dominated designs where the data processing parts play a relatively minor role, we believe the solutions produced by pure syntax directed translation methods may be significantly improved. In this paper we consider the problem of resynthesizing the control parts of the syntax directed translation solutions by means of STG based algorithmic synthesis approaches. This involves a strategy for partitioning between the control and data processing parts, algorithms for reconstructing the STGs from the control partitions, and a strategy for resynthesizing these reconstructed STGs using existing STG-based synthesis approaches. We show with a realistic design experiment that our control resynthesis approach can offer significant improvements over pure syntax directed translation solutions.","PeriodicalId":365358,"journal":{"name":"Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1996-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116673759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ASYNC.1996.494449
C. Foley
Determining metastability characteristics is challenging. Devising reliable and repeatable experiments and procedures requires time, patience, care and knowledge. This discussion presents practical measurement techniques to accurately determine the Resolving Time Constant (/spl tau/) and Metastability Window (W). Also included is a method for observing the metastability failure rate at a designated time following the clock. By converting this failure rate to observed MTBF (Mean Time Between Failure), a comparison is made to a predicted MTBF.
{"title":"Characterizing metastability","authors":"C. Foley","doi":"10.1109/ASYNC.1996.494449","DOIUrl":"https://doi.org/10.1109/ASYNC.1996.494449","url":null,"abstract":"Determining metastability characteristics is challenging. Devising reliable and repeatable experiments and procedures requires time, patience, care and knowledge. This discussion presents practical measurement techniques to accurately determine the Resolving Time Constant (/spl tau/) and Metastability Window (W). Also included is a method for observing the metastability failure rate at a designated time following the clock. By converting this failure rate to observed MTBF (Mean Time Between Failure), a comparison is made to a predicted MTBF.","PeriodicalId":365358,"journal":{"name":"Proceedings Second International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123431585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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