The main contribution of this work is to propose a distributed and collaborative cache solution in which the decisions to cache objects are performed in a collaborative way. In our solution, objects are classified in private and shared objects. Private objects are managed as in an individual cache system whereas the management of shared objects are performed collectively and are stored in a shared area. The simulation results have shown that our solution can expressively reduce the server load by increasing cache diversity and the probability of cache hits. Also, our solution provides significant savings in terms of battery power and congestion on the routes towards the sink node.
{"title":"A Cluster Based Collaborative Cache Approach for MANETs","authors":"Marcos F. Caetano, J. Bordim","doi":"10.1109/IC-NC.2010.41","DOIUrl":"https://doi.org/10.1109/IC-NC.2010.41","url":null,"abstract":"The main contribution of this work is to propose a distributed and collaborative cache solution in which the decisions to cache objects are performed in a collaborative way. In our solution, objects are classified in private and shared objects. Private objects are managed as in an individual cache system whereas the management of shared objects are performed collectively and are stored in a shared area. The simulation results have shown that our solution can expressively reduce the server load by increasing cache diversity and the probability of cache hits. Also, our solution provides significant savings in terms of battery power and congestion on the routes towards the sink node.","PeriodicalId":375145,"journal":{"name":"2010 First International Conference on Networking and Computing","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132811184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A skip graph is a valuable overlay network for searching for keys in a peer-to-peer application. A problem with the construction algorithm for skip graphs is that it does not consider the proximity of adjacent peers. Because of this, a skip graph often contains links with considerably high communication time. Another problem is that due to the random nature of the algorithm, a skip graph often exhibits structural imbalance. In this paper, we propose a topology reconstruction algorithm to solve these problems. This algorithm, iteratively executed by each node, evaluates both proximity and topological balance and reshapes the overlay topology if necessary. The results of simulations show that the skip graph constructed by our approach achieves shorter search delay than the original skip graph.
{"title":"Balance and Proximity-Aware Skip Graph Construction","authors":"Fuminori Makikawa, Tatsuhiro Tsuchiya, T. Kikuno","doi":"10.1109/IC-NC.2010.59","DOIUrl":"https://doi.org/10.1109/IC-NC.2010.59","url":null,"abstract":"A skip graph is a valuable overlay network for searching for keys in a peer-to-peer application. A problem with the construction algorithm for skip graphs is that it does not consider the proximity of adjacent peers. Because of this, a skip graph often contains links with considerably high communication time. Another problem is that due to the random nature of the algorithm, a skip graph often exhibits structural imbalance. In this paper, we propose a topology reconstruction algorithm to solve these problems. This algorithm, iteratively executed by each node, evaluates both proximity and topological balance and reshapes the overlay topology if necessary. The results of simulations show that the skip graph constructed by our approach achieves shorter search delay than the original skip graph.","PeriodicalId":375145,"journal":{"name":"2010 First International Conference on Networking and Computing","volume":"277 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125851346","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A Field Programmable Gate Array (FPGA) is used to embed a circuit designed by users instantly. FPGAs can be used for implementing hardware algorithms. Most of FPGAs have Configurable Logic Blocks (CLBs) to implement combinational and sequential circuits and block RAMs to implement Random Access Memories (RAMs) and Read Only Memories (ROMs). Circuit design that minimizes the number of clock cycles is easy if we use asynchronous read operations. However, most RAMs and ROMs in modern FPGAs support synchronous read operations, but do not support asynchronous read operations. It is one of the main difficulties for users to implement hardware algorithms using RAMs and ROMs with synchronous read operations. The main contribution of this paper is to provide one of the potent methods to resolve this problem. We assume that a circuit using asynchronous ROMs designed by a user is given. Our goal is to convert this circuit into an equivalent circuit with synchronous ROMs. We first clarify the condition that a given circuit with asynchronous ROMs can be converted into a circuit without asynchronous ROMs. For this purpose, we will show an algorithm that can generate a circuit with synchronous ROMs, whenever the original circuit with asynchronous ROMs satisfies this condition. Using our conversion algorithm, users can assume that FPGAs support asynchronous ROMs when they design their circuits. Finally, we will show that we can generate an almost equivalent circuit with synchronous ROMs by modifying the circuit even if it does not satisfy this condition.
{"title":"A Rewriting Algorithm to Generate AROM-free Fully Synchronous Circuits","authors":"Md. Nazrul Islam Mondal, K. Nakano, Yasuaki Ito","doi":"10.1109/IC-NC.2010.54","DOIUrl":"https://doi.org/10.1109/IC-NC.2010.54","url":null,"abstract":"A Field Programmable Gate Array (FPGA) is used to embed a circuit designed by users instantly. FPGAs can be used for implementing hardware algorithms. Most of FPGAs have Configurable Logic Blocks (CLBs) to implement combinational and sequential circuits and block RAMs to implement Random Access Memories (RAMs) and Read Only Memories (ROMs). Circuit design that minimizes the number of clock cycles is easy if we use asynchronous read operations. However, most RAMs and ROMs in modern FPGAs support synchronous read operations, but do not support asynchronous read operations. It is one of the main difficulties for users to implement hardware algorithms using RAMs and ROMs with synchronous read operations. The main contribution of this paper is to provide one of the potent methods to resolve this problem. We assume that a circuit using asynchronous ROMs designed by a user is given. Our goal is to convert this circuit into an equivalent circuit with synchronous ROMs. We first clarify the condition that a given circuit with asynchronous ROMs can be converted into a circuit without asynchronous ROMs. For this purpose, we will show an algorithm that can generate a circuit with synchronous ROMs, whenever the original circuit with asynchronous ROMs satisfies this condition. Using our conversion algorithm, users can assume that FPGAs support asynchronous ROMs when they design their circuits. Finally, we will show that we can generate an almost equivalent circuit with synchronous ROMs by modifying the circuit even if it does not satisfy this condition.","PeriodicalId":375145,"journal":{"name":"2010 First International Conference on Networking and Computing","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125999971","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper we propose a novel “Mesh-of-Tori” cellular interconnection network for scalable and massively parallel array processors with frontal plane I/O. The unit (called “m-Cell”) in this topology is the smallest double (for 2D case) or triple (for 3D) folded torus, which forms the basic ‘tile’. The Cells can be repeated and “fused” to form macro-Cells, or “divided” to form smaller Cells, without destroying the homogeneity of the entire structure, to give a highly scalable and cellular “Mesh-of-Tori” topology. The key features of the proposed interconnection network are (1) an excellent up and down scalability due to regularity and modularity, (2) no end-around connections, and (3) capability to map 2D streaming data from frontal plane I/O (stacked layer of sensors) to the processing elements. We also provide solutions for stream data manipulation through frontal plane I/O, on the propose d cellular topology.
{"title":"Mesh-of-Tori: A Novel Interconnection Network for Frontal Plane Cellular Processors","authors":"A. Ravankar, S. Sedukhin","doi":"10.1109/IC-NC.2010.30","DOIUrl":"https://doi.org/10.1109/IC-NC.2010.30","url":null,"abstract":"In this paper we propose a novel “Mesh-of-Tori” cellular interconnection network for scalable and massively parallel array processors with frontal plane I/O. The unit (called “m-Cell”) in this topology is the smallest double (for 2D case) or triple (for 3D) folded torus, which forms the basic ‘tile’. The Cells can be repeated and “fused” to form macro-Cells, or “divided” to form smaller Cells, without destroying the homogeneity of the entire structure, to give a highly scalable and cellular “Mesh-of-Tori” topology. The key features of the proposed interconnection network are (1) an excellent up and down scalability due to regularity and modularity, (2) no end-around connections, and (3) capability to map 2D streaming data from frontal plane I/O (stacked layer of sensors) to the processing elements. We also provide solutions for stream data manipulation through frontal plane I/O, on the propose d cellular topology.","PeriodicalId":375145,"journal":{"name":"2010 First International Conference on Networking and Computing","volume":"2227 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130186389","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Modern Super scalar Processor squashes up all of wrong-path instructions when the branch prediction misses. In deeper pipelines, branch miss prediction penalty increases seriously owing to large number of squashed instructions. Exploiting control independence has been proposed for reducing this penalty. Control Independence method reuses control independent instructions (CI instructions) without squashing when branch prediction misses. Reusing CI instructions at branch miss prediction is not easy because of changing data dependency between squashed instructions and CI instructions. Conventional researches of CI architecture require complex Re-renaming mechanism, or with a limited applicability. This paper proposes a new mechanism named Dual Renaming for reusing CI instructions. It assigns two tags for each source register of CI instruction, and solves data dependency with simple mechanism when branch miss prediction is detected. The simulation result shows that Dual Renaming mechanism increases IPCs by maximum 29.52%.
现代超级标量处理器会在分支预测失误时压制所有错误路径指令。在较深的流水线中，由于大量指令被压扁，分支预测失误的惩罚会严重增加。有人提出利用控制独立性来减少这种惩罚。控制独立方法是在分支预测失误时重复使用控制独立指令（CI 指令），而不进行挤压。由于被挤压指令和 CI 指令之间的数据依赖性不断变化，因此在分支预测未命中时重复使用 CI 指令并不容易。传统的 CI 架构研究需要复杂的重新命名机制，或者适用性有限。本文提出了一种名为 "双重重命名 "的新机制，用于重用 CI 指令。它为 CI 指令的每个源寄存器分配两个标记，并在检测到分支未命中预测时通过简单的机制解决数据依赖性问题。仿真结果表明，双重命名机制最多可将 IPC 提高 29.52%。
{"title":"Control Independence Using Dual Renaming","authors":"Lin Meng, S. Oyanagi","doi":"10.1109/IC-NC.2010.16","DOIUrl":"https://doi.org/10.1109/IC-NC.2010.16","url":null,"abstract":"Modern Super scalar Processor squashes up all of wrong-path instructions when the branch prediction misses. In deeper pipelines, branch miss prediction penalty increases seriously owing to large number of squashed instructions. Exploiting control independence has been proposed for reducing this penalty. Control Independence method reuses control independent instructions (CI instructions) without squashing when branch prediction misses. Reusing CI instructions at branch miss prediction is not easy because of changing data dependency between squashed instructions and CI instructions. Conventional researches of CI architecture require complex Re-renaming mechanism, or with a limited applicability. This paper proposes a new mechanism named Dual Renaming for reusing CI instructions. It assigns two tags for each source register of CI instruction, and solves data dependency with simple mechanism when branch miss prediction is detected. The simulation result shows that Dual Renaming mechanism increases IPCs by maximum 29.52%.","PeriodicalId":375145,"journal":{"name":"2010 First International Conference on Networking and Computing","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128006291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
GPU has a good performance ratio and exhibits the capability for applications with high level of parallelism despite its inexpensive price. The support of integer and logical instructions on the latest generation of GPU makes us to implement cipher algorithms easier with the same instructions. However the decisions such as parallel processing granularity or memory allocation place imposed heavy burden on programmers. For this reason this paper shows the results of several experiments to study relation between memory allocation style of AES parameters and granularity as the parallelism exploited from AES encoding process using CUDA with NVIDIA Geforce GTX285. The result of experiments cleared up that the 16Byte/thread granularity had the highest performance and it achieved approximately 35Gbps throughput. Moreover, implementation with overlapping between processing and data transfer brought up 22.5Gbps throughput including data transfer time. Also, it cleared up that it is important to decide granularity and memory allocation to effective processing in AES encryption on GPU.
{"title":"AES Encryption Implementation on CUDA GPU and Its Analysis","authors":"Keisuke Iwai, T. Kurokawa, Naoki Nishikawa","doi":"10.1109/IC-NC.2010.49","DOIUrl":"https://doi.org/10.1109/IC-NC.2010.49","url":null,"abstract":"GPU has a good performance ratio and exhibits the capability for applications with high level of parallelism despite its inexpensive price. The support of integer and logical instructions on the latest generation of GPU makes us to implement cipher algorithms easier with the same instructions. However the decisions such as parallel processing granularity or memory allocation place imposed heavy burden on programmers. For this reason this paper shows the results of several experiments to study relation between memory allocation style of AES parameters and granularity as the parallelism exploited from AES encoding process using CUDA with NVIDIA Geforce GTX285. The result of experiments cleared up that the 16Byte/thread granularity had the highest performance and it achieved approximately 35Gbps throughput. Moreover, implementation with overlapping between processing and data transfer brought up 22.5Gbps throughput including data transfer time. Also, it cleared up that it is important to decide granularity and memory allocation to effective processing in AES encryption on GPU.","PeriodicalId":375145,"journal":{"name":"2010 First International Conference on Networking and Computing","volume":"181 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123346701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Shinya Takamaeda-Yamazaki, Shimpei Sato, T. Miyoshi, Kenji Kise
Dependability of many-core processors is a very important topic. To improve the dependability, we propose the Smart Core system, which is a smart many-core system with redundant cores and multifunction routers. The multifunction router has three functions: copying packets, changing the destinations of packets, and rendezvousing and comparing two packets from different nodes. Using these additional functions, the Smart Core system realizes redundant execution on multiple cores and detects execution errors at the packet level. We implemented a many-core processor with the Smart Core system on a software simulator. The evalution result shows that the performance overhead of packet rendezvous is small, up to 4.1%. In addition, we verified that a dependable many-core processor with the Smart Core system detects execution errors on a hardware prototyping system.
{"title":"Smart Core System for Dependable Many-Core Processor with Multifunction Routers","authors":"Shinya Takamaeda-Yamazaki, Shimpei Sato, T. Miyoshi, Kenji Kise","doi":"10.1109/IC-NC.2010.53","DOIUrl":"https://doi.org/10.1109/IC-NC.2010.53","url":null,"abstract":"Dependability of many-core processors is a very important topic. To improve the dependability, we propose the Smart Core system, which is a smart many-core system with redundant cores and multifunction routers. The multifunction router has three functions: copying packets, changing the destinations of packets, and rendezvousing and comparing two packets from different nodes. Using these additional functions, the Smart Core system realizes redundant execution on multiple cores and detects execution errors at the packet level. We implemented a many-core processor with the Smart Core system on a software simulator. The evalution result shows that the performance overhead of packet rendezvous is small, up to 4.1%. In addition, we verified that a dependable many-core processor with the Smart Core system detects execution errors on a hardware prototyping system.","PeriodicalId":375145,"journal":{"name":"2010 First International Conference on Networking and Computing","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125674761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Tomoki Ikegaya, Tomoaki Tsumura, H. Matsuo, Y. Nakashima
We have proposed an auto-memoization processor based on computation reuse, and merged it with speculative multithreading based on value prediction into a parallel early computation. In the past model, the parallel early computation detects each iteration of loops as a reusable block. This paper proposes a new parallel early computation model, which integrates multiple continuous iterations into a reusable block automatically and dynamically without modifing executable binaries. We also propose a model for automatically detecting how many iterations should be integrated into one reusable block. Our model reduces the overhead of computation reuse, and further exploits reuse tables. The result of the experiment with SPEC CPU95 FP suite benchmarks shows that the new model improves the maximum speedup from 40.5% to 57.6%, and the average speedup from 15.0% to 26.0%.
{"title":"A Speed-Up Technique for an Auto-Memoization Processor by Collectively Reusing Continuous Iterations","authors":"Tomoki Ikegaya, Tomoaki Tsumura, H. Matsuo, Y. Nakashima","doi":"10.1109/IC-NC.2010.46","DOIUrl":"https://doi.org/10.1109/IC-NC.2010.46","url":null,"abstract":"We have proposed an auto-memoization processor based on computation reuse, and merged it with speculative multithreading based on value prediction into a parallel early computation. In the past model, the parallel early computation detects each iteration of loops as a reusable block. This paper proposes a new parallel early computation model, which integrates multiple continuous iterations into a reusable block automatically and dynamically without modifing executable binaries. We also propose a model for automatically detecting how many iterations should be integrated into one reusable block. Our model reduces the overhead of computation reuse, and further exploits reuse tables. The result of the experiment with SPEC CPU95 FP suite benchmarks shows that the new model improves the maximum speedup from 40.5% to 57.6%, and the average speedup from 15.0% to 26.0%.","PeriodicalId":375145,"journal":{"name":"2010 First International Conference on Networking and Computing","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126681723","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Peer-to-Peer (P2P) systems have attracted considerable attention in recent years, as a key technology to realize scalable, dependable network services. However, because of its high anonymity, P2P systems involve several flaws such as the weakness against malicious attacks by anonymous peers. In this paper, we propose a method to evaluate the trustfulness of each peer by explicitly taking into account the reliability of mutual evaluations. The proposed method is an improvement of the Eigen Trust algorithm proposed by Kamvar et al. which calculates a global trust vector consistent with the observed local trust vectors under the weighted sum in a linear space. The performance of the proposed method is evaluated by simulation. The result of simulations indicates that the proposed method identifies a large subset of reliable peers with sufficiently small number of message transmissions compared with previous schemes including the original Eigen Trust.
{"title":"An Effective Risk Avoidance Scheme for the EigenTrust Reputation Management System","authors":"Takuya Nishikawa, S. Fujita","doi":"10.1109/IC-NC.2010.28","DOIUrl":"https://doi.org/10.1109/IC-NC.2010.28","url":null,"abstract":"Peer-to-Peer (P2P) systems have attracted considerable attention in recent years, as a key technology to realize scalable, dependable network services. However, because of its high anonymity, P2P systems involve several flaws such as the weakness against malicious attacks by anonymous peers. In this paper, we propose a method to evaluate the trustfulness of each peer by explicitly taking into account the reliability of mutual evaluations. The proposed method is an improvement of the Eigen Trust algorithm proposed by Kamvar et al. which calculates a global trust vector consistent with the observed local trust vectors under the weighted sum in a linear space. The performance of the proposed method is evaluated by simulation. The result of simulations indicates that the proposed method identifies a large subset of reliable peers with sufficiently small number of message transmissions compared with previous schemes including the original Eigen Trust.","PeriodicalId":375145,"journal":{"name":"2010 First International Conference on Networking and Computing","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115717717","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Modern multiprocessor architectures have exacerbated problems of coordinating access to shared data, in particular as regards to the possibility of deadlock. For example semaphores, one of the most basic synchronization primitives, present difficulties. Djikstra defined semaphores to solve the problem of mutual exclusion. Practical implementation of the concept has, however, produced semaphores that are prone to deadlock, even while the original definition is theoretically free of it. This is not simply due to bad programming, but we have lacked a theory that allows us to understand the problem. We introduce a formal definition and new general theory of synchronization. We illustrate its applicability by deriving basic deadlock properties, to show where the problem lies with semaphores and also to guide us in finding some simple modifications to semaphores that greatly ameliorate the problem. We suggest some future directions for deadlock resolution that also avoid resource starvation.
{"title":"Algebra of Synchronization with Application to Deadlock and Semaphores","authors":"E. Gomez, K. Schubert","doi":"10.1109/IC-NC.2010.43","DOIUrl":"https://doi.org/10.1109/IC-NC.2010.43","url":null,"abstract":"Modern multiprocessor architectures have exacerbated problems of coordinating access to shared data, in particular as regards to the possibility of deadlock. For example semaphores, one of the most basic synchronization primitives, present difficulties. Djikstra defined semaphores to solve the problem of mutual exclusion. Practical implementation of the concept has, however, produced semaphores that are prone to deadlock, even while the original definition is theoretically free of it. This is not simply due to bad programming, but we have lacked a theory that allows us to understand the problem. We introduce a formal definition and new general theory of synchronization. We illustrate its applicability by deriving basic deadlock properties, to show where the problem lies with semaphores and also to guide us in finding some simple modifications to semaphores that greatly ameliorate the problem. We suggest some future directions for deadlock resolution that also avoid resource starvation.","PeriodicalId":375145,"journal":{"name":"2010 First International Conference on Networking and Computing","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2010-11-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124839304","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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