信息与控制最新文献

Branching programs are a general model of sequential computation. One of their computational features is their possibility to question (repeatedly) the information from each input bit. Real-time branching programs make at most n questions when computing on an input of length n. The restriction “real-time” allows to find a simple language which requires the lower bound 2^√2n/8 on memory (= the state space).

Every infinite sequence is Turing-reducible to an infinite sequence which is random in the sense of Martin-Löf.

We present two (closely-related) propositional probabilistic temporal logics based on temporal logics of branching time as introduced by Ben-Ari, Pnueli, and Manna (Acta Inform. 20 (1983), 207–226), Emerson and Halpern (“Proceedings, 14th ACM Sympos. Theory of Comput.,” 1982, pp. 169–179, and Emerson and Clarke (Sci. Comput. Program. 2 (1982), 241–266). The first logic, PTL_f, is interpreted over finite models, while the second logic, PTL_b, which is an extension of the first one, is interpreted over infinite models with transition probabilities bounded away from 0. The logic PTL_f allows us to reason about finite-state sequential probabilistic programs, and the logic PTL_b allows us to reason about (finite-state) concurrent probabilistic programs, without any explicit reference to the actual values of their state-transition probabilities. A generalization of the tableau method yields deterministic single-exponential time decision procedures for our logics, and complete axiomatizations of them are given. Several meta-results, including the absence of a finite-model property for PTL_b, and the connection between satisfiable formulae of PTL_b and finite state concurrent probabilistic programs, are also discussed.

Simultaneous resource bounded complexity classes for nondeterministic single worktape off-line Turing machines are considered such as time-space bounded classes, denoted by NTISP₁(T, S), reversal-space bounded classes, denoted by NRESP₁(R, S), and time-reversal bounded classes, denoted by NTIRE₁(T, R). It is shown that NRESP₁(R(n), S(n)) contains NTISP₁(S(n), R(n)) and is contained in NTISP₁(R(n) S(n)n² log n, R(n) log n). The following corollaries follow: (1) the affirmative solution to the nondeterministic single worktape version of the NC = ? SC problem, NTIRE₁(poly, polylog) = NTISP₁(poly, polylog), and (2) a reversal-space trade-off, NRESP₁(polylog, poly) = NRESP₁(poly, polylog).

A safe and deadlock free locking policy is introduced, called pre-analysis locking. A transaction system with no lock and unlock operations in the transactions is first being analyzed by the pre-analysis locking algorithm. Then, the result of this analysis is used to insert lock and unlock operations into the transactions with the goal of achieving a degree of concurrency as high as possible. However, pre-analysis locking is merely a heuristic operating in polynomial time; therefore, it is not guaranteed to perform optimally in all cases. In comparison with 2-phase locking, neither pre-analysis locking nor 2-phase locking dominates the other; there exist transaction systems in which pre-analysis locking allows for more concurrency than any 2-phase locking policy, but there are also cases in which a 2-phase locking policy allows for more concurrency than pre-analysis locking. However, preanalysis locking is free from deadlocks, in general.

A function of boolean arguments is symmetric if its value depends solely on the number of 1's among its arguments. In the first part of this paper we partially characterize those symmetric functions that can be computed by constant-depth polynomial-size sequences of boolean circuits, and discuss the complete characterization. (We treat both uniform and non-uniform sequences of circuits.) Our results imply that these circuits can compute functions that are not definable in first-order logic. In the second part of the paper we generalize from circuits computing symmetric functions to circuits recognizing first-order structures. By imposing fairly natural restrictions we develop a circuit model with precisely the power of first-order logic: a class of structures is first-order definable if and only if it can be recognized by a constant-depth polynomial-time sequence of such circuits.

In this paper we investigate inductive inference identification criteria which permit infinitely many errors in explanations, but which require that the “density” of these errors be no more than a certain, prespectified amount. We introduce three hierarchies of such criteria, each of which has the same order type as the real unit interval. These three hierarchies are progressively more strict in the way they measure density of errors of explanations. The strictest of the three turns out to have all of its members, save one, incomparable to the identification criterion which permits finitely many errors in explanations.

Let A be a recursive problem not in P. Lynch has shown that A then has an infinite recursive polynomial complexity core. This is a collection C of instances of A such that every algorithm deciding A needs more than polynomial time almost everywhere on C. We investigate the complexity of recognizing the instances in such a core, and show that every recursive problem A not in P has an infinite core recognizable in subexponential time. We further study how dense the core sets for A can be, under various assumptions about the structure of A. Our main results in this direction are that if P ≠ NP, then NP-complete problems have polynomially nonsparse cores recognizable in subexponential time, and that EXPTIME-complete problems have cores of exponential density recognizable in exponential time.