Pub Date : 2018-10-01DOI: 10.1109/igcc.2018.8752142
{"title":"Panel on Computational Methods and Challenges to Enabling Renewable Power Grid Integration","authors":"","doi":"10.1109/igcc.2018.8752142","DOIUrl":"https://doi.org/10.1109/igcc.2018.8752142","url":null,"abstract":"","PeriodicalId":388554,"journal":{"name":"2018 Ninth International Green and Sustainable Computing Conference (IGSC)","volume":"66 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128362147","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/IGCC.2018.8752136
A. Wijayasiri, Tania Banerjee-Mishra, S. Ranka, S. Sahni, M. Schmalz
The reconstruction of nxn-pixel Synthetic Aperture Radar (SAR) imagery using a Back Projection algorithm incurs O(n2 · m) cost, where n2 is the number of pixels and m is the number of pulses. We have developed parallel algorithms and software for constructing multi-resolution SAR images on many-core architectures. We also develop load balancing algorithms for distributing workload to the available cores, thereby optimizing performance and energy. We evaluate the performance of our algorithms and the resulting energy consumption on an Intel Knights Landing (KNL) processor. We also present a comparison of execution time and energy between KNL, Ivy Bridge and Tesla K40m processors.
{"title":"Performance and Energy Evaluation of SAR Reconstruction on Intel Knights Landing","authors":"A. Wijayasiri, Tania Banerjee-Mishra, S. Ranka, S. Sahni, M. Schmalz","doi":"10.1109/IGCC.2018.8752136","DOIUrl":"https://doi.org/10.1109/IGCC.2018.8752136","url":null,"abstract":"The reconstruction of nxn-pixel Synthetic Aperture Radar (SAR) imagery using a Back Projection algorithm incurs O(n2 · m) cost, where n2 is the number of pixels and m is the number of pulses. We have developed parallel algorithms and software for constructing multi-resolution SAR images on many-core architectures. We also develop load balancing algorithms for distributing workload to the available cores, thereby optimizing performance and energy. We evaluate the performance of our algorithms and the resulting energy consumption on an Intel Knights Landing (KNL) processor. We also present a comparison of execution time and energy between KNL, Ivy Bridge and Tesla K40m processors.","PeriodicalId":388554,"journal":{"name":"2018 Ninth International Green and Sustainable Computing Conference (IGSC)","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129574563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-10-01DOI: 10.1109/IGCC.2018.8752108
Sanjeev Sondur, K. Gross, Mengying Li
Data centers consume enormous energy, presently reported up to 2% of the world’s electricity, with most of this energy then rejected into the atmosphere as waste heat. Meanwhile there is a global scarcity of safe drinking water. The UN states that 20% of the world’s population lives in regions affected by scarcity of drinking water. In this paper, we discuss an on-going research initiative that investigates the reuse of “free” waste heat energy from data centers in coastal cities and island countries, and in modular data centers that are deployed in coastal regions, through a low-pressure desalination process that converts sea water into safe drinking and irrigation water supplies, while significantly improving the Power Utilization Efficiency (PUE) for the data centers. In this paper, we discuss a work-in-progress experimental setup with the purpose of demonstrating that heat removed via common fluid-cooled rack heat exchangers in modern data centers can be re-used via a controlled-low-pressure desalination technique to turn salt water into drinking water at zero added carbon cost for the desalination, and significantly reduced carbon cost for the data center operations.
{"title":"Data Center Cooling System Integrated with Low-Temperature Desalination and Intelligent Energy-Aware Control","authors":"Sanjeev Sondur, K. Gross, Mengying Li","doi":"10.1109/IGCC.2018.8752108","DOIUrl":"https://doi.org/10.1109/IGCC.2018.8752108","url":null,"abstract":"Data centers consume enormous energy, presently reported up to 2% of the world’s electricity, with most of this energy then rejected into the atmosphere as waste heat. Meanwhile there is a global scarcity of safe drinking water. The UN states that 20% of the world’s population lives in regions affected by scarcity of drinking water. In this paper, we discuss an on-going research initiative that investigates the reuse of “free” waste heat energy from data centers in coastal cities and island countries, and in modular data centers that are deployed in coastal regions, through a low-pressure desalination process that converts sea water into safe drinking and irrigation water supplies, while significantly improving the Power Utilization Efficiency (PUE) for the data centers. In this paper, we discuss a work-in-progress experimental setup with the purpose of demonstrating that heat removed via common fluid-cooled rack heat exchangers in modern data centers can be re-used via a controlled-low-pressure desalination technique to turn salt water into drinking water at zero added carbon cost for the desalination, and significantly reduced carbon cost for the data center operations.","PeriodicalId":388554,"journal":{"name":"2018 Ninth International Green and Sustainable Computing Conference (IGSC)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133083862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2018-09-24DOI: 10.1109/IGCC.2018.8752146
Edgard Muñoz-Coreas, H. Thapliyal
Quantum circuits for basic image processing functions such as bilinear interpolation are required to implement image processing algorithms on quantum computers. In this work, we propose quantum circuits for the bilinear interpolation of NEQR encoded images based on Clifford+T gates. Quantum circuits for the scale up operation and scale down operation are illustrated. The proposed quantum circuits are based on quantum Clifford+T gates and are optimized for T-count. Quantum circuits based on Clifford+T gates can be made fault tolerant but the T gate is very costly to implement. As a result, reducing T-count is an important optimization goal. The proposed quantum bilinear interpolation circuits are based on (i) a quantum adder, (ii) a proposed quantum subtractor, and (iii) a quantum multiplication circuit. Further, both designs are compared and shown to be superior to existing work in terms of T-count. The proposed quantum bilinear interpolation circuits for the scale down operation and for the scale up operation each have a 92.52% improvement in terms of T-count compared to the existing work.
{"title":"T-count Optimized Quantum Circuits for Bilinear Interpolation","authors":"Edgard Muñoz-Coreas, H. Thapliyal","doi":"10.1109/IGCC.2018.8752146","DOIUrl":"https://doi.org/10.1109/IGCC.2018.8752146","url":null,"abstract":"Quantum circuits for basic image processing functions such as bilinear interpolation are required to implement image processing algorithms on quantum computers. In this work, we propose quantum circuits for the bilinear interpolation of NEQR encoded images based on Clifford+T gates. Quantum circuits for the scale up operation and scale down operation are illustrated. The proposed quantum circuits are based on quantum Clifford+T gates and are optimized for T-count. Quantum circuits based on Clifford+T gates can be made fault tolerant but the T gate is very costly to implement. As a result, reducing T-count is an important optimization goal. The proposed quantum bilinear interpolation circuits are based on (i) a quantum adder, (ii) a proposed quantum subtractor, and (iii) a quantum multiplication circuit. Further, both designs are compared and shown to be superior to existing work in terms of T-count. The proposed quantum bilinear interpolation circuits for the scale down operation and for the scale up operation each have a 92.52% improvement in terms of T-count compared to the existing work.","PeriodicalId":388554,"journal":{"name":"2018 Ninth International Green and Sustainable Computing Conference (IGSC)","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2018-09-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130928046","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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