This paper shows that cascade circuits in the logic cells of all current lookup table based FPGAs support only linear cascading chain and, as a result, contribute to long cascading delay. We present an enhanced cascade circuit that will reduce cascading delay significantly: from linear time to log time in terms of the number of logic cells cascaded. We show that the additional area for the new cascade circuit is very small. We discuss an interaction between architecture design decision and CAD (in particular, placement) for the design of dedicated routing structure for cascade signals between logic cells. We illustrate the advantage of the new cascade circuit with an example of 32-bit equality checking circuit.
{"title":"Revisiting the Cascade Circuit in Logic Cells of Lookup Table Based FPGAs","authors":"N. Woo","doi":"10.1145/201310.201325","DOIUrl":"https://doi.org/10.1145/201310.201325","url":null,"abstract":"This paper shows that cascade circuits in the logic cells of all current lookup table based FPGAs support only linear cascading chain and, as a result, contribute to long cascading delay. We present an enhanced cascade circuit that will reduce cascading delay significantly: from linear time to log time in terms of the number of logic cells cascaded. We show that the additional area for the new cascade circuit is very small. We discuss an interaction between architecture design decision and CAD (in particular, placement) for the design of dedicated routing structure for cascade signals between logic cells. We illustrate the advantage of the new cascade circuit with an example of 32-bit equality checking circuit.","PeriodicalId":396858,"journal":{"name":"Third International ACM Symposium on Field-Programmable Gate Arrays","volume":"13 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129328197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A novel approach is presented for transforming a given scheduled and bound signal processing algorithm for a multiplexer based datapath to a BUS/RAM based FPGA datapath. A datapath model is introduced that allows maximum flexibility in scheduling bus transfers independent of operation scheduling. A novel integer linear programming (ILP) formulation that optimally selects and assigns data-transfers to busses while scheduling the bus transfers to minimize a linear combination of the number of busses, bus loading in terms of tristate drivers and fanout, registers and register file storage (RAM) locations. We demonstrate that our resulting optimal datapaths compare favorably to others for signal processing synthesis benchmarks such as: single and multiple elliptic filter and fast discrete-cosine-transform (FDCT).
{"title":"Synthesis of Signal Processing Structured Datapaths for FPGAs Supporting RAMs and Busses","authors":"B. Haroun, B. Sajjadi","doi":"10.1145/201310.201323","DOIUrl":"https://doi.org/10.1145/201310.201323","url":null,"abstract":"A novel approach is presented for transforming a given scheduled and bound signal processing algorithm for a multiplexer based datapath to a BUS/RAM based FPGA datapath. A datapath model is introduced that allows maximum flexibility in scheduling bus transfers independent of operation scheduling. A novel integer linear programming (ILP) formulation that optimally selects and assigns data-transfers to busses while scheduling the bus transfers to minimize a linear combination of the number of busses, bus loading in terms of tristate drivers and fanout, registers and register file storage (RAM) locations. We demonstrate that our resulting optimal datapaths compare favorably to others for signal processing synthesis benchmarks such as: single and multiple elliptic filter and fast discrete-cosine-transform (FDCT).","PeriodicalId":396858,"journal":{"name":"Third International ACM Symposium on Field-Programmable Gate Arrays","volume":"184 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132317953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Routing FPGAs is a challenging problem because of the relative scarcity of routing resources, both wires and connection points. This can lead either to slow implementations caused by long wiring paths that avoid congestion or a failure to route all signals. This paper presents PathFinder, a router that balances the goals of performance and routability. PathFinder uses an iterative algorithm that converges to a solution in which all signals are routed while achieving close to the optimal performance allowed by the placement. Routability is achieved by forcing signals to negotiate for a resource and thereby determine which signal needs the resource most. Delay is minimized by allowing the more critical signals a greater say in this negotiation. Because PathFinder requires only a directed graph to describe the architecture of routing resources, it adapts readily to a wide variety of FPGA architectures such as Triptych, Xilinx 3000 and mesh-connected arrays of FPGAs. The results of routing ISCAS benchmarks on the Triptych FPGA architecture show an average increase of only 4.5% in critical path delay over the optimum delay for a placement. Routes of ISCAS benchmarks on the Xilinx 3000 architecture show a greater completion rate than commercial tools, as well as 11% faster implementations.
{"title":"PathFinder: A Negotiation-Based Performance-Driven Router for FPGAs","authors":"L. McMurchie, C. Ebeling","doi":"10.1145/201310.201328","DOIUrl":"https://doi.org/10.1145/201310.201328","url":null,"abstract":"Routing FPGAs is a challenging problem because of the relative scarcity of routing resources, both wires and connection points. This can lead either to slow implementations caused by long wiring paths that avoid congestion or a failure to route all signals. This paper presents PathFinder, a router that balances the goals of performance and routability. PathFinder uses an iterative algorithm that converges to a solution in which all signals are routed while achieving close to the optimal performance allowed by the placement. Routability is achieved by forcing signals to negotiate for a resource and thereby determine which signal needs the resource most. Delay is minimized by allowing the more critical signals a greater say in this negotiation. Because PathFinder requires only a directed graph to describe the architecture of routing resources, it adapts readily to a wide variety of FPGA architectures such as Triptych, Xilinx 3000 and mesh-connected arrays of FPGAs. The results of routing ISCAS benchmarks on the Triptych FPGA architecture show an average increase of only 4.5% in critical path delay over the optimum delay for a placement. Routes of ISCAS benchmarks on the Xilinx 3000 architecture show a greater completion rate than commercial tools, as well as 11% faster implementations.","PeriodicalId":396858,"journal":{"name":"Third International ACM Symposium on Field-Programmable Gate Arrays","volume":"247 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133068987","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
As the capacities of FPGAs grow, it becomes feasible to implement the memory portions of systems directly on an FPGA together with logic. We believe that such an FPGA must contain specialized architectural support in order to implement memories efficiently. The key feature of such architectural support is that it must be exible enough to accommodate many different memory shapes (widths and depths) as well as allowing different numbers of independently-addressed memory blocks. This paper describes a family of centralized Field-Configurable Memory architectures which consist of a number of memory arrays and dedicated mapping blocks to combine these arrays. We also present a method for comparing these architectures, and use this method to examine the tradeoffs involved in choosing the array size and mapping block capabilities.
{"title":"Architecture of Centralized Field-Configurable Memory","authors":"S. Wilton, Jonathan Rose, Z. Vranesic","doi":"10.1145/201310.201326","DOIUrl":"https://doi.org/10.1145/201310.201326","url":null,"abstract":"As the capacities of FPGAs grow, it becomes feasible to implement the memory portions of systems directly on an FPGA together with logic. We believe that such an FPGA must contain specialized architectural support in order to implement memories efficiently. The key feature of such architectural support is that it must be exible enough to accommodate many different memory shapes (widths and depths) as well as allowing different numbers of independently-addressed memory blocks. This paper describes a family of centralized Field-Configurable Memory architectures which consist of a number of memory arrays and dedicated mapping blocks to combine these arrays. We also present a method for comparing these architectures, and use this method to examine the tradeoffs involved in choosing the array size and mapping block capabilities.","PeriodicalId":396858,"journal":{"name":"Third International ACM Symposium on Field-Programmable Gate Arrays","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129648020","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Area-IO provide a way to eliminate the IO bottleneck of field programmable logic devices (FPLDs) created the mismatch between the ability of perimeter bonds to provide IO and and the propensity of logic to demand it. Whether the incorporation of area IO into FPLD architectures has undesirable side effects is a question that has not yet been answered. In this paper, we examine the architectural impact of area-IO on FPLDs from a theoretical and experimental standpoint and show that the introduction of area IO generally improves the routability and delay of a set of benchmark circuits.
{"title":"Design of FPGAs with Area I/O for Field Programmable MCM","authors":"V. Maheshwari, J. Darnauer, J. Ramirez, W. Dai","doi":"10.1145/201310.201313","DOIUrl":"https://doi.org/10.1145/201310.201313","url":null,"abstract":"Area-IO provide a way to eliminate the IO bottleneck of field programmable logic devices (FPLDs) created the mismatch between the ability of perimeter bonds to provide IO and and the propensity of logic to demand it. Whether the incorporation of area IO into FPLD architectures has undesirable side effects is a question that has not yet been answered. In this paper, we examine the architectural impact of area-IO on FPLDs from a theoretical and experimental standpoint and show that the introduction of area IO generally improves the routability and delay of a set of benchmark circuits.","PeriodicalId":396858,"journal":{"name":"Third International ACM Symposium on Field-Programmable Gate Arrays","volume":"4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122177862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
One of the critical issues for multi-FPGA systems is developing software tools for automatically mapping circuits. In this paper we consider one step in this process, partitioning. We describe the task of finding partition orderings, i.e., determining the way in which a circuit should be bipartitioned so as to best map it to a multi-FPGA system. This allows multi-FPGA partitioners to harness standard partitioning techniques. We develop an algorithm for finding partition orderings, which includes a method for increasing parallelism in the process, as well as for including multi-sectioning and multi-way partitioning algorithms. This method is very efficient, and capable of handling most of the current multi-FPGA topologies.
{"title":"Logic Partition Orderings for Multi-FPGA Systems","authors":"S. Hauck, G. Borriello","doi":"10.1145/201310.201315","DOIUrl":"https://doi.org/10.1145/201310.201315","url":null,"abstract":"One of the critical issues for multi-FPGA systems is developing software tools for automatically mapping circuits. In this paper we consider one step in this process, partitioning. We describe the task of finding partition orderings, i.e., determining the way in which a circuit should be bipartitioned so as to best map it to a multi-FPGA system. This allows multi-FPGA partitioners to harness standard partitioning techniques. We develop an algorithm for finding partition orderings, which includes a method for increasing parallelism in the process, as well as for including multi-sectioning and multi-way partitioning algorithms. This method is very efficient, and capable of handling most of the current multi-FPGA topologies.","PeriodicalId":396858,"journal":{"name":"Third International ACM Symposium on Field-Programmable Gate Arrays","volume":"166 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133347225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper presents a methodology for production-time testing of (uncustomized) segmented channel field programmable gate arrays (FPGAs) such as those manufactured by Actel. The principles of this methodology are based on configuring the uncommitted modules (made of sequential and combinational logic circuits) of the FPGA as a set of disjoint one-dimensional arrays similar to iterative logic arrays (ILAs). These arrays can then be tested by establishing appropriate conditions such as constant testability (C-testability). A design approach is proposed. This approach is based on adding a small circuitry (consisting of two transistors) between each pair of uncustomized modules in a row for establishing the ILA configuration as a one-dimensional unilateral array. It also requires the addition of a further primary pin. Features such as number of test vectors and hardware requirements (measured by the number of additional transistors and primary input/output pins) are analyzed; it is shown that the proposed design approach requires a considerably smaller number of test vectors (a reduction of more than two orders of magnitude) and hardware overhead for the testing circuitry (a reduction of 13.6%) than the original FPGA configuration of [Actel Corporation, FPGA Data Book and Design Guide, Sunnyvale]. The proposed approach requires 8+2n_f vectors for testing the uncommitted FPGA of [Actel Corporation, FPGA Data Book and Design Guide, Sunnyvale], where nf is the number of flip-flops (equal to the number of sequential modules for the FPGA of [Actel Corporation, FPGA Data Book and Design Guide, Sunnyvale]) in a row of the FPGA.
本文提出了一种(非定制的)分段通道现场可编程门阵列(fpga)的生产时间测试方法，如Actel制造的fpga。这种方法的原理是基于将FPGA的未提交模块(由顺序和组合逻辑电路组成)配置为一组类似于迭代逻辑阵列(ILAs)的不连接的一维阵列。然后，这些阵列可以通过建立适当的条件进行测试，例如恒定可测试性(c -可测试性)。提出了一种设计方法。这种方法是基于在每对非定制模块之间添加一个小电路(由两个晶体管组成)，以将ILA配置建立为一维单边阵列。它还需要再增加一个主引脚。分析了测试向量的数量和硬件要求(通过额外晶体管和主输入/输出引脚的数量来测量)等特征;结果表明，与Actel Corporation, FPGA Data Book and design Guide, Sunnyvale的原始FPGA配置相比，所提出的设计方法所需的测试向量数量(减少了两个数量级以上)和测试电路的硬件开销(减少了13.6%)要少得多。所提出的方法需要8+2n_f向量来测试[Actel Corporation, FPGA Data Book and Design Guide, Sunnyvale]的未提交FPGA，其中nf是FPGA中一排触发器的数量(等于[Actel Corporation, FPGA Data Book and Design Guide, Sunnyvale]的FPGA的顺序模块数量)。
{"title":"Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays","authors":"Tong Liu, Wei-Kang Huang, F. Lombardi","doi":"10.1145/201310.201330","DOIUrl":"https://doi.org/10.1145/201310.201330","url":null,"abstract":"This paper presents a methodology for production-time testing of (uncustomized) segmented channel field programmable gate arrays (FPGAs) such as those manufactured by Actel. The principles of this methodology are based on configuring the uncommitted modules (made of sequential and combinational logic circuits) of the FPGA as a set of disjoint one-dimensional arrays similar to iterative logic arrays (ILAs). These arrays can then be tested by establishing appropriate conditions such as constant testability (C-testability). A design approach is proposed. This approach is based on adding a small circuitry (consisting of two transistors) between each pair of uncustomized modules in a row for establishing the ILA configuration as a one-dimensional unilateral array. It also requires the addition of a further primary pin. Features such as number of test vectors and hardware requirements (measured by the number of additional transistors and primary input/output pins) are analyzed; it is shown that the proposed design approach requires a considerably smaller number of test vectors (a reduction of more than two orders of magnitude) and hardware overhead for the testing circuitry (a reduction of 13.6%) than the original FPGA configuration of [Actel Corporation, FPGA Data Book and Design Guide, Sunnyvale]. The proposed approach requires 8+2n_f vectors for testing the uncommitted FPGA of [Actel Corporation, FPGA Data Book and Design Guide, Sunnyvale], where nf is the number of flip-flops (equal to the number of sequential modules for the FPGA of [Actel Corporation, FPGA Data Book and Design Guide, Sunnyvale]) in a row of the FPGA.","PeriodicalId":396858,"journal":{"name":"Third International ACM Symposium on Field-Programmable Gate Arrays","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116800372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
During the development of computer peripherals which interface to the processor via the system bus it is often necessary to acquire the signals on the bus at the hardware level. It is difficult to attach general-purpose logic analysers and in-circuit emulators to a multiple pin bus connector and hence it is not practical to catch all the bus data required to ensure that such signals are in accordance with the bus specification. Hence a given connector specific bus monitor board is a necessary instrument to attach to the system motherboard in order to monitor all bus activities. A connector specific bus monitor board provides an efficient resource with which to study the internal philosophy of system software, the software implementation process for different communication layers, and to provide debugging for hardware developers. The bus monitor board described here is designed to attach to a SUN SBus and is similar to the Transformable Computer, which appeared recently, in that its architecture is reconfigurable via the use of a Field Programmable Gate Array (FPGA). It can be programmed to customise it to various users' specific needs. It differs from the Transformable Computer in that although it can be programmed to function as a coprocessor its primary function is dedicated SBus Monitoring. It is less costly than a Transformable Computer. In this article we describe the prototype of an SBus monitor's architecture and functions, and present the experimental results obtained from a Sun SPARC work station and an Aurora SBox Expansion Chassis, which demonstrate its ability to capture and display data communication and bus activity. Since this prototype board is programmable, it has the potential to provide many special purpose SBus monitors, but also function as a programmable coprocessor.
{"title":"An SBus Monitor Board","authors":"H. A. Xie, K. Forward, K. M. Adams, D. Leask","doi":"10.1145/201310.201335","DOIUrl":"https://doi.org/10.1145/201310.201335","url":null,"abstract":"During the development of computer peripherals which interface to the processor via the system bus it is often necessary to acquire the signals on the bus at the hardware level. It is difficult to attach general-purpose logic analysers and in-circuit emulators to a multiple pin bus connector and hence it is not practical to catch all the bus data required to ensure that such signals are in accordance with the bus specification. Hence a given connector specific bus monitor board is a necessary instrument to attach to the system motherboard in order to monitor all bus activities. A connector specific bus monitor board provides an efficient resource with which to study the internal philosophy of system software, the software implementation process for different communication layers, and to provide debugging for hardware developers. The bus monitor board described here is designed to attach to a SUN SBus and is similar to the Transformable Computer, which appeared recently, in that its architecture is reconfigurable via the use of a Field Programmable Gate Array (FPGA). It can be programmed to customise it to various users' specific needs. It differs from the Transformable Computer in that although it can be programmed to function as a coprocessor its primary function is dedicated SBus Monitoring. It is less costly than a Transformable Computer. In this article we describe the prototype of an SBus monitor's architecture and functions, and present the experimental results obtained from a Sun SPARC work station and an Aurora SBox Expansion Chassis, which demonstrate its ability to capture and display data communication and bus activity. Since this prototype board is programmable, it has the potential to provide many special purpose SBus monitors, but also function as a programmable coprocessor.","PeriodicalId":396858,"journal":{"name":"Third International ACM Symposium on Field-Programmable Gate Arrays","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129271679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we give a method to design FPGA logic modules, based on an extension of classical work on designing Universal Logic Modules (ULM). Specifically, we give a technique to design a class of logic modules that specialize to a large number of functions under complementations and permutations of inputs, bridging of inputs and assignment of 0/1 to inputs. Thus, a lot of functions can be implemented using a single logic module. The significance of our work lies in our ability to generate a large set of such logic modules. A choice can be made from this set based on design criteria. We demonstrate the technique by generating a set of 471 8-input functions that have a much higher coverage than the 8-input cells employed by Actel's FPGAs. Our functions can specialize to up to 23 times the number of functions that Actel functions can. We also show that by carefully optimizing these functions one can obtain multi-level implementations of them that have delays within 10% of the delays of Actel modules. We demonstrate the effectiveness of these modules in mapping benchmark circuits. We observed a 16% reduction in area and a 21% reduction in delay using our logic modules instead of Actel's on these circuits.
{"title":"On Designing ULM-Based FPGA Logic Modules","authors":"Shashidhar Thakur, D. F. Wong","doi":"10.1145/201310.201311","DOIUrl":"https://doi.org/10.1145/201310.201311","url":null,"abstract":"In this paper, we give a method to design FPGA logic modules, based on an extension of classical work on designing Universal Logic Modules (ULM). Specifically, we give a technique to design a class of logic modules that specialize to a large number of functions under complementations and permutations of inputs, bridging of inputs and assignment of 0/1 to inputs. Thus, a lot of functions can be implemented using a single logic module. The significance of our work lies in our ability to generate a large set of such logic modules. A choice can be made from this set based on design criteria. We demonstrate the technique by generating a set of 471 8-input functions that have a much higher coverage than the 8-input cells employed by Actel's FPGAs. Our functions can specialize to up to 23 times the number of functions that Actel functions can. We also show that by carefully optimizing these functions one can obtain multi-level implementations of them that have delays within 10% of the delays of Actel modules. We demonstrate the effectiveness of these modules in mapping benchmark circuits. We observed a 16% reduction in area and a 21% reduction in delay using our logic modules instead of Actel's on these circuits.","PeriodicalId":396858,"journal":{"name":"Third International ACM Symposium on Field-Programmable Gate Arrays","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129406398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Recent research on FPGA partitioning has focussed on finding minimum cuts between partitions without regard to the routability of the partitioned sub-circuits. In this paper we develop a spectral approach to multi-way partitioning in which the primary goal is to produce routable subcircuits while maximizing FPGA device utilization. To assist the partitioner in assessing the routability of the partitioned subcircuits, we have developed a theory to predict the routability of the partitioned subcircuits prior to partitioning. Advancement over the current work is evidenced by results of experiments on the standard MCNC benchmarks.
{"title":"Spectral-Based Multi-Way FPGA Partitioning","authors":"P. K. Chan, M. Schlag, Jason Y. Zien","doi":"10.1145/201310.201331","DOIUrl":"https://doi.org/10.1145/201310.201331","url":null,"abstract":"Recent research on FPGA partitioning has focussed on finding minimum cuts between partitions without regard to the routability of the partitioned sub-circuits. In this paper we develop a spectral approach to multi-way partitioning in which the primary goal is to produce routable subcircuits while maximizing FPGA device utilization. To assist the partitioner in assessing the routability of the partitioned subcircuits, we have developed a theory to predict the routability of the partitioned subcircuits prior to partitioning. Advancement over the current work is evidenced by results of experiments on the standard MCNC benchmarks.","PeriodicalId":396858,"journal":{"name":"Third International ACM Symposium on Field-Programmable Gate Arrays","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129588653","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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