This paper considers the problem of partitioning a circuit into a collection of subcircuits, such that each subcircuit is feasible for some device from an FPGA library, and the total cost of devices is minimized. We propose a three-phase heuristic that uses ordering, clustering, and dynamic programming to achieve good solutions. Experimental comparisons are made with the previous methods of [Circuit Partitioning for Huge Logic Emulation Systems][Cost Minimization of Partitions into Multiple Devices].
{"title":"Multi-Way System Partitioning into a Single Type or Multiple Types of FPGAs","authors":"D. J. Huang, A. Kahng","doi":"10.1145/201310.201332","DOIUrl":"https://doi.org/10.1145/201310.201332","url":null,"abstract":"This paper considers the problem of partitioning a circuit into a collection of subcircuits, such that each subcircuit is feasible for some device from an FPGA library, and the total cost of devices is minimized. We propose a three-phase heuristic that uses ordering, clustering, and dynamic programming to achieve good solutions. Experimental comparisons are made with the previous methods of [Circuit Partitioning for Huge Logic Emulation Systems][Cost Minimization of Partitions into Multiple Devices].","PeriodicalId":396858,"journal":{"name":"Third International ACM Symposium on Field-Programmable Gate Arrays","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124877959","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The future Large Hadron Collider (LHC) to be built at CERN, by the turn of the millenium, provides an ample source of challenging real-time computational problems. We report here some results from a collaboration between CERN EAST (RD-11) group and DECPRL PAM team. We present the implementations of the three foremost LHC algorithms on DECPeRLe-1. Our machine is the only one which presently meets the requirements from CERN (100 kHz event rate), except for another dedicated FPGA-based board built for just one of the algorithm. All other implementations based on single and multiprocessor general purpose computing systems fall short either of computing power, or of I/O resources or both.
在世纪之交，欧洲核子研究中心将建造未来的大型强子对撞机(LHC)，为具有挑战性的实时计算问题提供了充足的资源。我们在此报告一些CERN EAST (RD-11)小组与DECPRL PAM小组合作的结果。我们提出了在DECPeRLe-1上实现的三种最重要的LHC算法。我们的机器是目前唯一满足CERN (100 kHz事件率)要求的机器，除了为其中一种算法构建的另一个专用基于fpga的板。所有其他基于单处理器和多处理器通用计算系统的实现要么缺乏计算能力，要么缺乏I/O资源，要么两者都缺乏。
{"title":"High-Energy Physics on DECPeRLe-1 Programmable Active Memory","authors":"L. Moll, J. Vuillemin, P. Boucard","doi":"10.1145/201310.201318","DOIUrl":"https://doi.org/10.1145/201310.201318","url":null,"abstract":"The future Large Hadron Collider (LHC) to be built at CERN, by the turn of the millenium, provides an ample source of challenging real-time computational problems. We report here some results from a collaboration between CERN EAST (RD-11) group and DECPRL PAM team. We present the implementations of the three foremost LHC algorithms on DECPeRLe-1. Our machine is the only one which presently meets the requirements from CERN (100 kHz event rate), except for another dedicated FPGA-based board built for just one of the algorithm. All other implementations based on single and multiprocessor general purpose computing systems fall short either of computing power, or of I/O resources or both.","PeriodicalId":396858,"journal":{"name":"Third International ACM Symposium on Field-Programmable Gate Arrays","volume":"42 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-02-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126452940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We study the nominal delay minimization problemin LUT-based FPGA technology mapping, where interconnect delay is assumed proportional to net fanout size. We prove that the delay-optimal K-LUT mapping problem under the nominal delay model is NP-hard when K ≥ 3, and remains NP-hard for duplication-free mapping and tree-based mapping for K ≥ 5 (but is polynomial time solvable for K = 2). We also present a simple heuristic to take nominal delay into consideration during LUT mapping for delay minimization.
{"title":"On Nominal Delay Minimization in LUT-Based FPGA Technology Mapping","authors":"J. Cong, Y. Ding","doi":"10.1145/201310.201324","DOIUrl":"https://doi.org/10.1145/201310.201324","url":null,"abstract":"We study the nominal delay minimization problemin LUT-based FPGA technology mapping, where interconnect delay is assumed proportional to net fanout size. We prove that the delay-optimal K-LUT mapping problem under the nominal delay model is NP-hard when K ≥ 3, and remains NP-hard for duplication-free mapping and tree-based mapping for K ≥ 5 (but is polynomial time solvable for K = 2). We also present a simple heuristic to take nominal delay into consideration during LUT mapping for delay minimization.","PeriodicalId":396858,"journal":{"name":"Third International ACM Symposium on Field-Programmable Gate Arrays","volume":"210 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1994-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123239225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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