Pub Date : 1990-05-21DOI: 10.1109/ISMSS.1990.66125
J.W. Lawton, A. Drake, R. Henderson, L.M. Wein, R. Whitney, D. Zuanich
The workload regulating wafer release policy, that was developed for MWTD's (Hewlett-Packard's Microwave Technology Division) GaAs fabrication facility is described. A discrete-event simulator, ManSim was used to determine its improvements over other wafer release policies, and it was shown that it has the potential to reduce fabrication cycle time by roughly 50%. It is suggested that the plant's historical focus on leading-edge process technology rather than on more traditional measures of manufacturing performance has delayed the recognition of the potential of a policy of this type.<>
{"title":"Workload regulating wafer release in a GaAs fab facility","authors":"J.W. Lawton, A. Drake, R. Henderson, L.M. Wein, R. Whitney, D. Zuanich","doi":"10.1109/ISMSS.1990.66125","DOIUrl":"https://doi.org/10.1109/ISMSS.1990.66125","url":null,"abstract":"The workload regulating wafer release policy, that was developed for MWTD's (Hewlett-Packard's Microwave Technology Division) GaAs fabrication facility is described. A discrete-event simulator, ManSim was used to determine its improvements over other wafer release policies, and it was shown that it has the potential to reduce fabrication cycle time by roughly 50%. It is suggested that the plant's historical focus on leading-edge process technology rather than on more traditional measures of manufacturing performance has delayed the recognition of the potential of a policy of this type.<<ETX>>","PeriodicalId":398535,"journal":{"name":"IEEE/SEMI International Symposium on Semiconductor Manufacturing Science","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131818508","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-21DOI: 10.1109/ISMSS.1990.66120
F. Nadi, A. Agogino, D. Hodges
An adaptive learning architecture has been developed for modeling manufacturing processes involving several controlling variables. Experimental results of applying the new architecture to process modeling and recipe synthesis for LPCVD (low-pressure chemical vapor deposition) of undoped polysilicon are described. Control parameters considered are pressure, temperature, gas-flow rate, wafer position, and time. Models for both deposition rate and final mechanical stress in the film have been developed. By using the generalization ability of neural networks in the synthesis algorithm, this architecture can produce new recipes for the process. Two such recipes have been generated for the LPCVD process. One is a zero-stress polysilicon film receipt; the second is a uniform deposition rate receipt based on the use of a nonuniform temperature distribution during deposition.<>
{"title":"Use of influence diagrams and neural networks in modeling LPCVD","authors":"F. Nadi, A. Agogino, D. Hodges","doi":"10.1109/ISMSS.1990.66120","DOIUrl":"https://doi.org/10.1109/ISMSS.1990.66120","url":null,"abstract":"An adaptive learning architecture has been developed for modeling manufacturing processes involving several controlling variables. Experimental results of applying the new architecture to process modeling and recipe synthesis for LPCVD (low-pressure chemical vapor deposition) of undoped polysilicon are described. Control parameters considered are pressure, temperature, gas-flow rate, wafer position, and time. Models for both deposition rate and final mechanical stress in the film have been developed. By using the generalization ability of neural networks in the synthesis algorithm, this architecture can produce new recipes for the process. Two such recipes have been generated for the LPCVD process. One is a zero-stress polysilicon film receipt; the second is a uniform deposition rate receipt based on the use of a nonuniform temperature distribution during deposition.<<ETX>>","PeriodicalId":398535,"journal":{"name":"IEEE/SEMI International Symposium on Semiconductor Manufacturing Science","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130420663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-21DOI: 10.1109/ISMSS.1990.66128
A. Matsuyama, R. Atherton
The authors describe the extensive base of factory simulation experience in Japan and experiences with the new factory-modeling technology in the US. It is pointed out that factory simulation and performance analysis are valuable for the insights that they provide for obtaining rapid cycle times and the associated business advantages. Experiences in Japan that have highlighted the practical difficulties of applying the traditional techniques of queueing theory and simulation languages to the complexities of real factories are described. By comparison, Nihon Semiconductor's experience with the new factory-modeling technology indicates that it overcomes these traditional difficulties. This modeling technology reduces the risks of undertaking a factory-performance analysis project. The new factory-modeling technology is now being successfully used in the US and Japan. Several examples of performance analysis studies at Nihon Semiconductor are described. A comparison of factory model results with factory operating data resulted in the development of a new characterization of labor efficiency.<>
{"title":"Experience in simulating wafer fabs in the USA and Japan","authors":"A. Matsuyama, R. Atherton","doi":"10.1109/ISMSS.1990.66128","DOIUrl":"https://doi.org/10.1109/ISMSS.1990.66128","url":null,"abstract":"The authors describe the extensive base of factory simulation experience in Japan and experiences with the new factory-modeling technology in the US. It is pointed out that factory simulation and performance analysis are valuable for the insights that they provide for obtaining rapid cycle times and the associated business advantages. Experiences in Japan that have highlighted the practical difficulties of applying the traditional techniques of queueing theory and simulation languages to the complexities of real factories are described. By comparison, Nihon Semiconductor's experience with the new factory-modeling technology indicates that it overcomes these traditional difficulties. This modeling technology reduces the risks of undertaking a factory-performance analysis project. The new factory-modeling technology is now being successfully used in the US and Japan. Several examples of performance analysis studies at Nihon Semiconductor are described. A comparison of factory model results with factory operating data resulted in the development of a new characterization of labor efficiency.<<ETX>>","PeriodicalId":398535,"journal":{"name":"IEEE/SEMI International Symposium on Semiconductor Manufacturing Science","volume":"98 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127099174","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-21DOI: 10.1109/ISMSS.1990.66107
W. Matthews
The author describes his point of view-developed from over eight years of visiting Japan and Japanese manufacturing plants, including three years of actually living in Japan-on differences in the decision-making process for manufacturing in Japan and the US. It is pointed out that in the American system everyone has a specific area of responsibility and the plant manager is ultimately responsible when machines break. In the Japanese fab, the person operating the machine is specifically responsible for output and knows how to achieve that output. The machine keeper is responsible for everything on the machine: from routine cleaning and loading of material to sophisticated PMs and tough fix-it issues when machines actually break.<>
{"title":"Functional and operational differences in the decision making process for manufacturing in Japan and in America","authors":"W. Matthews","doi":"10.1109/ISMSS.1990.66107","DOIUrl":"https://doi.org/10.1109/ISMSS.1990.66107","url":null,"abstract":"The author describes his point of view-developed from over eight years of visiting Japan and Japanese manufacturing plants, including three years of actually living in Japan-on differences in the decision-making process for manufacturing in Japan and the US. It is pointed out that in the American system everyone has a specific area of responsibility and the plant manager is ultimately responsible when machines break. In the Japanese fab, the person operating the machine is specifically responsible for output and knows how to achieve that output. The machine keeper is responsible for everything on the machine: from routine cleaning and loading of material to sophisticated PMs and tough fix-it issues when machines actually break.<<ETX>>","PeriodicalId":398535,"journal":{"name":"IEEE/SEMI International Symposium on Semiconductor Manufacturing Science","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132621404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-21DOI: 10.1109/ISMSS.1990.66111
M. Adams, B. Smoak
The authors present the application of manufacturing improvement programs which use computer-integrated methods to track performance and gather data necessary for problem identification. This application focuses on existing wafer fabrication at Harris Semiconductor in Palm Bay, Florida. The authors specifically concentrate on the methodology used to improve key fabrication performance indices, such as throughput yield, cycle time, and performance to schedule. It is shown how CIM (computer-integrated manufacturing) methodology was critical to the improvement process. The specific methodologies discussed are the following: work-in-process management, inventory reduction, activity planning and work scheduling; equipment tracking, preventative-maintenance scheduling, and equipment performance; SPC (statistical process control) implementation and support, data collection, chart limit calculation, capability studies, and online support; and scrap reduction programs. A wafer inventory reduction of over 70% was realized and a product performance to mix of over 50% was realized during a 30 month period. Wafer throughput yield improved by over 30% during the 30 month period.<>
{"title":"Managing manufacturing improvement using computer integrated manufacturing methods","authors":"M. Adams, B. Smoak","doi":"10.1109/ISMSS.1990.66111","DOIUrl":"https://doi.org/10.1109/ISMSS.1990.66111","url":null,"abstract":"The authors present the application of manufacturing improvement programs which use computer-integrated methods to track performance and gather data necessary for problem identification. This application focuses on existing wafer fabrication at Harris Semiconductor in Palm Bay, Florida. The authors specifically concentrate on the methodology used to improve key fabrication performance indices, such as throughput yield, cycle time, and performance to schedule. It is shown how CIM (computer-integrated manufacturing) methodology was critical to the improvement process. The specific methodologies discussed are the following: work-in-process management, inventory reduction, activity planning and work scheduling; equipment tracking, preventative-maintenance scheduling, and equipment performance; SPC (statistical process control) implementation and support, data collection, chart limit calculation, capability studies, and online support; and scrap reduction programs. A wafer inventory reduction of over 70% was realized and a product performance to mix of over 50% was realized during a 30 month period. Wafer throughput yield improved by over 30% during the 30 month period.<<ETX>>","PeriodicalId":398535,"journal":{"name":"IEEE/SEMI International Symposium on Semiconductor Manufacturing Science","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129225183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-21DOI: 10.1109/ISMSS.1990.66127
D. Khera, M. Cresswell, L. W. Linholm, G. Ramanathan, J. Buzzeo, A. Nagarajan
The authors describe a procedure for using induction-based classification techniques for identifying relationships between work-in-process (WIP) test structure data and future IC yield at wafer test on a wafer-by-wafer or lot-by-lot basis. The relationships are extracted from databases of previously processed WIP wafer test structure measurements and final wafer yield. They are presented in the form of rules relating WIP data to final yield. It is further shown that these rules, when incorporated into expert systems, can advise the human operator responsible for screening wafers which are likely to produce submarginal yield if processed to completion. These rules also identify the WIP test structure parameters and values which have historically provided the highest and lowest final wafer yields.<>
{"title":"Knowledge extraction techniques for expert system assisted wafer screening","authors":"D. Khera, M. Cresswell, L. W. Linholm, G. Ramanathan, J. Buzzeo, A. Nagarajan","doi":"10.1109/ISMSS.1990.66127","DOIUrl":"https://doi.org/10.1109/ISMSS.1990.66127","url":null,"abstract":"The authors describe a procedure for using induction-based classification techniques for identifying relationships between work-in-process (WIP) test structure data and future IC yield at wafer test on a wafer-by-wafer or lot-by-lot basis. The relationships are extracted from databases of previously processed WIP wafer test structure measurements and final wafer yield. They are presented in the form of rules relating WIP data to final yield. It is further shown that these rules, when incorporated into expert systems, can advise the human operator responsible for screening wafers which are likely to produce submarginal yield if processed to completion. These rules also identify the WIP test structure parameters and values which have historically provided the highest and lowest final wafer yields.<<ETX>>","PeriodicalId":398535,"journal":{"name":"IEEE/SEMI International Symposium on Semiconductor Manufacturing Science","volume":"276 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115986529","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-21DOI: 10.1109/ISMSS.1990.66115
R. S. Nowicki, C. Fuhs, P. Geraghty
Summary form only given. The authors describe a predeposition clean in which reactive ion etching (RIE) prior to tungsten silicide deposition is used. This technique yields silicide films which can easily withstand postsilicide deposition, high-temperature heat treatment, and wet oxidation without loss of film adhesion or other obvious degradation. The authors also report the extensive use of the secondary ion mass spectrometry (SIMS) microanalytical technique to demonstrate that this procedure has indeed been effective in the removal of the oxide layer prior to silicide deposition. The etch properties for C/sub 2/F/sub 6/ and CF/sub 4/ have been compared.<>
{"title":"Comparison of integrated in situ RIE preclean processes for CVD tungsten silicide deposition done in a cluster tool","authors":"R. S. Nowicki, C. Fuhs, P. Geraghty","doi":"10.1109/ISMSS.1990.66115","DOIUrl":"https://doi.org/10.1109/ISMSS.1990.66115","url":null,"abstract":"Summary form only given. The authors describe a predeposition clean in which reactive ion etching (RIE) prior to tungsten silicide deposition is used. This technique yields silicide films which can easily withstand postsilicide deposition, high-temperature heat treatment, and wet oxidation without loss of film adhesion or other obvious degradation. The authors also report the extensive use of the secondary ion mass spectrometry (SIMS) microanalytical technique to demonstrate that this procedure has indeed been effective in the removal of the oxide layer prior to silicide deposition. The etch properties for C/sub 2/F/sub 6/ and CF/sub 4/ have been compared.<<ETX>>","PeriodicalId":398535,"journal":{"name":"IEEE/SEMI International Symposium on Semiconductor Manufacturing Science","volume":"109 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117192183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-21DOI: 10.1109/ISMSS.1990.66119
L. Liu, G.H. Liu
A DFM (design for manufacturability) method that applies artificial intelligence techniques and robust design ideas and can be used in many semiconductor design and manufacturing areas is described. The method includes both controllable design and uncontrollable variation factors early in the design stage. It uses neural network computing techniques to find an optimal design for controllable design factors of maximizing the yield of the semiconductor product design and manufacturing process. The controllable design factors include the device component values, device physical variables, and fabrication parameters such as deposition time, rate, and doses. The uncontrollable factors are environmental condition variations such as temperature and humidity, as well as fabrication inaccuracies in alignment and diffusion. The method consists of sample, relate, and optimize (SR) stages. At the sample stage, a set of confined random design points are chosen from an initial design space. At the relate stage, the relationship between these points and their responses are used to train an artificial neural network (NN) based on a backpropagation model. At the optimize stage, acceptable inputs can be predicted and therefore the manufacturing yield increased by using this NN computational scheme. This method, when applied to a semiconductor processing-dependent IC design example, showed satisfactory results.<>
{"title":"Neural network computing applied in design for manufacturability","authors":"L. Liu, G.H. Liu","doi":"10.1109/ISMSS.1990.66119","DOIUrl":"https://doi.org/10.1109/ISMSS.1990.66119","url":null,"abstract":"A DFM (design for manufacturability) method that applies artificial intelligence techniques and robust design ideas and can be used in many semiconductor design and manufacturing areas is described. The method includes both controllable design and uncontrollable variation factors early in the design stage. It uses neural network computing techniques to find an optimal design for controllable design factors of maximizing the yield of the semiconductor product design and manufacturing process. The controllable design factors include the device component values, device physical variables, and fabrication parameters such as deposition time, rate, and doses. The uncontrollable factors are environmental condition variations such as temperature and humidity, as well as fabrication inaccuracies in alignment and diffusion. The method consists of sample, relate, and optimize (SR) stages. At the sample stage, a set of confined random design points are chosen from an initial design space. At the relate stage, the relationship between these points and their responses are used to train an artificial neural network (NN) based on a backpropagation model. At the optimize stage, acceptable inputs can be predicted and therefore the manufacturing yield increased by using this NN computational scheme. This method, when applied to a semiconductor processing-dependent IC design example, showed satisfactory results.<<ETX>>","PeriodicalId":398535,"journal":{"name":"IEEE/SEMI International Symposium on Semiconductor Manufacturing Science","volume":"151 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122448368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-21DOI: 10.1109/ISMSS.1990.66105
J. Ghiselli, B. Rathbun
The 'Generic Equipment Model for SECS Communications (GEM)' (1988) proposed methodology for implementing SECS communication links on equipment, and suggests that equipment supporting the methodology could significantly reduce total factory automation costs. Previously, in the absence of any actual implementations of GEM, the benefits remained theoretical, and feasibility and cost remained unknown. The authors describe a software implementation of the GEM methodology, and its actual application on equipment. Some valuable practical lessons have been learned about applying generic host communication software on equipment, and about the GEM methodology.<>
{"title":"Practical aspects of the GEM model for factory automation","authors":"J. Ghiselli, B. Rathbun","doi":"10.1109/ISMSS.1990.66105","DOIUrl":"https://doi.org/10.1109/ISMSS.1990.66105","url":null,"abstract":"The 'Generic Equipment Model for SECS Communications (GEM)' (1988) proposed methodology for implementing SECS communication links on equipment, and suggests that equipment supporting the methodology could significantly reduce total factory automation costs. Previously, in the absence of any actual implementations of GEM, the benefits remained theoretical, and feasibility and cost remained unknown. The authors describe a software implementation of the GEM methodology, and its actual application on equipment. Some valuable practical lessons have been learned about applying generic host communication software on equipment, and about the GEM methodology.<<ETX>>","PeriodicalId":398535,"journal":{"name":"IEEE/SEMI International Symposium on Semiconductor Manufacturing Science","volume":"47 2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126048740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1990-05-21DOI: 10.1109/ISMSS.1990.66116
E. Sachs, S. Ha, A. Hu, W. Metz
As part of a system for process control, the run by run controller implements a form of adaptive control based on the sequential design of experiments. The run by run controller can be applied to the local optimization, feedback control, and feedforward control or processes in which multiple inputs control multiple output characteristics. Current work concerns the application of the controller to the optimization and control of thickness and resistivity uniformity of silicon epitaxy. Initial experiments to investigate the effect of noise and disturbances on an AME 7800 barrel reactor indicate that the system is a good candidate for modeling and control using the multiple response surface method, wherein each measured site is separately modeled with a response surface and the uniformity metric is calculated from these models.<>
{"title":"Automated on-line optimization of an epitaxial process","authors":"E. Sachs, S. Ha, A. Hu, W. Metz","doi":"10.1109/ISMSS.1990.66116","DOIUrl":"https://doi.org/10.1109/ISMSS.1990.66116","url":null,"abstract":"As part of a system for process control, the run by run controller implements a form of adaptive control based on the sequential design of experiments. The run by run controller can be applied to the local optimization, feedback control, and feedforward control or processes in which multiple inputs control multiple output characteristics. Current work concerns the application of the controller to the optimization and control of thickness and resistivity uniformity of silicon epitaxy. Initial experiments to investigate the effect of noise and disturbances on an AME 7800 barrel reactor indicate that the system is a good candidate for modeling and control using the multiple response surface method, wherein each measured site is separately modeled with a response surface and the uniformity metric is calculated from these models.<<ETX>>","PeriodicalId":398535,"journal":{"name":"IEEE/SEMI International Symposium on Semiconductor Manufacturing Science","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1990-05-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115506249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：