A. Gerstlauer, J. Peng, Dongwan Shin, D. Gajski, Atsushi Nakamura, Dai Araki, Yuuji Nishihara
Driven by increasing complexity and reliability demands, the Japanese Aerospace Exploration Agency (JAXA) in 2004 commissioned development of ELEGANT, a complete SpecC-based environment for electronic system-level (ESL) design of space and satellite electronics. As integral part of ELEGANT, the Center for Embedded Computer System (CECS) has developed and supplied the SER tool set. Following a Specify-Explore-Refine methodology, SER supports system-level design space exploration, interactive platform development and automatic model refinement and model generation. The SER engine has been successfully integrated into ELEGANT. With SER at its core, ELEGANT provides a seamless tool chain for modeling verification and synthesis from top-level specification down to embedded HW/SW implementation. ELEGANT and SER have been successfully delivered to JAXA and its suppliers. Tools are currently being deployed in companies like NEC Toshiba Space Systems. Evaluation results prove the feasibility of the approach for design space exploration, rapid virtual prototyping and system synthesis resulting in tremendous productivity and reliability gains. In addition, ELEGANT has been commercialized for general market availability. The SER component has been licensed to InterDesign Technologies, Inc. (IDT) and it is available from, sold and supported by IDT.
受日益增加的复杂性和可靠性需求的驱动，日本宇宙航空研究开发机构(JAXA)于2004年委托开发了ELEGANT，这是一个完整的基于规范的环境，用于空间和卫星电子系统级(ESL)设计。作为ELEGANT的组成部分，嵌入式计算机系统中心(CECS)开发并提供了SER工具集。按照“指定-探索-改进”的方法，SER支持系统级设计空间探索、交互平台开发以及自动模型改进和模型生成。SER引擎已成功集成到ELEGANT中。以SER为核心，ELEGANT提供了一个无缝的工具链，用于从顶级规范到嵌入式硬件/软件实现的建模验证和综合。ELEGANT和SER已成功交付给JAXA及其供应商。目前，NEC东芝空间系统等公司正在部署这些工具。评估结果证明了该方法在设计空间探索、快速虚拟样机和系统综合方面的可行性，从而大大提高了生产效率和可靠性。此外，ELEGANT已经商业化，可以在一般市场上使用。SER组件已被授权给InterDesign Technologies, Inc. (IDT)，并由IDT提供、销售和支持。
{"title":"Specify-Explore-Refine (SER): From specification to implementation","authors":"A. Gerstlauer, J. Peng, Dongwan Shin, D. Gajski, Atsushi Nakamura, Dai Araki, Yuuji Nishihara","doi":"10.1145/1391469.1391617","DOIUrl":"https://doi.org/10.1145/1391469.1391617","url":null,"abstract":"Driven by increasing complexity and reliability demands, the Japanese Aerospace Exploration Agency (JAXA) in 2004 commissioned development of ELEGANT, a complete SpecC-based environment for electronic system-level (ESL) design of space and satellite electronics. As integral part of ELEGANT, the Center for Embedded Computer System (CECS) has developed and supplied the SER tool set. Following a Specify-Explore-Refine methodology, SER supports system-level design space exploration, interactive platform development and automatic model refinement and model generation. The SER engine has been successfully integrated into ELEGANT. With SER at its core, ELEGANT provides a seamless tool chain for modeling verification and synthesis from top-level specification down to embedded HW/SW implementation. ELEGANT and SER have been successfully delivered to JAXA and its suppliers. Tools are currently being deployed in companies like NEC Toshiba Space Systems. Evaluation results prove the feasibility of the approach for design space exploration, rapid virtual prototyping and system synthesis resulting in tremendous productivity and reliability gains. In addition, ELEGANT has been commercialized for general market availability. The SER component has been licensed to InterDesign Technologies, Inc. (IDT) and it is available from, sold and supported by IDT.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132551938","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we develop a generalized automated design methodology for tunable impedance matching networks in reconfigurable wireless systems. The method simultaneously determines the fixed and tunable/switchable circuit element values in an arbitrary-order canonical filter for a general set of performance constraints over a discrete or continuous set of operating frequencies and source/load impedances. To solve the filter design problem, we combine deterministic nonlinear constrained optimization using Sequential Quadratic Programming with a systematic constraint relaxation approach to facilitate convergence. Using the proposed methodology, we successfully generate three different reconfigurable impedance matching networks with performance requirements that would be difficult to realize using manual design techniques.
{"title":"Automated design of tunable impedance matching networks for reconfigurable wireless applications","authors":"A. Nieuwoudt, J. Kawa, Y. Massoud","doi":"10.1145/1391469.1391596","DOIUrl":"https://doi.org/10.1145/1391469.1391596","url":null,"abstract":"In this paper, we develop a generalized automated design methodology for tunable impedance matching networks in reconfigurable wireless systems. The method simultaneously determines the fixed and tunable/switchable circuit element values in an arbitrary-order canonical filter for a general set of performance constraints over a discrete or continuous set of operating frequencies and source/load impedances. To solve the filter design problem, we combine deterministic nonlinear constrained optimization using Sequential Quadratic Programming with a systematic constraint relaxation approach to facilitate convergence. Using the proposed methodology, we successfully generate three different reconfigurable impedance matching networks with performance requirements that would be difficult to realize using manual design techniques.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"60 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133334764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions under which the transition of a register may be safely blocked can either be explicitly specified by the designer or detected automatically. We introduce a new method for automatically synthesizing these conditions in a way that minimizes netlist perturbation and is both timing- and physical-aware. Our automatic method is also scalable, utilizing simulation and satisfiability tests and necessitating no symbolic representation. On a set of benchmarks, our technique successfully reduces the dynamic clock power by 14.5% on average. Furthermore, we demonstrate how to apply a straightforward logic simplification to utilize resulting don't cares and reduce the logic by 7.0% on average.
{"title":"Automatic synthesis of clock gating logic with controlled netlist perturbation","authors":"A. Hurst","doi":"10.1145/1391469.1391637","DOIUrl":"https://doi.org/10.1145/1391469.1391637","url":null,"abstract":"Clock gating is the insertion of combinational logic along the clock path to prevent the unnecessary switching of registers and reduce dynamic power consumption. The conditions under which the transition of a register may be safely blocked can either be explicitly specified by the designer or detected automatically. We introduce a new method for automatically synthesizing these conditions in a way that minimizes netlist perturbation and is both timing- and physical-aware. Our automatic method is also scalable, utilizing simulation and satisfiability tests and necessitating no symbolic representation. On a set of benchmarks, our technique successfully reduces the dynamic clock power by 14.5% on average. Furthermore, we demonstrate how to apply a straightforward logic simplification to utilize resulting don't cares and reduce the logic by 7.0% on average.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116209852","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Boolean function bi-decomposition is a fundamental operation in logic synthesis. A function f(X) is bi-decomposable under a variable partition XA, XB, XC on X if it can be written as h(fA(XA, XC), fB(XB, XC)) for some functions h, Ja, and /#. The quality of a bi-decomposition is mainly determined by its variable partition. A preferred decomposition is disjoint, i.e. XC = Oslash, and balanced, i.e. |XA| ap |XB|. Finding such a good decomposition reduces communication and circuit complexity, and yields simple physical design solutions. Prior BDD-based methods may not be scalable to decompose large functions due to the memory explosion problem. Also as decomposability is checked under a fixed variable partition, searching a good or feasible partition may run through costly enumeration that requires separate and independent decomposability checkings. This paper proposes a solution to these difficulties using interpolation and incremental SAT solving. Preliminary experimental results show that the capacity of bi-decomposition can be scaled up substantially to handle large designs.
{"title":"Bi-decomposing large Boolean functions via interpolation and satisfiability solving","authors":"Ruei-Rung Lee, J. H. Jiang, W. Hung","doi":"10.1145/1391469.1391634","DOIUrl":"https://doi.org/10.1145/1391469.1391634","url":null,"abstract":"Boolean function bi-decomposition is a fundamental operation in logic synthesis. A function f(X) is bi-decomposable under a variable partition X<sub>A</sub>, X<sub>B</sub>, X<sub>C</sub> on X if it can be written as h(f<sub>A</sub>(X<sub>A</sub>, X<sub>C</sub>), f<sub>B</sub>(X<sub>B</sub>, X<sub>C</sub>)) for some functions h, Ja, and /#. The quality of a bi-decomposition is mainly determined by its variable partition. A preferred decomposition is disjoint, i.e. X<sub>C</sub> = Oslash, and balanced, i.e. |X<sub>A</sub>| ap |X<sub>B</sub>|. Finding such a good decomposition reduces communication and circuit complexity, and yields simple physical design solutions. Prior BDD-based methods may not be scalable to decompose large functions due to the memory explosion problem. Also as decomposability is checked under a fixed variable partition, searching a good or feasible partition may run through costly enumeration that requires separate and independent decomposability checkings. This paper proposes a solution to these difficulties using interpolation and incremental SAT solving. Preliminary experimental results show that the capacity of bi-decomposition can be scaled up substantially to handle large designs.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116580690","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We propose a new resynthesis algorithm for FPGA area reduction. In contrast to existing resynthesis techniques, which consider only single-output Boolean functions and the combinational portion of a circuit, we consider multi-output functions and retiming, and develop effective algorithms that incorporate recent improvements to SAT-based Boolean matching. Our experimental results show that with the optimal logic depth, the resynthesis considering multi-output functions reduces area by up to 0.4% compared to the one considering single-output functions, and the sequential resynthesis reduces area by up to 10% compared to combinational resynthesis when both consider multi-output functions. Furthermore, our proposed resynthesis algorithm reduces area by up to 16% compared to the best existing academic technology mapper, Berrylikei ABC.
{"title":"FPGA area reduction by multi-output function based sequential resynthesis","authors":"Yu Hu, Victor Shih, R. Majumdar, Lei He","doi":"10.1145/1391469.1391478","DOIUrl":"https://doi.org/10.1145/1391469.1391478","url":null,"abstract":"We propose a new resynthesis algorithm for FPGA area reduction. In contrast to existing resynthesis techniques, which consider only single-output Boolean functions and the combinational portion of a circuit, we consider multi-output functions and retiming, and develop effective algorithms that incorporate recent improvements to SAT-based Boolean matching. Our experimental results show that with the optimal logic depth, the resynthesis considering multi-output functions reduces area by up to 0.4% compared to the one considering single-output functions, and the sequential resynthesis reduces area by up to 10% compared to combinational resynthesis when both consider multi-output functions. Furthermore, our proposed resynthesis algorithm reduces area by up to 16% compared to the best existing academic technology mapper, Berrylikei ABC.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"131 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114661404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In modern day digital design flow, high-level models written in C and C++ serve multiple purposes, one of which is to aid verification of register-transfer level (RTL) hardware models. These high-level models, also called system-level models (SLMs), act as reference models for hardware designs created at the RTL level. They define the correct behavior for the RTL hardware design under verification. Written in a programming language (or similar) and therefore executable, they are used extensively in both simulation-based verification and formal equivalence checking. This paper presents how SLMs fit into the different RTL verification schemes and the challenges involved in the various verification flows. Input stimulus generation based on formal verification technology is introduced as a new way to improve simulation coverage. This paper also covers other techniques engineers use to meet various challenges encountered in RTL verification.
{"title":"Challenges in using system-level models for RTL verification","authors":"Kelvin Ng","doi":"10.1145/1391469.1391676","DOIUrl":"https://doi.org/10.1145/1391469.1391676","url":null,"abstract":"In modern day digital design flow, high-level models written in C and C++ serve multiple purposes, one of which is to aid verification of register-transfer level (RTL) hardware models. These high-level models, also called system-level models (SLMs), act as reference models for hardware designs created at the RTL level. They define the correct behavior for the RTL hardware design under verification. Written in a programming language (or similar) and therefore executable, they are used extensively in both simulation-based verification and formal equivalence checking. This paper presents how SLMs fit into the different RTL verification schemes and the challenges involved in the various verification flows. Input stimulus generation based on formal verification technology is introduced as a new way to improve simulation coverage. This paper also covers other techniques engineers use to meet various challenges encountered in RTL verification.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121982129","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we present a generalized network flow based algorithm for power-aware FPGA memory mapping. Our algorithm not only maps user-defined logical memories to physical embedded memory blocks under the memory resource constraint but also achieves minimum power consumption. The experimental results show that our algorithm was always able to efficiently generate optimal solutions for all test cases while an existing greedy method could do so only for about one third of the test cases.
{"title":"A generalized network flow based algorithm for power-aware FPGA memory mapping","authors":"Tien-Yuan Hsu, Ting-Chi Wang","doi":"10.1145/1391469.1391479","DOIUrl":"https://doi.org/10.1145/1391469.1391479","url":null,"abstract":"In this paper, we present a generalized network flow based algorithm for power-aware FPGA memory mapping. Our algorithm not only maps user-defined logical memories to physical embedded memory blocks under the memory resource constraint but also achieves minimum power consumption. The experimental results show that our algorithm was always able to efficiently generate optimal solutions for all test cases while an existing greedy method could do so only for about one third of the test cases.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121412369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We propose the use of functional magnetic resonance imaging (fMRI) systems, techniques, and tools to observe the neuron-level activity of the brains of designers or CAD tool developers. The objective is to enable designers and developers to complete their task in a faster and more creative way with significantly reduced number of logical and design errors. While fMRI techniques are already used in economics, decision and several other social sciences, until now their potential for closing the design productivity-silicon productivity (DPSP) gap has not been recognized. By compounding the new approach with techniques for designing integrated circuits and system within fMRI data collection and analysis, we will establish a positive productivity and creativity feedback loop that may permanently close the DPSP gap. As a preliminary and presently feasible step, we propose the creation of behavioral CAD research and development techniques. The usage of judiciously selected verbal, visual information and reintroduction of successful design paradigm and exposure to beneficial synthesis templates may help current and future designers to learn and design more effectively.
{"title":"(Bio)-Behavioral CAD","authors":"M. Potkonjak, F. Koushanfar","doi":"10.1145/1391469.1391562","DOIUrl":"https://doi.org/10.1145/1391469.1391562","url":null,"abstract":"We propose the use of functional magnetic resonance imaging (fMRI) systems, techniques, and tools to observe the neuron-level activity of the brains of designers or CAD tool developers. The objective is to enable designers and developers to complete their task in a faster and more creative way with significantly reduced number of logical and design errors. While fMRI techniques are already used in economics, decision and several other social sciences, until now their potential for closing the design productivity-silicon productivity (DPSP) gap has not been recognized. By compounding the new approach with techniques for designing integrated circuits and system within fMRI data collection and analysis, we will establish a positive productivity and creativity feedback loop that may permanently close the DPSP gap. As a preliminary and presently feasible step, we propose the creation of behavioral CAD research and development techniques. The usage of judiciously selected verbal, visual information and reintroduction of successful design paradigm and exposure to beneficial synthesis templates may help current and future designers to learn and design more effectively.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"67 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129891178","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Many recent techniques for timing analysis under variability, in which delay is an explicit function of underlying parameters, may be described as parameterized timing analysis. The "max" operator, used repeatedly during block-based timing analysis, causes several complications during parameterized timing analysis. We introduce bounds on, and an approximation to, the max operator which allow us to develop an accurate, general, and efficient approach to parameterized timing, which can handle either uncertain or random variations. Applied to random variations, the approach is competitive with existing statistical static timing analysis (SSTA) techniques, in that it allows for nonlinear delay models and arbitrary distributions. Applied to uncertain variations, the method is competitive with existing multi-corner STA techniques, in that it more reliably reproduces overall circuit sensitivity to variations. Crucially, this technique can also be applied to the mixed case where both random and uncertain variations are considered. Our results show that, on average, circuit delay is predicted with less than 2% error for multi-corner analysis, and less than 1% error for SSTA.
{"title":"Parameterized timing analysis with general delay models and arbitrary variation sources","authors":"K. R. Heloue, F. Najm","doi":"10.1145/1391469.1391576","DOIUrl":"https://doi.org/10.1145/1391469.1391576","url":null,"abstract":"Many recent techniques for timing analysis under variability, in which delay is an explicit function of underlying parameters, may be described as parameterized timing analysis. The \"max\" operator, used repeatedly during block-based timing analysis, causes several complications during parameterized timing analysis. We introduce bounds on, and an approximation to, the max operator which allow us to develop an accurate, general, and efficient approach to parameterized timing, which can handle either uncertain or random variations. Applied to random variations, the approach is competitive with existing statistical static timing analysis (SSTA) techniques, in that it allows for nonlinear delay models and arbitrary distributions. Applied to uncertain variations, the method is competitive with existing multi-corner STA techniques, in that it more reliably reproduces overall circuit sensitivity to variations. Crucially, this technique can also be applied to the mixed case where both random and uncertain variations are considered. Our results show that, on average, circuit delay is predicted with less than 2% error for multi-corner analysis, and less than 1% error for SSTA.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"226 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130721862","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Formal verification technology has advanced significantly in recent years, yet it seems to have no noticeable acceptance as a mainstream verification methodology within the industry. This paper discusses the issues involved with deploying formal verification on a production mode, and the strategies that may need to be adopted to make this deployment successful. It analyses the real benefits and risks of using formal verification in the overall verification process, and how to integrate this new technology with traditional technologies like simulation. The lessons described in this paper have been learnt from several years of experience with using commercial formal verification tools in industrial projects.
{"title":"Strategies for mainstream usage of formal verification","authors":"Raj S. Mitra","doi":"10.1145/1391469.1391674","DOIUrl":"https://doi.org/10.1145/1391469.1391674","url":null,"abstract":"Formal verification technology has advanced significantly in recent years, yet it seems to have no noticeable acceptance as a mainstream verification methodology within the industry. This paper discusses the issues involved with deploying formal verification on a production mode, and the strategies that may need to be adopted to make this deployment successful. It analyses the real benefits and risks of using formal verification in the overall verification process, and how to integrate this new technology with traditional technologies like simulation. The lessons described in this paper have been learnt from several years of experience with using commercial formal verification tools in industrial projects.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"340 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130380225","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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