The paper presents an infrastructure for debug and trace of the embedded digital signal processor (DSP) system, consisting of the in-system trace interface and its methodology to optimize the compression rate of the program and data traces. The platform has been implemented in a multimedia dual-core SOC design with little area overhead. Both the benchmark evaluation and realistic system integration justified the efficiency and effectiveness of our approach.
{"title":"An embedded infrastructure of debug and trace interface for the DSP platform","authors":"Ming-Chang Hsieh, Chih-Tsun Huang","doi":"10.1145/1391469.1391688","DOIUrl":"https://doi.org/10.1145/1391469.1391688","url":null,"abstract":"The paper presents an infrastructure for debug and trace of the embedded digital signal processor (DSP) system, consisting of the in-system trace interface and its methodology to optimize the compression rate of the program and data traces. The platform has been implemented in a multimedia dual-core SOC design with little area overhead. Both the benchmark evaluation and realistic system integration justified the efficiency and effectiveness of our approach.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134008924","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In deep submicron circuits, thermal hot spots and high temperature gradients increase the cooling costs, and degrade reliability and performance. In this paper, we propose a low-cost temperature management strategy for multicore systems to reduce the adverse effects of hot spots and temperature variations. Our technique utilizes online learning to select the best policy for the current workload characteristics among a given set of expert policies. We achieve 20% and 60% average decrease in the frequency of hot spots and thermal cycles respectively in comparison to the best performing expert, and reduce the spatial gradients to below 5%.
{"title":"Temperature management in multiprocessor SoCs using online learning","authors":"A. Coskun, T. Simunic, K. Gross","doi":"10.1145/1391469.1391693","DOIUrl":"https://doi.org/10.1145/1391469.1391693","url":null,"abstract":"In deep submicron circuits, thermal hot spots and high temperature gradients increase the cooling costs, and degrade reliability and performance. In this paper, we propose a low-cost temperature management strategy for multicore systems to reduce the adverse effects of hot spots and temperature variations. Our technique utilizes online learning to select the best policy for the current workload characteristics among a given set of expert policies. We achieve 20% and 60% average decrease in the frequency of hot spots and thermal cycles respectively in comparison to the best performing expert, and reduce the spatial gradients to below 5%.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131159823","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The objective of IFRA, instruction footprint recording and analysis, is to overcome the challenges associated with a very expensive step in post-silicon validation of processors - bug localization in a system setup. IFRA consists of special design and analysis techniques required to bridge a major gap between system-level and circuit-level debug. Special hardware recorders, called footprint recording structures (FRS's), record semantic information about data and control flows of instructions passing through various design blocks of a processor. This information is recorded concurrently during normal operation of a processor in a post-silicon system validation setup. Upon detection of a problem, the recorded information is scanned out and analyzed for bug localization. Special program analysis techniques, together with the binary of the application executed during post-silicon validation, are used for the analysis. IFRA does not require full system-level reproduction of bugs or system-level simulation. Simulation results on a complex super-scalar processor demonstrate that IFRA is effective in accurately localizing bugs with very little impact on overall chip area.
{"title":"IFRA: Instruction Footprint Recording and Analysis for post-silicon bug localization in processors","authors":"Sung-Boem Park, S. Mitra","doi":"10.1145/1391469.1391569","DOIUrl":"https://doi.org/10.1145/1391469.1391569","url":null,"abstract":"The objective of IFRA, instruction footprint recording and analysis, is to overcome the challenges associated with a very expensive step in post-silicon validation of processors - bug localization in a system setup. IFRA consists of special design and analysis techniques required to bridge a major gap between system-level and circuit-level debug. Special hardware recorders, called footprint recording structures (FRS's), record semantic information about data and control flows of instructions passing through various design blocks of a processor. This information is recorded concurrently during normal operation of a processor in a post-silicon system validation setup. Upon detection of a problem, the recorded information is scanned out and analyzed for bug localization. Special program analysis techniques, together with the binary of the application executed during post-silicon validation, are used for the analysis. IFRA does not require full system-level reproduction of bugs or system-level simulation. Simulation results on a complex super-scalar processor demonstrate that IFRA is effective in accurately localizing bugs with very little impact on overall chip area.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130915233","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Two consultants, each with over twenty years of experience designing integrated circuits at a variety of companies large and small, are fed up with the imperfect flows typically used by their clients. Drawing on a career's worth of mistakes knowledge, they present a set of coherent engineering principles for building a better flow infrastructure.
{"title":"Flow engineering for physical implementation: Theory and practice","authors":"S. Golson, Peter Churchill","doi":"10.1145/1391469.1391471","DOIUrl":"https://doi.org/10.1145/1391469.1391471","url":null,"abstract":"Two consultants, each with over twenty years of experience designing integrated circuits at a variety of companies large and small, are fed up with the imperfect flows typically used by their clients. Drawing on a career's worth of mistakes knowledge, they present a set of coherent engineering principles for building a better flow infrastructure.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"24 6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131187870","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In the design of complex power distribution networks (PDN) with multiple power islands, it is required that the PDN represents a low impedance as seen by the digital modules. This is to reduce the simultaneous switching noise (SSN), generated due to the switching activity of digital drivers. Typically this reduction in impedance is accomplished by placing decoupling capacitors between the power and ground planes of a package or board. However, the performance of the decoupling solution is a function of capacitor selection and its placement. In this paper, an automatic capacitor placement optimization method has been proposed. This method relies on a genetic algorithm to provide a stochastic search of the design space, while employing an efficient core PDN simulator based on the multi-layer finite difference method (M-FDM). The technique has been employed to show optimized placements for split planes as well as for a realistic multi-layer server board.
{"title":"Automatic package and board decoupling capacitor placement using genetic algorithms and M-FDM","authors":"K. Bharath, E. Engin, M. Swaminathan","doi":"10.1145/1391469.1391611","DOIUrl":"https://doi.org/10.1145/1391469.1391611","url":null,"abstract":"In the design of complex power distribution networks (PDN) with multiple power islands, it is required that the PDN represents a low impedance as seen by the digital modules. This is to reduce the simultaneous switching noise (SSN), generated due to the switching activity of digital drivers. Typically this reduction in impedance is accomplished by placing decoupling capacitors between the power and ground planes of a package or board. However, the performance of the decoupling solution is a function of capacitor selection and its placement. In this paper, an automatic capacitor placement optimization method has been proposed. This method relies on a genetic algorithm to provide a stochastic search of the design space, while employing an efficient core PDN simulator based on the multi-layer finite difference method (M-FDM). The technique has been employed to show optimized placements for split planes as well as for a realistic multi-layer server board.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133158322","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The forward/backward trace refers to the trace captured after/before a target point is reached, respectively. Real time compression of the backward trace in a circular buffer is a challenging problem since the initial state of the trace currently under compression might be overwritten when wrapping around occurs. This paper presents a real time multi-resolution AHB on-chip bus tracer which is capable of capturing and compressing both forward and backward traces in a circular buffer. The backward trace is accomplished with a ping-pong organization of dual forward trace compression engines. While one module is compressing the trace, the other is clearing up its internal data structure. The roles of the two engines are exchanged periodically. The Bus Tracer, costs 60 K gates and runs up to 500 MHz in TSMC 0.13 mum technology. The experiments show that our approach achieves 2.32 to 3.98 times in effective trace depth than traditional circular buffer approaches.
{"title":"A multi-resolution AHB bus tracer for real-time compression of forward/backward traces in a circular buffer","authors":"Yi-Ting Lin, Wen-Chi Shiue, Ing-Jer Huang","doi":"10.1145/1391469.1391687","DOIUrl":"https://doi.org/10.1145/1391469.1391687","url":null,"abstract":"The forward/backward trace refers to the trace captured after/before a target point is reached, respectively. Real time compression of the backward trace in a circular buffer is a challenging problem since the initial state of the trace currently under compression might be overwritten when wrapping around occurs. This paper presents a real time multi-resolution AHB on-chip bus tracer which is capable of capturing and compressing both forward and backward traces in a circular buffer. The backward trace is accomplished with a ping-pong organization of dual forward trace compression engines. While one module is compressing the trace, the other is clearing up its internal data structure. The roles of the two engines are exchanged periodically. The Bus Tracer, costs 60 K gates and runs up to 500 MHz in TSMC 0.13 mum technology. The experiments show that our approach achieves 2.32 to 3.98 times in effective trace depth than traditional circular buffer approaches.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133474333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We consider voltage based (logic) tests to detect complete opens in digital CMOS circuits. Open defects are known to be prevalent in the current VLSI technologies and vias are known to be the primary sites of interconnect opens. The voltage on a circuit node that is disconnected due to an open via is determined by several circuit parameters. As the feature size of VLSI circuits decreases, precise knowledge of the values of circuit parameters may be difficult, if not impossible, to obtain. Thus, it is important to develop methods to generate tests to detect opens that do not require accurate knowledge of circuit parameters. We propose new classes of tests to detect via opens with voltage based (logic) tests that are effective even with imprecise knowledge of circuit parameters. The proposed tests to detect an open via are constituted as a pair of constrained stuck-at fault tests for the circuit node affected by the open defect. One class of proposed tests called circuit parameter independent tests detect via opens even in the case of complete lack of knowledge of the circuit parameters. Experimental results demonstrate that high coverage of open vias can be obtained using the proposed constrained tests.
{"title":"On tests to detect via opens in digital CMOS circuits","authors":"S. Reddy, I. Pomeranz, Chen Liu","doi":"10.1145/1391469.1391682","DOIUrl":"https://doi.org/10.1145/1391469.1391682","url":null,"abstract":"We consider voltage based (logic) tests to detect complete opens in digital CMOS circuits. Open defects are known to be prevalent in the current VLSI technologies and vias are known to be the primary sites of interconnect opens. The voltage on a circuit node that is disconnected due to an open via is determined by several circuit parameters. As the feature size of VLSI circuits decreases, precise knowledge of the values of circuit parameters may be difficult, if not impossible, to obtain. Thus, it is important to develop methods to generate tests to detect opens that do not require accurate knowledge of circuit parameters. We propose new classes of tests to detect via opens with voltage based (logic) tests that are effective even with imprecise knowledge of circuit parameters. The proposed tests to detect an open via are constituted as a pair of constrained stuck-at fault tests for the circuit node affected by the open defect. One class of proposed tests called circuit parameter independent tests detect via opens even in the case of complete lack of knowledge of the circuit parameters. Experimental results demonstrate that high coverage of open vias can be obtained using the proposed constrained tests.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"107 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124117054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A fundamental problem in timing-driven physical synthesis is the reduction of critical paths in a design. In this work, we propose a powerful new technique that moves (and can also resize) multiple cells simultaneously to smooth critical paths, thereby reducing delay and improving worst negative slack or a figure-of-merit. Our approach offers several key advantages over previous formulations, including the accurate modeling of objectives and constraints in the true timing model, and a guarantee of legality for all cell locations.
{"title":"Path smoothing via discrete optimization","authors":"Michael D. Moffitt, D. Papa, Zhuo Li, C. Alpert","doi":"10.1145/1391469.1391655","DOIUrl":"https://doi.org/10.1145/1391469.1391655","url":null,"abstract":"A fundamental problem in timing-driven physical synthesis is the reduction of critical paths in a design. In this work, we propose a powerful new technique that moves (and can also resize) multiple cells simultaneously to smooth critical paths, thereby reducing delay and improving worst negative slack or a figure-of-merit. Our approach offers several key advantages over previous formulations, including the accurate modeling of objectives and constraints in the true timing model, and a guarantee of legality for all cell locations.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124233135","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Puri, D. Varma, D. Edwards, A. Weger, P. Franzon, A. Yang, S. Kosonocky
Thermal issues are becoming more important but is the hype getting the better of the facts? Does this deserve more attention than for some niche designs and technologies such as 3D ICs.? Does the broader design community need to worry about it at 32 nm and beyond or it will only impact a small segment of designs? In short, does the severity of power issues coupled with packaging complexity translate into a thermal crisis in future? This is an educational panel with a little bit of controversy that will address the thermal issue in IC design. When will this issue be emerging as a crucial concern if at all? What are the solutions to resolve this potential crisis?
{"title":"Keeping hot chips cool: Are IC thermal problems hot air?","authors":"R. Puri, D. Varma, D. Edwards, A. Weger, P. Franzon, A. Yang, S. Kosonocky","doi":"10.1145/1391469.1391632","DOIUrl":"https://doi.org/10.1145/1391469.1391632","url":null,"abstract":"Thermal issues are becoming more important but is the hype getting the better of the facts? Does this deserve more attention than for some niche designs and technologies such as 3D ICs.? Does the broader design community need to worry about it at 32 nm and beyond or it will only impact a small segment of designs? In short, does the severity of power issues coupled with packaging complexity translate into a thermal crisis in future? This is an educational panel with a little bit of controversy that will address the thermal issue in IC design. When will this issue be emerging as a crucial concern if at all? What are the solutions to resolve this potential crisis?","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114362427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Future SoCs will contain multiple cores. For workloads with significant parallelism, prior work has shown the benefit of many small, multi-threaded, scalar cores. For workloads that require better single-thread performance, a dedicated, larger core can help but comes at a large opportunity cost in the number of scalar cores that could be provisioned instead. This paper proposes a way to repurpose a pair of scalar cores into a 2-way out-of-order issue core with minimal area overhead. "Federating" scalar cores in this way nevertheless achieves comparable performance to a dedicated out-of-order core and dissipates less power as well.
{"title":"Federation: Repurposing scalar cores for out-of-order instruction issue","authors":"D. Tarjan, Michael Boyer, K. Skadron","doi":"10.1145/1391469.1391666","DOIUrl":"https://doi.org/10.1145/1391469.1391666","url":null,"abstract":"Future SoCs will contain multiple cores. For workloads with significant parallelism, prior work has shown the benefit of many small, multi-threaded, scalar cores. For workloads that require better single-thread performance, a dedicated, larger core can help but comes at a large opportunity cost in the number of scalar cores that could be provisioned instead. This paper proposes a way to repurpose a pair of scalar cores into a 2-way out-of-order issue core with minimal area overhead. \"Federating\" scalar cores in this way nevertheless achieves comparable performance to a dedicated out-of-order core and dissipates less power as well.","PeriodicalId":412696,"journal":{"name":"2008 45th ACM/IEEE Design Automation Conference","volume":"32 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2008-06-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115053689","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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