Pub Date : 1993-06-20DOI: 10.1109/ARITH.1993.378101
N. D. Hemkumar, Joseph R. Cavallaro
A two-sided unitary transformation (Q transformation) structured to permit integrated evaluation and application using CORDIC primitives is introduced. The Q transformation is shown to be useful as an atomic operation in parallel arrays for computing the eigenvalue/singular value decomposition of Hermitian/arbitrary matrices, and three specific Q transformations that are needed in such arrays are identified. Issues related to the use of CORDIC for complex arithmetic are addressed, and implementations in both conventional (nonredundant) CORDIC and redundant and online modifications to CORDIC are described. If the time to compute a CORDIC operation in nonredundant CORDIC is T/sub c/, the Q transformations identified here can be evaluated and/or applied in 2T/sub c/ using four CORDIC modules for maximum concurrency. In either case, 0.5 T/sub c/ is required to account for scale factor correction. It is shown that a Q transformation can be evaluated and/or applied in /spl ap/10n, where n is the desired bit-precision.<>
{"title":"Efficient complex matrix transformations with CORDIC","authors":"N. D. Hemkumar, Joseph R. Cavallaro","doi":"10.1109/ARITH.1993.378101","DOIUrl":"https://doi.org/10.1109/ARITH.1993.378101","url":null,"abstract":"A two-sided unitary transformation (Q transformation) structured to permit integrated evaluation and application using CORDIC primitives is introduced. The Q transformation is shown to be useful as an atomic operation in parallel arrays for computing the eigenvalue/singular value decomposition of Hermitian/arbitrary matrices, and three specific Q transformations that are needed in such arrays are identified. Issues related to the use of CORDIC for complex arithmetic are addressed, and implementations in both conventional (nonredundant) CORDIC and redundant and online modifications to CORDIC are described. If the time to compute a CORDIC operation in nonredundant CORDIC is T/sub c/, the Q transformations identified here can be evaluated and/or applied in 2T/sub c/ using four CORDIC modules for maximum concurrency. In either case, 0.5 T/sub c/ is required to account for scale factor correction. It is shown that a Q transformation can be evaluated and/or applied in /spl ap/10n, where n is the desired bit-precision.<<ETX>>","PeriodicalId":414758,"journal":{"name":"Proceedings of IEEE 11th Symposium on Computer Arithmetic","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1993-06-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132438583","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ARITH.1993.378090
T. K. Callaway, E. Swartzlander
Six types of adders are examined in an attempt to model their power dissipation. It is shown that the use of a relatively simple model provides results that are qualitatively accurate, when compared to more sophisticated models and to physical implementations of the circuits. The main discrepancy between the simple model and the physical measurements seems to be the assumption that all gates will consume the same amount of power when they switch, regardless of their fan-in or fanout. Because the carry lookahead adder has several gates with a fan out and fan-in higher than two, the simple model underestimates its power dissipation.<>
{"title":"Estimating the power consumption of CMOS adders","authors":"T. K. Callaway, E. Swartzlander","doi":"10.1109/ARITH.1993.378090","DOIUrl":"https://doi.org/10.1109/ARITH.1993.378090","url":null,"abstract":"Six types of adders are examined in an attempt to model their power dissipation. It is shown that the use of a relatively simple model provides results that are qualitatively accurate, when compared to more sophisticated models and to physical implementations of the circuits. The main discrepancy between the simple model and the physical measurements seems to be the assumption that all gates will consume the same amount of power when they switch, regardless of their fan-in or fanout. Because the carry lookahead adder has several gates with a fan out and fan-in higher than two, the simple model underestimates its power dissipation.<<ETX>>","PeriodicalId":414758,"journal":{"name":"Proceedings of IEEE 11th Symposium on Computer Arithmetic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115116208","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ARITH.1993.378095
David Eisig, Josh Rotstain, I. Koren
The highlights of the design of an integer multiplier/divider unit for a 64-b processor are presented. The final design is the result of a compromise between performance, complexity, and transistor count. It is optimized for two specific operations with the same hardware being shared by the remaining operations. Thus, for example, the multiplier can be configured for the execution of several different multiply operations and its hardware is also heavily utilized in division. The divider design is optimized for repetitive division by small numbers, since this is a characteristic of several important applications planned for the processor. For such small divisors, the reciprocal is calculated and stored in a content-addressable memory. The stored reciprocals can then be used to generate quotients through fast multiplication. Simulations of the planned applications show a 20% to 30% performance increase over alternative designs.<>
{"title":"The design of a 64-bit integer multiplier/divider unit","authors":"David Eisig, Josh Rotstain, I. Koren","doi":"10.1109/ARITH.1993.378095","DOIUrl":"https://doi.org/10.1109/ARITH.1993.378095","url":null,"abstract":"The highlights of the design of an integer multiplier/divider unit for a 64-b processor are presented. The final design is the result of a compromise between performance, complexity, and transistor count. It is optimized for two specific operations with the same hardware being shared by the remaining operations. Thus, for example, the multiplier can be configured for the execution of several different multiply operations and its hardware is also heavily utilized in division. The divider design is optimized for repetitive division by small numbers, since this is a characteristic of several important applications planned for the processor. For such small divisors, the reciprocal is calculated and stored in a content-addressable memory. The stored reciprocals can then be used to generate quotients through fast multiplication. Simulations of the planned applications show a 20% to 30% performance increase over alternative designs.<<ETX>>","PeriodicalId":414758,"journal":{"name":"Proceedings of IEEE 11th Symposium on Computer Arithmetic","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124784074","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1900-01-01DOI: 10.1109/ARITH.1993.378106
S. E. McQuillan, J. McCanny, R. Hamill
Radix two algorithms for SRT division and square-rooting are developed. For these schemes, the result digits and the residuals are computed concurrently and the computations in adjacent rows are overlapped. Consequently, their performance should exceed that of the radix 2 SRT methods. VLSI array architectures for implementing the new division and square-rooting methods are also presented.<>
{"title":"New algorithms and VLSI architectures for SRT division and square root","authors":"S. E. McQuillan, J. McCanny, R. Hamill","doi":"10.1109/ARITH.1993.378106","DOIUrl":"https://doi.org/10.1109/ARITH.1993.378106","url":null,"abstract":"Radix two algorithms for SRT division and square-rooting are developed. For these schemes, the result digits and the residuals are computed concurrently and the computations in adjacent rows are overlapped. Consequently, their performance should exceed that of the radix 2 SRT methods. VLSI array architectures for implementing the new division and square-rooting methods are also presented.<<ETX>>","PeriodicalId":414758,"journal":{"name":"Proceedings of IEEE 11th Symposium on Computer Arithmetic","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130379410","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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