Pub Date : 1987-05-18DOI: 10.1109/ARITH.1987.6158698
H. Hamada
A new internal representation is proposed for real numbers. It has been named URR for universal representation of real numbers. This approach is based on a bisection method which is applied to real number intervals. With this method, the point of division increases or decreases in a double exponential manner in the global range.
{"title":"A new real number representation and its operation","authors":"H. Hamada","doi":"10.1109/ARITH.1987.6158698","DOIUrl":"https://doi.org/10.1109/ARITH.1987.6158698","url":null,"abstract":"A new internal representation is proposed for real numbers. It has been named URR for universal representation of real numbers. This approach is based on a bisection method which is applied to real number intervals. With this method, the point of division increases or decreases in a double exponential manner in the global range.","PeriodicalId":424620,"journal":{"name":"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115794953","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-05-18DOI: 10.1109/ARITH.1987.6158704
R. Kirchner, U. Kulisch
In electronic computers the elementary-arithmetic operations are these days generally approximated by floating-point operations of highest accuracy. Vector processors and parallel computers often provide additional operations like “multiply and add”, “accumulate” or “multiply and accumulate”. Also these operations shall always deliver the correct answer whatever the data are. The user should not be oblighed to execute an error analysis for operations predefined by the manufacturer. In the first part of this paper we discuss circuits which allow a fast and correct computation of sums and scalar products making use of a matrix shaped arrangement of adders and pipeline technology. In the second part a variant is discussed which permits a drastic reduction in the number of adders required. The methods discussed in this paper can also be used to build a fast arithmetic unit for micro computers in VLSI-technology.
{"title":"Arithmetic for vector processors","authors":"R. Kirchner, U. Kulisch","doi":"10.1109/ARITH.1987.6158704","DOIUrl":"https://doi.org/10.1109/ARITH.1987.6158704","url":null,"abstract":"In electronic computers the elementary-arithmetic operations are these days generally approximated by floating-point operations of highest accuracy. Vector processors and parallel computers often provide additional operations like “multiply and add”, “accumulate” or “multiply and accumulate”. Also these operations shall always deliver the correct answer whatever the data are. The user should not be oblighed to execute an error analysis for operations predefined by the manufacturer. In the first part of this paper we discuss circuits which allow a fast and correct computation of sums and scalar products making use of a matrix shaped arrangement of adders and pipeline technology. In the second part a variant is discussed which permits a drastic reduction in the number of adders required. The methods discussed in this paper can also be used to build a fast arithmetic unit for micro computers in VLSI-technology.","PeriodicalId":424620,"journal":{"name":"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131735879","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-05-18DOI: 10.1109/ARITH.1987.6158713
G. Redinbo
Fault-tolerance in dense high-speed arithmetic units that calculate convolutions between arrays of data is introduced through cyclic codes which are defined over the rings and fields commonly employed by such units. New systematic encoding and data manipulation techniques make the application of these generalized cyclic codes to error detection straightforward and efficient. The necessary overhead parity computations have complexity proportional to the number of parity symbols squared, whereas the error-detecting capability for both random and burst errors is directly related to this parity number.
{"title":"Protecting convolution-type aritmetic array calculations with generalized cyclic codes","authors":"G. Redinbo","doi":"10.1109/ARITH.1987.6158713","DOIUrl":"https://doi.org/10.1109/ARITH.1987.6158713","url":null,"abstract":"Fault-tolerance in dense high-speed arithmetic units that calculate convolutions between arrays of data is introduced through cyclic codes which are defined over the rings and fields commonly employed by such units. New systematic encoding and data manipulation techniques make the application of these generalized cyclic codes to error detection straightforward and efficient. The necessary overhead parity computations have complexity proportional to the number of parity symbols squared, whereas the error-detecting capability for both random and burst errors is directly related to this parity number.","PeriodicalId":424620,"journal":{"name":"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128209889","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-05-18DOI: 10.1109/ARITH.1987.6158702
K. Hwang, H. C. Wang, Z. Xu
Fast evaluation of vector-valued elementary functions plays a vital role in many real-time applications. In this paper, we present a pipeline networking approach to designing a Chebyshev polynomial evaluator for the fast evaluation of elementary functions over a string of arguments. In particular, pipeline nets are employed to perform the preprocessing and postprocessing of various elementary functions to boost the overall system performance. Design tradeoffs are analyzed among representational accuracy, processing speed and hardware complexity.
{"title":"Evaluating elementary functions with Chebyshev polynomials on pipeline nets","authors":"K. Hwang, H. C. Wang, Z. Xu","doi":"10.1109/ARITH.1987.6158702","DOIUrl":"https://doi.org/10.1109/ARITH.1987.6158702","url":null,"abstract":"Fast evaluation of vector-valued elementary functions plays a vital role in many real-time applications. In this paper, we present a pipeline networking approach to designing a Chebyshev polynomial evaluator for the fast evaluation of elementary functions over a string of arguments. In particular, pipeline nets are employed to perform the preprocessing and postprocessing of various elementary functions to boost the overall system performance. Design tradeoffs are analyzed among representational accuracy, processing speed and hardware complexity.","PeriodicalId":424620,"journal":{"name":"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132974854","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-05-18DOI: 10.1109/ARITH.1987.6158706
S. Kuninobu, T. Nishiyama, H. Edamatsu, T. Taniguchi, N. Takagi
A high speed multiplier and divider for MOS LSI based on a new algorithm is presented. When we implement the multiplier and the divider in LSI, the features such as high speed operation, small number of transistors and easy layout are the most important factors. A computational algorithm using a redundant binary representation has several excellent features such as high speed addition operations. We improved the algorithm and the method of implementation, and designed an advanced multiplier and divider with the above mentioned features. We expect mat our multiplier and divider are excellent compared with multipliers using the Booth algorithm and the Wallace tree, and with divider using the SRT method, respectively.
{"title":"Design of high speed MOS multiplier and divider using redundant binary representation","authors":"S. Kuninobu, T. Nishiyama, H. Edamatsu, T. Taniguchi, N. Takagi","doi":"10.1109/ARITH.1987.6158706","DOIUrl":"https://doi.org/10.1109/ARITH.1987.6158706","url":null,"abstract":"A high speed multiplier and divider for MOS LSI based on a new algorithm is presented. When we implement the multiplier and the divider in LSI, the features such as high speed operation, small number of transistors and easy layout are the most important factors. A computational algorithm using a redundant binary representation has several excellent features such as high speed addition operations. We improved the algorithm and the method of implementation, and designed an advanced multiplier and divider with the above mentioned features. We expect mat our multiplier and divider are excellent compared with multipliers using the Booth algorithm and the Wallace tree, and with divider using the SRT method, respectively.","PeriodicalId":424620,"journal":{"name":"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121988257","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-05-18DOI: 10.1109/ARITH.1987.6158717
Ramautar Sharma
Algorithms for the high speed binary arithmetic operations of addition and multiplication in a VLSI environment are analyzed for area-time efficiency. It is shown that some schemes for addition and multiplication, although good for stand-alone designs, fail to provide both area and time efficiencies simultaneously. Solutions that yield area-time efficient practical implementations of these arithmetic functions are described.
{"title":"Area-time efficient arithmetic elements for VLSI systems","authors":"Ramautar Sharma","doi":"10.1109/ARITH.1987.6158717","DOIUrl":"https://doi.org/10.1109/ARITH.1987.6158717","url":null,"abstract":"Algorithms for the high speed binary arithmetic operations of addition and multiplication in a VLSI environment are analyzed for area-time efficiency. It is shown that some schemes for addition and multiplication, although good for stand-alone designs, fail to provide both area and time efficiencies simultaneously. Solutions that yield area-time efficient practical implementations of these arithmetic functions are described.","PeriodicalId":424620,"journal":{"name":"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130878110","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-05-18DOI: 10.1109/ARITH.1987.6158707
H. Lin, H. Sips
This paper describes a new online division (reciprocal) algorithm for (maximally) redundant floating-point numbers of arbitrary radix. The algorithm works for normalized, quasi-normalized, and pseudo-normailized numbers and can therefore be applied in chained online compuatations. The online delay of die proposed algorithm is the smallest reported so far. The algorithm consista of two steps: the first m digits of the result are generated by a simple table lookup method; the remaining n-m digits are generated by using an adapted Newton-Raphson iteration method. In the second step, the online digits are created by using a fast and simple selection mechanism.
{"title":"A novel floating-point online division algorithm","authors":"H. Lin, H. Sips","doi":"10.1109/ARITH.1987.6158707","DOIUrl":"https://doi.org/10.1109/ARITH.1987.6158707","url":null,"abstract":"This paper describes a new online division (reciprocal) algorithm for (maximally) redundant floating-point numbers of arbitrary radix. The algorithm works for normalized, quasi-normalized, and pseudo-normailized numbers and can therefore be applied in chained online compuatations. The online delay of die proposed algorithm is the smallest reported so far. The algorithm consista of two steps: the first m digits of the result are generated by a simple table lookup method; the remaining n-m digits are generated by using an adapted Newton-Raphson iteration method. In the second step, the online digits are created by using a fast and simple selection mechanism.","PeriodicalId":424620,"journal":{"name":"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121707949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-05-18DOI: 10.1109/ARITH.1987.6158709
F. Olver, P. Turner
This paper is concerned with finding fast efficient algorithms for performing level-index arithmetic. The approach used combines the advantages of parallel processing with the use of table look-up. The latter is used only for short words and the result is a potential implementation with ℓi operation times comparable with floating-point long multiplications.
{"title":"Implementation of level-index arithmetic using partial table look-up","authors":"F. Olver, P. Turner","doi":"10.1109/ARITH.1987.6158709","DOIUrl":"https://doi.org/10.1109/ARITH.1987.6158709","url":null,"abstract":"This paper is concerned with finding fast efficient algorithms for performing level-index arithmetic. The approach used combines the advantages of parallel processing with the use of table look-up. The latter is used only for short words and the result is a potential implementation with ℓi operation times comparable with floating-point long multiplications.","PeriodicalId":424620,"journal":{"name":"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115667996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-05-18DOI: 10.1109/ARITH.1987.6158710
B. Parhami
Although a state encoding scheme for systolic counters has been presented earlier, several important practical problems such as zero test, sign detection, overflow, underflow, and modulo-n (cyclic) counting have not been dealt with adequately. In this paper, design principles for unary and binary systolic up/down counters are presented. The unary counters, which are attractive when dealing with relatively small counts, are based on the systolic stack concept. The binary counters use conventional binary number representation, with several tags associated with each bit position. The binary counter design presented can be generalized to counters with higher-radix state encodings.
{"title":"Systolic up/down counters with zero and sign detection","authors":"B. Parhami","doi":"10.1109/ARITH.1987.6158710","DOIUrl":"https://doi.org/10.1109/ARITH.1987.6158710","url":null,"abstract":"Although a state encoding scheme for systolic counters has been presented earlier, several important practical problems such as zero test, sign detection, overflow, underflow, and modulo-n (cyclic) counting have not been dealt with adequately. In this paper, design principles for unary and binary systolic up/down counters are presented. The unary counters, which are attractive when dealing with relatively small counts, are based on the systolic stack concept. The binary counters use conventional binary number representation, with several tags associated with each bit position. The binary counter design presented can be generalized to counters with higher-radix state encodings.","PeriodicalId":424620,"journal":{"name":"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)","volume":"61 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127857830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-05-18DOI: 10.1109/ARITH.1987.6158683
G. Barrett
This paper presents a formal description of rounding, as specified in the IEEE Standard, and an algorithm to perform the task along with its proof of correctness.
本文给出了IEEE标准中规定的舍入的形式化描述，以及执行该任务的算法及其正确性证明。
{"title":"A formal approach to rounding","authors":"G. Barrett","doi":"10.1109/ARITH.1987.6158683","DOIUrl":"https://doi.org/10.1109/ARITH.1987.6158683","url":null,"abstract":"This paper presents a formal description of rounding, as specified in the IEEE Standard, and an algorithm to perform the task along with its proof of correctness.","PeriodicalId":424620,"journal":{"name":"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121455460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：