Pub Date : 1987-05-18DOI: 10.1109/ARITH.1987.6158703
R.-S. Kao, F. Taylor
Recently the complex residue number system, or RNS, has been a subject of intense study. One special embodiment of this theory is the single modulus complex RNS processor which suggests both implementation and performance advantages. In this paper these conjectures are tested in the context of a CMOS gate array design and are found to be valid. This work was supported under an ARO grant.
{"title":"Implementation of the single modulus complex ALU","authors":"R.-S. Kao, F. Taylor","doi":"10.1109/ARITH.1987.6158703","DOIUrl":"https://doi.org/10.1109/ARITH.1987.6158703","url":null,"abstract":"Recently the complex residue number system, or RNS, has been a subject of intense study. One special embodiment of this theory is the single modulus complex RNS processor which suggests both implementation and performance advantages. In this paper these conjectures are tested in the context of a CMOS gate array design and are found to be valid. This work was supported under an ARO grant.","PeriodicalId":424620,"journal":{"name":"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129401457","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-05-18DOI: 10.1109/ARITH.1987.6158685
Tony M. Carter
Robertson's Theory of Decomposition and Structured Tiling (an IC design technique) are combined in a structured arithmetic circuit design method. This method, extended by a set of inverse operators and a set of multiply operators, is used with computer-aided design tools to automate the design of arithmetic circuits.
{"title":"Structured arithmetic tiling of integrated circuits","authors":"Tony M. Carter","doi":"10.1109/ARITH.1987.6158685","DOIUrl":"https://doi.org/10.1109/ARITH.1987.6158685","url":null,"abstract":"Robertson's Theory of Decomposition and Structured Tiling (an IC design technique) are combined in a structured arithmetic circuit design method. This method, extended by a set of inverse operators and a set of multiply operators, is used with computer-aided design tools to automate the design of arithmetic circuits.","PeriodicalId":424620,"journal":{"name":"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)","volume":"3 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130591317","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-05-18DOI: 10.1109/ARITH.1987.6158716
G. Schumacher
Interval arithmetic, i.e. the computation with numbers which are afflicted with tolerances, always provides reliable statements when applied in numerical algorithms on computers. It guarantees that the exact result of an algorithm lies within the computed tolerance bounds. In ill-conditioned cases these bounds may be extremly wide and although the statement still remains valid, it is in practice worthless. Methods which have been recently introduced as E-methods provide the possibility of successively diminishing the tolerance. Furthermore, the existence and uniqueness of the solution is proved (in a mathematical sense) by the computer. These methods combine the concepts of interval analysis with the computer arithmetic defined by Kulisch and Miranker. They are based on fixed point theorems and an exact scalar product is essential for their implementation.
{"title":"Computer arithmetic and ill-conditioned algebraic problems","authors":"G. Schumacher","doi":"10.1109/ARITH.1987.6158716","DOIUrl":"https://doi.org/10.1109/ARITH.1987.6158716","url":null,"abstract":"Interval arithmetic, i.e. the computation with numbers which are afflicted with tolerances, always provides reliable statements when applied in numerical algorithms on computers. It guarantees that the exact result of an algorithm lies within the computed tolerance bounds. In ill-conditioned cases these bounds may be extremly wide and although the statement still remains valid, it is in practice worthless. Methods which have been recently introduced as E-methods provide the possibility of successively diminishing the tolerance. Furthermore, the existence and uniqueness of the solution is proved (in a mathematical sense) by the computer. These methods combine the concepts of interval analysis with the computer arithmetic defined by Kulisch and Miranker. They are based on fixed point theorems and an exact scalar product is essential for their implementation.","PeriodicalId":424620,"journal":{"name":"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115176355","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-05-18DOI: 10.1109/ARITH.1987.6158708
F. Olver
Two closely related new systems of computer arithmetic are proposed. It is shown that both are closed under arithmetic operations in finite-precision arithmetic, thereby offering a permanent solution to the problems of overflow and underflow. Other advantages of the new systems pertaining to precision are described, and there is also a brief discussion of possible ways of hardware implementation.
{"title":"A closed computer arithmetic","authors":"F. Olver","doi":"10.1109/ARITH.1987.6158708","DOIUrl":"https://doi.org/10.1109/ARITH.1987.6158708","url":null,"abstract":"Two closely related new systems of computer arithmetic are proposed. It is shown that both are closed under arithmetic operations in finite-precision arithmetic, thereby offering a permanent solution to the problems of overflow and underflow. Other advantages of the new systems pertaining to precision are described, and there is also a brief discussion of possible ways of hardware implementation.","PeriodicalId":424620,"journal":{"name":"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124368070","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-05-18DOI: 10.1109/ARITH.1987.6158687
L. Ciminiera
Two new implementations of parallel multipliers, based on iterative arrays of logic cells are presented in this paper. Both are able to compute the product of two n bit numbers with a delay of n cells, rather 2n−l as in classical structures. The high speed operation is obtained by using pure horizontal compressors, to accelerate the horizontal signal propagation, and by adopting a suitable array structure, to shorten the vertical signal propagation. The cost and performance advantages over similar structures based on vertical compressors are discussed.
{"title":"Parallel multipliers based on horizontal compressors","authors":"L. Ciminiera","doi":"10.1109/ARITH.1987.6158687","DOIUrl":"https://doi.org/10.1109/ARITH.1987.6158687","url":null,"abstract":"Two new implementations of parallel multipliers, based on iterative arrays of logic cells are presented in this paper. Both are able to compute the product of two n bit numbers with a delay of n cells, rather 2n−l as in classical structures. The high speed operation is obtained by using pure horizontal compressors, to accelerate the horizontal signal propagation, and by adopting a suitable array structure, to shorten the vertical signal propagation. The cost and performance advantages over similar structures based on vertical compressors are discussed.","PeriodicalId":424620,"journal":{"name":"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121496498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-05-18DOI: 10.1109/ARITH.1987.6158688
A. Colagrossi, A. Miola
This paper presents a new algorithmic approach to cope with the problems related to the generation and the manipulation of the pseudo-Hensel-codes in the p-adic arithmetic. After reviewing some classical properties and the results of the Hensel code arithmetic, a new algorithm to manipulate pseudo-Hensel-codes is presented, discussed and compared with two existing methods. The lower cost of the proposed new algorithm will result from the comparison.
{"title":"A normalization algorithm for truncated p-adic arithmetic","authors":"A. Colagrossi, A. Miola","doi":"10.1109/ARITH.1987.6158688","DOIUrl":"https://doi.org/10.1109/ARITH.1987.6158688","url":null,"abstract":"This paper presents a new algorithmic approach to cope with the problems related to the generation and the manipulation of the pseudo-Hensel-codes in the p-adic arithmetic. After reviewing some classical properties and the results of the Hensel code arithmetic, a new algorithm to manipulate pseudo-Hensel-codes is presented, discussed and compared with two existing methods. The lower cost of the proposed new algorithm will result from the comparison.","PeriodicalId":424620,"journal":{"name":"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)","volume":"1 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115595866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-05-18DOI: 10.1109/ARITH.1987.6158701
T. E. Hull, M. S. Cohen
A new computer arithmetic is described. Closely related built-in functions are included. A user's point of view is taken, so that the emphasis is on what language features are available to a user. The main new feature is flexible precision control of decimal floating-point arithmetic. It is intended that the language facilities be sufficient for describing numerical processes one might want to implement, while at the same time being simple to use, and implementable in a reasonably efficient manner. Illustrative examples are based on experience with an existing software implementation.
{"title":"Toward an ideal computer arithmetic","authors":"T. E. Hull, M. S. Cohen","doi":"10.1109/ARITH.1987.6158701","DOIUrl":"https://doi.org/10.1109/ARITH.1987.6158701","url":null,"abstract":"A new computer arithmetic is described. Closely related built-in functions are included. A user's point of view is taken, so that the emphasis is on what language features are available to a user. The main new feature is flexible precision control of decimal floating-point arithmetic. It is intended that the language facilities be sufficient for describing numerical processes one might want to implement, while at the same time being simple to use, and implementable in a reasonably efficient manner. Illustrative examples are based on experience with an existing software implementation.","PeriodicalId":424620,"journal":{"name":"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)","volume":"57 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125838164","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-05-18DOI: 10.1109/ARITH.1987.6158712
V. Piuri
Much attention has been recently given to VLSI and WSI processing arrays: systolic arrays are often adopted to execute a wide class of algorithms, e.g for matrix arithmetic or signal and image processing. In this paper a fault-tolerant architecture is proposed to allow reliable computation of systolic arrays by using physical redundancy and residue number coding. Such architecture supplies also information for fast reconfiguration.
{"title":"Fault-tolerant systolic arrays: An approach based upon residue arithmetic","authors":"V. Piuri","doi":"10.1109/ARITH.1987.6158712","DOIUrl":"https://doi.org/10.1109/ARITH.1987.6158712","url":null,"abstract":"Much attention has been recently given to VLSI and WSI processing arrays: systolic arrays are often adopted to execute a wide class of algorithms, e.g for matrix arithmetic or signal and image processing. In this paper a fault-tolerant architecture is proposed to allow reliable computation of systolic arrays by using physical redundancy and residue number coding. Such architecture supplies also information for fast reconfiguration.","PeriodicalId":424620,"journal":{"name":"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128561464","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-05-18DOI: 10.1109/ARITH.1987.6158682
P. Balsara, R. Owens
Digit serial data transmission can be used to an advantage in the design of special purpose processors where communication issues dominate and where digit pipelining can be used to maintain high data rates. VLSI signal processing is one such problem domain. We propose designs of systolic and semi-systolic digit serial multipliers. These multipliers are programmable i.e. one operand is pre-stored in the multiplier and the other operand is fed in a digit serial fashion. The VLSI implementation of the systolic multiplier is also given. This systolic multiplier is used in our VLSI signal processing system.
{"title":"Systolic & semi-systolic digit serial multipliers","authors":"P. Balsara, R. Owens","doi":"10.1109/ARITH.1987.6158682","DOIUrl":"https://doi.org/10.1109/ARITH.1987.6158682","url":null,"abstract":"Digit serial data transmission can be used to an advantage in the design of special purpose processors where communication issues dominate and where digit pipelining can be used to maintain high data rates. VLSI signal processing is one such problem domain. We propose designs of systolic and semi-systolic digit serial multipliers. These multipliers are programmable i.e. one operand is pre-stored in the multiplier and the other operand is fed in a digit serial fashion. The VLSI implementation of the systolic multiplier is also given. This systolic multiplier is used in our VLSI signal processing system.","PeriodicalId":424620,"journal":{"name":"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132406192","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1987-05-18DOI: 10.1109/ARITH.1987.6158693
J. D. Croz, M. Pont
{"title":"The development of a floating-point validation package","authors":"J. D. Croz, M. Pont","doi":"10.1109/ARITH.1987.6158693","DOIUrl":"https://doi.org/10.1109/ARITH.1987.6158693","url":null,"abstract":"","PeriodicalId":424620,"journal":{"name":"1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-05-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124182701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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