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1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)最新文献

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Implementation of the single modulus complex ALU 单模复数ALU的实现
Pub Date : 1987-05-18 DOI: 10.1109/ARITH.1987.6158703
R.-S. Kao, F. Taylor
Recently the complex residue number system, or RNS, has been a subject of intense study. One special embodiment of this theory is the single modulus complex RNS processor which suggests both implementation and performance advantages. In this paper these conjectures are tested in the context of a CMOS gate array design and are found to be valid. This work was supported under an ARO grant.
近年来,复剩数系统(RNS)一直是人们研究的热点。该理论的一个特殊体现是单模复数RNS处理器,它在实现和性能上都有优势。在本文中,这些猜想在CMOS门阵列设计的背景下进行了测试,并发现是有效的。这项工作得到了ARO拨款的支持。
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引用次数: 1
Structured arithmetic tiling of integrated circuits 集成电路的结构化算术平铺
Pub Date : 1987-05-18 DOI: 10.1109/ARITH.1987.6158685
Tony M. Carter
Robertson's Theory of Decomposition and Structured Tiling (an IC design technique) are combined in a structured arithmetic circuit design method. This method, extended by a set of inverse operators and a set of multiply operators, is used with computer-aided design tools to automate the design of arithmetic circuits.
将罗伯逊的分解理论和结构化平铺(一种集成电路设计技术)结合成一种结构化的算术电路设计方法。该方法通过一组逆算子和一组乘算子的扩展,与计算机辅助设计工具一起实现了算术电路的自动化设计。
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引用次数: 6
Computer arithmetic and ill-conditioned algebraic problems 计算机算术与病态代数问题
Pub Date : 1987-05-18 DOI: 10.1109/ARITH.1987.6158716
G. Schumacher
Interval arithmetic, i.e. the computation with numbers which are afflicted with tolerances, always provides reliable statements when applied in numerical algorithms on computers. It guarantees that the exact result of an algorithm lies within the computed tolerance bounds. In ill-conditioned cases these bounds may be extremly wide and although the statement still remains valid, it is in practice worthless. Methods which have been recently introduced as E-methods provide the possibility of successively diminishing the tolerance. Furthermore, the existence and uniqueness of the solution is proved (in a mathematical sense) by the computer. These methods combine the concepts of interval analysis with the computer arithmetic defined by Kulisch and Miranker. They are based on fixed point theorems and an exact scalar product is essential for their implementation.
区间算法,即对受公差影响的数字进行计算,在计算机上应用于数值算法时总是提供可靠的结论。它保证算法的精确结果在计算的公差范围内。在病态的情况下,这些界限可能非常宽,尽管这个陈述仍然有效,但实际上它是毫无价值的。最近作为e -方法引入的方法提供了逐渐减小公差的可能性。进一步,用计算机证明了解的存在唯一性(在数学意义上)。这些方法将区间分析的概念与Kulisch和Miranker定义的计算机算法相结合。它们基于不动点定理,精确的标量积对于它们的实现至关重要。
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引用次数: 3
A closed computer arithmetic 一个封闭的计算机算法
Pub Date : 1987-05-18 DOI: 10.1109/ARITH.1987.6158708
F. Olver
Two closely related new systems of computer arithmetic are proposed. It is shown that both are closed under arithmetic operations in finite-precision arithmetic, thereby offering a permanent solution to the problems of overflow and underflow. Other advantages of the new systems pertaining to precision are described, and there is also a brief discussion of possible ways of hardware implementation.
提出了两个密切相关的计算机算法新系统。在有限精度算法中,两者在算术运算下都是封闭的,从而永久地解决了溢流和下流问题。描述了新系统在精度方面的其他优点,并简要讨论了硬件实现的可能方法。
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引用次数: 9
Parallel multipliers based on horizontal compressors 基于水平压缩机的平行乘法器
Pub Date : 1987-05-18 DOI: 10.1109/ARITH.1987.6158687
L. Ciminiera
Two new implementations of parallel multipliers, based on iterative arrays of logic cells are presented in this paper. Both are able to compute the product of two n bit numbers with a delay of n cells, rather 2n−l as in classical structures. The high speed operation is obtained by using pure horizontal compressors, to accelerate the horizontal signal propagation, and by adopting a suitable array structure, to shorten the vertical signal propagation. The cost and performance advantages over similar structures based on vertical compressors are discussed.
本文提出了两种新的基于逻辑单元迭代阵列的并行乘法器。两者都能够计算两个n位数字的乘积,延迟为n个单元,而不是经典结构中的2n−1。采用纯卧式压缩机实现高速运行,加速了信号的水平传播;采用合适的阵列结构,缩短了信号的垂直传播。讨论了基于立式压缩机的同类结构的成本和性能优势。
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引用次数: 1
A normalization algorithm for truncated p-adic arithmetic 截断p进算术的一种规范化算法
Pub Date : 1987-05-18 DOI: 10.1109/ARITH.1987.6158688
A. Colagrossi, A. Miola
This paper presents a new algorithmic approach to cope with the problems related to the generation and the manipulation of the pseudo-Hensel-codes in the p-adic arithmetic. After reviewing some classical properties and the results of the Hensel code arithmetic, a new algorithm to manipulate pseudo-Hensel-codes is presented, discussed and compared with two existing methods. The lower cost of the proposed new algorithm will result from the comparison.
本文提出了一种新的算法方法来解决p进算法中伪亨塞尔码的生成和处理问题。在回顾了汉塞尔码算法的一些经典性质和结果的基础上,提出了一种新的伪汉塞尔码处理算法,并与现有的两种算法进行了讨论和比较。通过比较,可以得出新算法的成本较低。
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引用次数: 4
Toward an ideal computer arithmetic 走向理想的计算机运算
Pub Date : 1987-05-18 DOI: 10.1109/ARITH.1987.6158701
T. E. Hull, M. S. Cohen
A new computer arithmetic is described. Closely related built-in functions are included. A user's point of view is taken, so that the emphasis is on what language features are available to a user. The main new feature is flexible precision control of decimal floating-point arithmetic. It is intended that the language facilities be sufficient for describing numerical processes one might want to implement, while at the same time being simple to use, and implementable in a reasonably efficient manner. Illustrative examples are based on experience with an existing software implementation.
介绍了一种新的计算机算法。包括密切相关的内置函数。考虑用户的观点,因此重点是用户可以使用哪些语言特性。该方法的主要特点是灵活的十进制浮点运算精度控制。它的目的是使语言功能足以描述人们可能想要实现的数值过程,同时使用简单,并以一种合理有效的方式实现。说明性的例子是基于已有软件实现的经验。
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引用次数: 11
Fault-tolerant systolic arrays: An approach based upon residue arithmetic 一种基于残数算法的容错收缩数组方法
Pub Date : 1987-05-18 DOI: 10.1109/ARITH.1987.6158712
V. Piuri
Much attention has been recently given to VLSI and WSI processing arrays: systolic arrays are often adopted to execute a wide class of algorithms, e.g for matrix arithmetic or signal and image processing. In this paper a fault-tolerant architecture is proposed to allow reliable computation of systolic arrays by using physical redundancy and residue number coding. Such architecture supplies also information for fast reconfiguration.
最近对VLSI和WSI处理阵列给予了很大的关注:收缩阵列通常用于执行各种算法,例如矩阵算法或信号和图像处理。本文提出了一种容错结构,利用物理冗余和剩余数编码实现收缩阵列的可靠计算。这种体系结构还为快速重新配置提供了信息。
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引用次数: 14
Systolic & semi-systolic digit serial multipliers 收缩期和半收缩期数字串行乘法器
Pub Date : 1987-05-18 DOI: 10.1109/ARITH.1987.6158682
P. Balsara, R. Owens
Digit serial data transmission can be used to an advantage in the design of special purpose processors where communication issues dominate and where digit pipelining can be used to maintain high data rates. VLSI signal processing is one such problem domain. We propose designs of systolic and semi-systolic digit serial multipliers. These multipliers are programmable i.e. one operand is pre-stored in the multiplier and the other operand is fed in a digit serial fashion. The VLSI implementation of the systolic multiplier is also given. This systolic multiplier is used in our VLSI signal processing system.
数字串行数据传输可以在通信问题占主导地位的特殊用途处理器的设计中发挥优势,并且可以使用数字流水线来保持高数据速率。超大规模集成电路信号处理就是这样一个问题领域。我们提出了收缩和半收缩数字串行乘法器的设计。这些乘数是可编程的,即一个操作数预先存储在乘数中,另一个操作数以数字串行方式输入。并给出了收缩乘法器的VLSI实现。该收缩压乘法器已应用于我们的VLSI信号处理系统中。
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引用次数: 6
The development of a floating-point validation package 浮点验证包的开发
Pub Date : 1987-05-18 DOI: 10.1109/ARITH.1987.6158693
J. D. Croz, M. Pont
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引用次数: 21
期刊
1987 IEEE 8th Symposium on Computer Arithmetic (ARITH)
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