Pub Date : 1998-03-30DOI: 10.1109/ASYNC.1998.666498
K. T. Christensen, P. Jensen, P. Korger, J. Sparsø
This paper presents the design of an asynchronous version of the TR4101 embedded microprocessor core developed by LSI Logic Inc. The asynchronous processor, called ARISC, was designed using the same CAD tools and the same standard cell library that was used to implement the TR4101. The paper reports on the design methodology, the architecture, the implementation, and the performance of the ARISC. This includes a comparison with the TR4101, and a detailed breakdown of the power consumption in the ARISC. ARISC is our first attempt at an asynchronous implementation and a number of simplifying decisions were made up front. Throughout the entire design we use four-phase handshaking in combination with a normally opaque latch controller. All logic is implemented using static logic standard cells. Despite this the ARISC performs surprisingly well: In 0.35 /spl mu/m CMOS performance is 74-123 MIPS depending on the instruction mix, and at 74 MIPS the power efficiency is 635 MIPS/Watt.
{"title":"The design of an asynchronous TinyRISC/sup TM/ TR4101 microprocessor core","authors":"K. T. Christensen, P. Jensen, P. Korger, J. Sparsø","doi":"10.1109/ASYNC.1998.666498","DOIUrl":"https://doi.org/10.1109/ASYNC.1998.666498","url":null,"abstract":"This paper presents the design of an asynchronous version of the TR4101 embedded microprocessor core developed by LSI Logic Inc. The asynchronous processor, called ARISC, was designed using the same CAD tools and the same standard cell library that was used to implement the TR4101. The paper reports on the design methodology, the architecture, the implementation, and the performance of the ARISC. This includes a comparison with the TR4101, and a detailed breakdown of the power consumption in the ARISC. ARISC is our first attempt at an asynchronous implementation and a number of simplifying decisions were made up front. Throughout the entire design we use four-phase handshaking in combination with a normally opaque latch controller. All logic is implemented using static logic standard cells. Despite this the ARISC performs surprisingly well: In 0.35 /spl mu/m CMOS performance is 74-123 MIPS depending on the instruction mix, and at 74 MIPS the power efficiency is 635 MIPS/Watt.","PeriodicalId":425072,"journal":{"name":"Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125798788","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-03-30DOI: 10.1109/ASYNC.1998.666512
Z. J. Deng, S. Whiteley, T. Duzer, J. Tierno
Superconductive Rapid Single Flux Quantum (RSFQ) logic and memory, in which ones and zeros are represented by the presence or absence within a timing window of quantized picosecond voltage pulse (/spl int/v(t)dt=h/2e=2.07 mV/spl middot/ps), corresponding to one SFQ, can be integrated into a digital computing system with an operating rate of several tens of GHz, based on the present Nb Josephson junction integrated circuit technology. It is the most promising technology beyond semiconductor transistors for low-power high-end computation. However, as the operating speed of circuits and systems increase, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, we present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. We also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Several key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists two self-timed shift registers and an on-chip 5-38 GHz clock generator.
{"title":"Asynchronous circuits and systems in superconducting RSFQ digital technology","authors":"Z. J. Deng, S. Whiteley, T. Duzer, J. Tierno","doi":"10.1109/ASYNC.1998.666512","DOIUrl":"https://doi.org/10.1109/ASYNC.1998.666512","url":null,"abstract":"Superconductive Rapid Single Flux Quantum (RSFQ) logic and memory, in which ones and zeros are represented by the presence or absence within a timing window of quantized picosecond voltage pulse (/spl int/v(t)dt=h/2e=2.07 mV/spl middot/ps), corresponding to one SFQ, can be integrated into a digital computing system with an operating rate of several tens of GHz, based on the present Nb Josephson junction integrated circuit technology. It is the most promising technology beyond semiconductor transistors for low-power high-end computation. However, as the operating speed of circuits and systems increase, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, we present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. We also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Several key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists two self-timed shift registers and an on-chip 5-38 GHz clock generator.","PeriodicalId":425072,"journal":{"name":"Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"86 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134127303","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-03-30DOI: 10.1109/ASYNC.1998.666499
William John Bainbridge, S. Furber
This paper introduces MARBLE, the Manchester AsynchRonous Bus for Low Energy, a two channel micropipeline bus with centralized arbitration and address decoding which provides for the interconnection of asynchronous VLSI macrocells. In addition to basic bus functionality, MARBLE supports bus-bridging and test access, demonstrating that all the functions of a high speed macrocell bus can be implemented efficiently in a fully asynchronous design style. MARBLE is used in the AMULET3i microprocessor to connect the CPU core and DMA controller to RAM, ROM and peripherals. It exploits pipelining of the arbitration, address and data cycles, together with spatial locality optimizations and in-order split transfers, to supply the bandwidth requirements of such a system. The design of a MARBLE initiator data interface used in the AMULET3i is presented, including a Petri-net specification suitable for synthesis using the Petrify tool.
本文介绍了一种具有集中仲裁和地址解码功能的双通道微管道总线MARBLE (Manchester AsynchRonous Bus for Low Energy)，用于异步超大规模集成电路(VLSI)宏单元的互连。除了基本的总线功能外，MARBLE还支持总线桥接和测试访问，这表明高速macrocell总线的所有功能都可以在完全异步的设计风格下有效地实现。AMULET3i微处理器使用MARBLE将CPU核心和DMA控制器连接到RAM、ROM和外设。它利用仲裁、地址和数据周期的流水线，以及空间局部性优化和按顺序分割传输，来提供这样一个系统的带宽需求。介绍了AMULET3i中使用的大理石引发剂数据接口的设计，包括适合使用石化工具合成的Petri-net规范。
{"title":"Asynchronous macrocell interconnect using MARBLE","authors":"William John Bainbridge, S. Furber","doi":"10.1109/ASYNC.1998.666499","DOIUrl":"https://doi.org/10.1109/ASYNC.1998.666499","url":null,"abstract":"This paper introduces MARBLE, the Manchester AsynchRonous Bus for Low Energy, a two channel micropipeline bus with centralized arbitration and address decoding which provides for the interconnection of asynchronous VLSI macrocells. In addition to basic bus functionality, MARBLE supports bus-bridging and test access, demonstrating that all the functions of a high speed macrocell bus can be implemented efficiently in a fully asynchronous design style. MARBLE is used in the AMULET3i microprocessor to connect the CPU core and DMA controller to RAM, ROM and peripherals. It exploits pipelining of the arbitration, address and data cycles, together with spatial locality optimizations and in-order split transfers, to supply the bandwidth requirements of such a system. The design of a MARBLE initiator data interface used in the AMULET3i is presented, including a Petri-net specification suitable for synthesis using the Petrify tool.","PeriodicalId":425072,"journal":{"name":"Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131062598","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-03-30DOI: 10.1109/ASYNC.1998.666492
N. Paver, P. Day, C. Farnsworth, D. L. Jackson, W. A. Lien, Jianwei Liu
This paper describes a commercial implementation of a self-timed DSP. The self-timed design is fully compatible with a synchronous implementation allowing comparisons of both design styles to be made. The self-timed implementation has shown many benefits over its synchronous counterpart especially with regards power consumption and noise emissions. It also demonstrates the commercial viability of self-timed designs in power and noise sensitive applications. This paper also introduces the concept of a highly configurable Application Specific Integrated Architecture (ASIA/sup TM/).
{"title":"A low-power, low noise, configurable self-timed DSP","authors":"N. Paver, P. Day, C. Farnsworth, D. L. Jackson, W. A. Lien, Jianwei Liu","doi":"10.1109/ASYNC.1998.666492","DOIUrl":"https://doi.org/10.1109/ASYNC.1998.666492","url":null,"abstract":"This paper describes a commercial implementation of a self-timed DSP. The self-timed design is fully compatible with a synchronous implementation allowing comparisons of both design styles to be made. The self-timed implementation has shown many benefits over its synchronous counterpart especially with regards power consumption and noise emissions. It also demonstrates the commercial viability of self-timed designs in power and noise sensitive applications. This paper also introduces the concept of a highly configurable Application Specific Integrated Architecture (ASIA/sup TM/).","PeriodicalId":425072,"journal":{"name":"Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"65 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126249269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-03-30DOI: 10.1109/ASYNC.1998.666490
William S. Coates, J. Lexau, I. W. Jones, Scott M. Fairbanks, I. Sutherland
A core problem in many pipelined circuit designs is data-dependent data flow. We describe a methodology and a set of circuit modules to address this problem in the asynchronous domain. We call our methodology P**3, or "P cubed". Items flowing through a set of FIFO datapaths can be conditionally steered under the control of data carried by other FIFOs. We have used the P**3 methodology to design and implement a FIFO rest chip that uses a data-dependent switch to delete marked data items conditionally. The circuit uses two on-chip FIFO rings as high-speed data sources. It was fabricated through MOSIS using their 0.6 /spl mu/ CMOS design rules. The peak data switch throughput was measured to be a minimum of 580 million data items per second at nominal Vdd of 3.3 V.
{"title":"A FIFO data switch design experiment","authors":"William S. Coates, J. Lexau, I. W. Jones, Scott M. Fairbanks, I. Sutherland","doi":"10.1109/ASYNC.1998.666490","DOIUrl":"https://doi.org/10.1109/ASYNC.1998.666490","url":null,"abstract":"A core problem in many pipelined circuit designs is data-dependent data flow. We describe a methodology and a set of circuit modules to address this problem in the asynchronous domain. We call our methodology P**3, or \"P cubed\". Items flowing through a set of FIFO datapaths can be conditionally steered under the control of data carried by other FIFOs. We have used the P**3 methodology to design and implement a FIFO rest chip that uses a data-dependent switch to delete marked data items conditionally. The circuit uses two on-chip FIFO rings as high-speed data sources. It was fabricated through MOSIS using their 0.6 /spl mu/ CMOS design rules. The peak data switch throughput was measured to be a minimum of 580 million data items per second at nominal Vdd of 3.3 V.","PeriodicalId":425072,"journal":{"name":"Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133535072","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-03-30DOI: 10.1109/ASYNC.1998.666501
Tarik Ono-Tesfaye, Christoph Kern, M. Greenstreet
This paper presents an approach to verifying timed designs based on refinement: first, correctness is established for a speed-independent model; then, the timed design is shown to be a refinement of this model. Although this approach is less automatic than methods based on timed state space enumeration, it is tractable for larger designs. Our method is implemented using a proof checker with a built-in model checker for verifying properties of high-level models, a tautology checker for establishing refinement, and a graph-based timing verification procedure for showing timing properties of transistor level models. We demonstrate the method by proving the timing correctness of Williams' self-timed divider.
{"title":"Verifying a self-timed divider","authors":"Tarik Ono-Tesfaye, Christoph Kern, M. Greenstreet","doi":"10.1109/ASYNC.1998.666501","DOIUrl":"https://doi.org/10.1109/ASYNC.1998.666501","url":null,"abstract":"This paper presents an approach to verifying timed designs based on refinement: first, correctness is established for a speed-independent model; then, the timed design is shown to be a refinement of this model. Although this approach is less automatic than methods based on timed state space enumeration, it is tractable for larger designs. Our method is implemented using a proof checker with a built-in model checker for verifying properties of high-level models, a tautology checker for establishing refinement, and a graph-based timing verification procedure for showing timing properties of transistor level models. We demonstrate the method by proving the timing correctness of Williams' self-timed divider.","PeriodicalId":425072,"journal":{"name":"Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"119 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134045608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-03-30DOI: 10.1109/ASYNC.1998.666504
W. C. Mallon, J. T. Udding
Numerous formalisms exist to specify delay-insensitive computations and their implementations. It is not always straightforward to compare specifications in the different formalisms. One way of comparing specifications is transforming them to automata in which nodes are annotated with progress requirements. In this paper we present an algorithm that transforms DI-algebra recursive process expressions into finite automata. In doing so we develop an operational semantics for DI-algebra. The algorithm has been proven correct, and we highlight the most interesting aspects of that proof The algorithm has been implemented and turns out to be very valuable in the process of getting a specification right.
{"title":"Building finite automata from DI specifications","authors":"W. C. Mallon, J. T. Udding","doi":"10.1109/ASYNC.1998.666504","DOIUrl":"https://doi.org/10.1109/ASYNC.1998.666504","url":null,"abstract":"Numerous formalisms exist to specify delay-insensitive computations and their implementations. It is not always straightforward to compare specifications in the different formalisms. One way of comparing specifications is transforming them to automata in which nodes are annotated with progress requirements. In this paper we present an algorithm that transforms DI-algebra recursive process expressions into finite automata. In doing so we develop an operational semantics for DI-algebra. The algorithm has been proven correct, and we highlight the most interesting aspects of that proof The algorithm has been implemented and turns out to be very valuable in the process of getting a specification right.","PeriodicalId":425072,"journal":{"name":"Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128577591","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-03-30DOI: 10.1109/ASYNC.1998.666500
P. T. Røine
Pseudo-random bit sequences (PRBS) are commonly used to determine the bit error rate (BER) of serial communication links. On self-clocked links in an asynchronous environment, the data rate may vary over time. An asynchronous PRBS error checker was designed for BER measurements on such links working at data rates exceeding 1 Gbps. To achieve the highest possible speed, the error checker employs a self-timed ring structure with distributed completion detection.
{"title":"An asynchronous PRBS error checker for testing high-speed self-clocked serial links","authors":"P. T. Røine","doi":"10.1109/ASYNC.1998.666500","DOIUrl":"https://doi.org/10.1109/ASYNC.1998.666500","url":null,"abstract":"Pseudo-random bit sequences (PRBS) are commonly used to determine the bit error rate (BER) of serial communication links. On self-clocked links in an asynchronous environment, the data rate may vary over time. An asynchronous PRBS error checker was designed for BER measurements on such links working at data rates exceeding 1 Gbps. To achieve the highest possible speed, the error checker employs a self-timed ring structure with distributed completion detection.","PeriodicalId":425072,"journal":{"name":"Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122137576","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-03-30DOI: 10.1109/ASYNC.1998.666493
Martin Benes, S. Nowick, A. Wolfe
This paper presents the architecture and design of a high-performance asynchronous Huffman decoder for compressed-code embedded processors. In such processors, embedded programs are stored in compressed form in instruction ROM then are decompressed on demand during instruction cache refill. The Huffman decoder is used as a code decompression engine. The circuit is non-pipelined, and is implemented as an iterative self-timed ring. It achieves a high-speed decode rate with very low area overhead. Simulations using Lsim show an average throughput of 32 bits/25 ns on the output side (or 163 MBytes/sec, or 1303 Mbit/sec), corresponding to about 889 Mbit/sec on the input side. The area of the design is extremely small: under 1 mm/sup 2/ in a 0.8 micron full-custom layout. The decoder is estimated to have higher throughput than any comparable synchronous Huffman decoder (after normalizing for feature size and voltage), yet is much smaller than synchronous designs. Its performance is also 83% faster than a recently published asynchronous Huffman decoder using the same technology.
{"title":"A fast asynchronous Huffman decoder for compressed-code embedded processors","authors":"Martin Benes, S. Nowick, A. Wolfe","doi":"10.1109/ASYNC.1998.666493","DOIUrl":"https://doi.org/10.1109/ASYNC.1998.666493","url":null,"abstract":"This paper presents the architecture and design of a high-performance asynchronous Huffman decoder for compressed-code embedded processors. In such processors, embedded programs are stored in compressed form in instruction ROM then are decompressed on demand during instruction cache refill. The Huffman decoder is used as a code decompression engine. The circuit is non-pipelined, and is implemented as an iterative self-timed ring. It achieves a high-speed decode rate with very low area overhead. Simulations using Lsim show an average throughput of 32 bits/25 ns on the output side (or 163 MBytes/sec, or 1303 Mbit/sec), corresponding to about 889 Mbit/sec on the input side. The area of the design is extremely small: under 1 mm/sup 2/ in a 0.8 micron full-custom layout. The decoder is estimated to have higher throughput than any comparable synchronous Huffman decoder (after normalizing for feature size and voltage), yet is much smaller than synchronous designs. Its performance is also 83% faster than a recently published asynchronous Huffman decoder using the same technology.","PeriodicalId":425072,"journal":{"name":"Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"64 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134624362","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1998-03-30DOI: 10.1109/ASYNC.1998.666495
K. W. James, K. Yun
We describe an automated method (3D-map) for determining near-optimal decomposed generalized C-element (gC) implementations of extended burst-mode asynchronous controllers. Average-case optimization is performed so that frequent paths are accelerated, possibly at the expense of less frequent paths. The overall effect, as quantified using Elmore delay analysis, is a circuit that has near-optimal performance for the average or common case.
{"title":"Average-case optimized transistor-level technology mapping of extended burst-mode circuits","authors":"K. W. James, K. Yun","doi":"10.1109/ASYNC.1998.666495","DOIUrl":"https://doi.org/10.1109/ASYNC.1998.666495","url":null,"abstract":"We describe an automated method (3D-map) for determining near-optimal decomposed generalized C-element (gC) implementations of extended burst-mode asynchronous controllers. Average-case optimization is performed so that frequent paths are accelerated, possibly at the expense of less frequent paths. The overall effect, as quantified using Elmore delay analysis, is a circuit that has near-optimal performance for the average or common case.","PeriodicalId":425072,"journal":{"name":"Proceedings Fourth International Symposium on Advanced Research in Asynchronous Circuits and Systems","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1998-03-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134022050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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