Faults due to configuration of resources account for majority of errors in distributed software systems. Yet, the problem of identifying faulty configuration remains at large. Current approaches for fault identification are focused on event correlation techniques which suffer from limited granular data generated by software components. As complexity of cloud environments increase, resource sharing increases many-fold thereby making it even harder to isolate configuration faults through analysis of events. In this paper, we propose a scalable approach that not only identifies the presence of a configuration fault but also attempts to nail down the parameter that is the source of the observed fault. We leverage the knowledge of shared resources in the environment and use a simple matrix representation for providing near real-time analysis of the faults. This enables the solution to be used for both reactive management and for automated proactive problem determination. Experiments through simulations demonstrate that our approach is effective in identifying configuration faults with reduced time and increased accuracy. Our algorithm gracefully handles the complexity of the problem as the system size grows.
{"title":"Nail-it-down: nailing and fixing configuration faults in cloud environments","authors":"Kalapriya Kannan, A. Bhamidipaty","doi":"10.1145/2482767.2482796","DOIUrl":"https://doi.org/10.1145/2482767.2482796","url":null,"abstract":"Faults due to configuration of resources account for majority of errors in distributed software systems. Yet, the problem of identifying faulty configuration remains at large. Current approaches for fault identification are focused on event correlation techniques which suffer from limited granular data generated by software components. As complexity of cloud environments increase, resource sharing increases many-fold thereby making it even harder to isolate configuration faults through analysis of events. In this paper, we propose a scalable approach that not only identifies the presence of a configuration fault but also attempts to nail down the parameter that is the source of the observed fault. We leverage the knowledge of shared resources in the environment and use a simple matrix representation for providing near real-time analysis of the faults. This enables the solution to be used for both reactive management and for automated proactive problem determination. Experiments through simulations demonstrate that our approach is effective in identifying configuration faults with reduced time and increased accuracy. Our algorithm gracefully handles the complexity of the problem as the system size grows.","PeriodicalId":430420,"journal":{"name":"ACM International Conference on Computing Frontiers","volume":"1 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120971785","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Providing fault tolerance especially to mission critical applications in order to detect transient and permanent faults and to recover from them is one of the main necessity for processor designers. However, fault tolerance for multi-threaded applications presents high performance degradations due to comparing the results of the instruction streams, checkpointing the entire system and recovering from the detected errors to an agreed state. In this study, we present FaulTM-multi, a fault tolerance scheme for multi threaded applications running on transactional memory hardware which reduces these performance degradations. FaulTM-multi decreases the performance degradation of lockstepping, a conventional fault detection scheme, from 23% and 9% to 10% and 2% for lock-based parallel and TM applications respectively. Also, FaulTM-multi creates 28% less checkpoints compared to Rebound, the state of the art checkpointing scheme.
{"title":"Fault tolerance for multi-threaded applications by leveraging hardware transactional memory","authors":"Gulay Yalcin, O. Unsal, A. Cristal","doi":"10.1145/2482767.2482773","DOIUrl":"https://doi.org/10.1145/2482767.2482773","url":null,"abstract":"Providing fault tolerance especially to mission critical applications in order to detect transient and permanent faults and to recover from them is one of the main necessity for processor designers. However, fault tolerance for multi-threaded applications presents high performance degradations due to comparing the results of the instruction streams, checkpointing the entire system and recovering from the detected errors to an agreed state. In this study, we present FaulTM-multi, a fault tolerance scheme for multi threaded applications running on transactional memory hardware which reduces these performance degradations. FaulTM-multi decreases the performance degradation of lockstepping, a conventional fault detection scheme, from 23% and 9% to 10% and 2% for lock-based parallel and TM applications respectively. Also, FaulTM-multi creates 28% less checkpoints compared to Rebound, the state of the art checkpointing scheme.","PeriodicalId":430420,"journal":{"name":"ACM International Conference on Computing Frontiers","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125580835","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The scale and complexity of todays IT-Infrastructures represent a challenge to understand the effects of modifications to these IT-Infrastructures or their components. This motivates the following research question: "How to evaluate high-level, global capability effects induced through low-level, local modifications to IT-Infrastructures?". Answering this question requires understanding of IT-Infrastructures in general and especially of their building blocks and of the complex interdependencies and ratios between capabilities, which have to be considered while planning modifications. After further illustrating the environment by providing an exemplary scenario, the question is described in detail. Preliminary results and the next steps to conduct on the way to answer the above mentioned research question are presented.
{"title":"An IT-infrastructure capability model","authors":"Christian Straube, D. Kranzlmüller","doi":"10.1145/2482767.2482781","DOIUrl":"https://doi.org/10.1145/2482767.2482781","url":null,"abstract":"The scale and complexity of todays IT-Infrastructures represent a challenge to understand the effects of modifications to these IT-Infrastructures or their components. This motivates the following research question: \"How to evaluate high-level, global capability effects induced through low-level, local modifications to IT-Infrastructures?\". Answering this question requires understanding of IT-Infrastructures in general and especially of their building blocks and of the complex interdependencies and ratios between capabilities, which have to be considered while planning modifications. After further illustrating the environment by providing an exemplary scenario, the question is described in detail. Preliminary results and the next steps to conduct on the way to answer the above mentioned research question are presented.","PeriodicalId":430420,"journal":{"name":"ACM International Conference on Computing Frontiers","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126157418","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Heba Saadeldeen, D. Franklin, Guoping Long, Charlotte Hill, Aisha Browne, D. Strukov, T. Sherwood, F. Chong
Memristors offer many potential advantages over more traditional memory-cell technologies, including the potential for extreme densities, and fast read times. Current devices, however, are plagued by problems of yield, and durability. We present a limit study of an aggressive neural network application that has a high update rate and a strict latency requirement, analog neural branch predictor. Of course, traditional analog neural network (ANN) implementations of branch predictors are not built with the idea that the underlying bits are likely to fail due to both manufacturing and wear-out issues. Without some careful precautions, a direct one-to-one replacement will result in poor behavior. We propose a hybrid system that uses SRAM front-end cache, and a distributed-sum scheme to overcome memristors' limitations. Our design can leverage devices with even modest durability (surviving only hours of continuous switching) to provide a system lasting 5 or more years of continuous operation. In addition, these schemes allow for a fault-tolerant design as well. We find that, while a neural predictor benefits from larger density, current technology parameters do not allow high dense, energy-efficient design. Thus, we discuss a range of plausible memristor characteristics that would; as the technology advances; make them practical for our application.
{"title":"Memristors for neural branch prediction: a case study in strict latency and write endurance challenges","authors":"Heba Saadeldeen, D. Franklin, Guoping Long, Charlotte Hill, Aisha Browne, D. Strukov, T. Sherwood, F. Chong","doi":"10.1145/2482767.2482801","DOIUrl":"https://doi.org/10.1145/2482767.2482801","url":null,"abstract":"Memristors offer many potential advantages over more traditional memory-cell technologies, including the potential for extreme densities, and fast read times. Current devices, however, are plagued by problems of yield, and durability. We present a limit study of an aggressive neural network application that has a high update rate and a strict latency requirement, analog neural branch predictor. Of course, traditional analog neural network (ANN) implementations of branch predictors are not built with the idea that the underlying bits are likely to fail due to both manufacturing and wear-out issues. Without some careful precautions, a direct one-to-one replacement will result in poor behavior.\u0000 We propose a hybrid system that uses SRAM front-end cache, and a distributed-sum scheme to overcome memristors' limitations. Our design can leverage devices with even modest durability (surviving only hours of continuous switching) to provide a system lasting 5 or more years of continuous operation. In addition, these schemes allow for a fault-tolerant design as well. We find that, while a neural predictor benefits from larger density, current technology parameters do not allow high dense, energy-efficient design. Thus, we discuss a range of plausible memristor characteristics that would; as the technology advances; make them practical for our application.","PeriodicalId":430420,"journal":{"name":"ACM International Conference on Computing Frontiers","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124757187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Complexity in resource allocation grows dramatically as multiple cores and threads are implemented on Multicore Multi-threaded Microprocessors (MMMP). Such complexity is escalated with variations in workload behaviors. In an effort to support a dynamic, adaptive and scalable operating system (OS) scheduling policy for MMMP, architectural strategies are proposed to construct linear models to capture workload behaviors and then schedule threads according to their resource demands. This paper describes the design through three steps: in the first step we convert a static scheduling policy into a dynamic one, which evaluates the thread mapping pattern at runtime. In the second step we employ regression models to ensure that the scheduling policy is capable of responding to the changing behaviors of threads during execution. In the final step we limit the overhead of the proposed policy by adopting a heuristic approach, thus ensure the scalability with the exponential growth of core and thread counts. The experimental results validate our proposed model in terms of throughput, adaptability and scalability. Compared with the baseline static approach, our phase-triggered scheduling policy could achieve up to 29% speedup. We also provide detailed tradeoff study between performance and overhead that system architects can reference to when target systems and specific overheads are presented.
{"title":"Scheduling optimization in multicore multithreaded microprocessors through dynamic modeling","authors":"L. Weng, Chen Liu, J. Gaudiot","doi":"10.1145/2482767.2482774","DOIUrl":"https://doi.org/10.1145/2482767.2482774","url":null,"abstract":"Complexity in resource allocation grows dramatically as multiple cores and threads are implemented on Multicore Multi-threaded Microprocessors (MMMP). Such complexity is escalated with variations in workload behaviors. In an effort to support a dynamic, adaptive and scalable operating system (OS) scheduling policy for MMMP, architectural strategies are proposed to construct linear models to capture workload behaviors and then schedule threads according to their resource demands. This paper describes the design through three steps: in the first step we convert a static scheduling policy into a dynamic one, which evaluates the thread mapping pattern at runtime. In the second step we employ regression models to ensure that the scheduling policy is capable of responding to the changing behaviors of threads during execution. In the final step we limit the overhead of the proposed policy by adopting a heuristic approach, thus ensure the scalability with the exponential growth of core and thread counts. The experimental results validate our proposed model in terms of throughput, adaptability and scalability. Compared with the baseline static approach, our phase-triggered scheduling policy could achieve up to 29% speedup. We also provide detailed tradeoff study between performance and overhead that system architects can reference to when target systems and specific overheads are presented.","PeriodicalId":430420,"journal":{"name":"ACM International Conference on Computing Frontiers","volume":"1655 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129314160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper describes an experimental study of a novel computing system (algorithm plus platform) that carries out quantum annealing, a type of adiabatic quantum computation, to solve optimization problems. We compare this system to three conventional software solvers, using instances from three NP-hard problem domains. We also describe experiments to learn how performance of the quantum annealing algorithm depends on input.
{"title":"Experimental evaluation of an adiabiatic quantum system for combinatorial optimization","authors":"Catherine C. McGeoch, Cong Wang","doi":"10.1145/2482767.2482797","DOIUrl":"https://doi.org/10.1145/2482767.2482797","url":null,"abstract":"This paper describes an experimental study of a novel computing system (algorithm plus platform) that carries out quantum annealing, a type of adiabatic quantum computation, to solve optimization problems. We compare this system to three conventional software solvers, using instances from three NP-hard problem domains. We also describe experiments to learn how performance of the quantum annealing algorithm depends on input.","PeriodicalId":430420,"journal":{"name":"ACM International Conference on Computing Frontiers","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129006819","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jie Shen, A. Varbanescu, H. Sips, M. Arntzen, D. Simons
Heterogeneous platforms integrating different processors like GPUs and multi-core CPUs become popular in high performance computing. While most applications are currently using the homogeneous parts of these platforms, we argue that there is a large class of applications that can benefit from their heterogeneity: massively parallel imbalanced applications. Such applications emerge, for example, from variable time step based numerical methods and simulations. In this paper, we present Glinda, a framework for accelerating imbalanced applications on heterogeneous computing platforms. Our framework is able to correctly detect the application workload characteristics, make choices based on the available parallel solutions and hardware configuration, and automatically obtain the optimal workload decomposition and distribution. Our experiments on parallelizing a heavily imbalanced acoustic ray tracing application show that Glinda improves application performance in multiple scenarios, achieving up to 12x speedup against manually configured parallel solutions.
{"title":"Glinda: a framework for accelerating imbalanced applications on heterogeneous platforms","authors":"Jie Shen, A. Varbanescu, H. Sips, M. Arntzen, D. Simons","doi":"10.1145/2482767.2482785","DOIUrl":"https://doi.org/10.1145/2482767.2482785","url":null,"abstract":"Heterogeneous platforms integrating different processors like GPUs and multi-core CPUs become popular in high performance computing. While most applications are currently using the homogeneous parts of these platforms, we argue that there is a large class of applications that can benefit from their heterogeneity: massively parallel imbalanced applications. Such applications emerge, for example, from variable time step based numerical methods and simulations. In this paper, we present Glinda, a framework for accelerating imbalanced applications on heterogeneous computing platforms. Our framework is able to correctly detect the application workload characteristics, make choices based on the available parallel solutions and hardware configuration, and automatically obtain the optimal workload decomposition and distribution. Our experiments on parallelizing a heavily imbalanced acoustic ray tracing application show that Glinda improves application performance in multiple scenarios, achieving up to 12x speedup against manually configured parallel solutions.","PeriodicalId":430420,"journal":{"name":"ACM International Conference on Computing Frontiers","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133095732","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
D. Pasetto, H. Franke, Weihong Qian, Zhili Guo, Honglei Guo, Dongxu Duan, Y. Ni, Yingxin Pan, Shenghua Bao, Feng Cao, Zhong Su
Governance, Risk Management and Compliance are key success factors for corporations. Every company worldwide must ensure a proper compliance level with current and future laws and regulations, but managing the dynamic nature of the regulatory environment is a challenge, for both small and medium business as well as large corporations. Specifically the challenge is knowing and interpreting which regulations impact a particular business. Governments and standard bodies keep producing new, revised legislation, and businesses today rely on employees and consultants for tracking and understanding impact on their operations. This paper introduces a novel prototype solution that addresses these concerns through the use of advanced text analytics. In particular the system is able to discover sources of regulatory content on the world wide web, track the changes to these regulations, extract metadata and semantic information and use these to provide a semantically guided comparison of regulation versions. Moreover, by leveraging the IBM DeepQA architecture, the solution is able to cross reference business objectives with the regulatory database and provide insights about the impact of new and revised laws on a company's business.
{"title":"RTS - an integrated analytic solution for managing regulation changes and their impact on business compliance","authors":"D. Pasetto, H. Franke, Weihong Qian, Zhili Guo, Honglei Guo, Dongxu Duan, Y. Ni, Yingxin Pan, Shenghua Bao, Feng Cao, Zhong Su","doi":"10.1145/2482767.2482798","DOIUrl":"https://doi.org/10.1145/2482767.2482798","url":null,"abstract":"Governance, Risk Management and Compliance are key success factors for corporations. Every company worldwide must ensure a proper compliance level with current and future laws and regulations, but managing the dynamic nature of the regulatory environment is a challenge, for both small and medium business as well as large corporations. Specifically the challenge is knowing and interpreting which regulations impact a particular business. Governments and standard bodies keep producing new, revised legislation, and businesses today rely on employees and consultants for tracking and understanding impact on their operations.\u0000 This paper introduces a novel prototype solution that addresses these concerns through the use of advanced text analytics. In particular the system is able to discover sources of regulatory content on the world wide web, track the changes to these regulations, extract metadata and semantic information and use these to provide a semantically guided comparison of regulation versions. Moreover, by leveraging the IBM DeepQA architecture, the solution is able to cross reference business objectives with the regulatory database and provide insights about the impact of new and revised laws on a company's business.","PeriodicalId":430420,"journal":{"name":"ACM International Conference on Computing Frontiers","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121442077","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Conventional communication satellite payloads have the drawback to have their architecture fixed for the lifetime of the satellite (15 years) and therefore cannot adapt to changing communication standards and market/application evolution (like multimedia applications). A way to alleviate the rigidity is the use of onboard reconfigurable technology in order to be able to modify the processing of the signals performed onboard. Additionally, the increasing use of new earth-observation and communication technologies coupled with rapidly changing customer needs require a high performance and flexible processing technology for on-board data processing. The algorithmic and processing requirements for such processing are of a magnitude larger than those that could be successfully handled by classical processors. Therefore, there is a need for a powerful and flexible processor that can process large amounts of data at high speeds, and at the same time, is reconfigurable to adapt to changes. This paper gives an overview of the development at Astrium for in-orbit applications demanding high performance processing.
{"title":"A high performance reliable dataflow based processor for space applications","authors":"M. Syed, G. Acher, T. Helfers","doi":"10.1145/2482767.2482769","DOIUrl":"https://doi.org/10.1145/2482767.2482769","url":null,"abstract":"Conventional communication satellite payloads have the drawback to have their architecture fixed for the lifetime of the satellite (15 years) and therefore cannot adapt to changing communication standards and market/application evolution (like multimedia applications). A way to alleviate the rigidity is the use of onboard reconfigurable technology in order to be able to modify the processing of the signals performed onboard. Additionally, the increasing use of new earth-observation and communication technologies coupled with rapidly changing customer needs require a high performance and flexible processing technology for on-board data processing. The algorithmic and processing requirements for such processing are of a magnitude larger than those that could be successfully handled by classical processors. Therefore, there is a need for a powerful and flexible processor that can process large amounts of data at high speeds, and at the same time, is reconfigurable to adapt to changes.\u0000 This paper gives an overview of the development at Astrium for in-orbit applications demanding high performance processing.","PeriodicalId":430420,"journal":{"name":"ACM International Conference on Computing Frontiers","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117081771","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
New many-core architectures are characterized not only by the large amount of processing elements but also by the large number and heterogeneity of resources. This new environment has prompted the development of new techniques that seek finer granularity and a greater interplay in the sharing of resources. The research proposed here will provide an analysis of these new scenarios, proposing new methodologies and solutions that leverage these new challenges in order to increase the performance and energy efficiency of modern many-core architectures.
{"title":"Strategies for improving performance and energy efficiency on a many-core","authors":"E. Garcia, G. Gao","doi":"10.1145/2482767.2482779","DOIUrl":"https://doi.org/10.1145/2482767.2482779","url":null,"abstract":"New many-core architectures are characterized not only by the large amount of processing elements but also by the large number and heterogeneity of resources. This new environment has prompted the development of new techniques that seek finer granularity and a greater interplay in the sharing of resources.\u0000 The research proposed here will provide an analysis of these new scenarios, proposing new methodologies and solutions that leverage these new challenges in order to increase the performance and energy efficiency of modern many-core architectures.","PeriodicalId":430420,"journal":{"name":"ACM International Conference on Computing Frontiers","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-05-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114544448","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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