Situation assessment and decision making (SA & DM) in mission critical scenarios is a complex cognitive task involving assessment of numerous variables which are often interdependent. Tasks are performed by individuals, teams and organizations and information is provided by different sources. Team members often perform a specific role, but must share information and a common understanding of the problem with other team members to be effective. Proper automated support could alleviate the problems of distributed cognition. This paper defines many requirements for distributed decision support systems, to support mission critical operations such as disaster recovery, personnel evacuation, and medical support during a pandemic. The paper also addresses the difficulty in developing such systems
{"title":"Requirements for distributed mission-critical decision support systems","authors":"S. White","doi":"10.1109/ECBS.2006.61","DOIUrl":"https://doi.org/10.1109/ECBS.2006.61","url":null,"abstract":"Situation assessment and decision making (SA & DM) in mission critical scenarios is a complex cognitive task involving assessment of numerous variables which are often interdependent. Tasks are performed by individuals, teams and organizations and information is provided by different sources. Team members often perform a specific role, but must share information and a common understanding of the problem with other team members to be effective. Proper automated support could alleviate the problems of distributed cognition. This paper defines many requirements for distributed decision support systems, to support mission critical operations such as disaster recovery, personnel evacuation, and medical support during a pandemic. The paper also addresses the difficulty in developing such systems","PeriodicalId":430872,"journal":{"name":"13th Annual IEEE International Symposium and Workshop on Engineering of Computer-Based Systems (ECBS'06)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114552376","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We present a design methodology for specifying embedded systems that addresses the complex nature of embedded systems design. Our approach uses modern model-based techniques to correct specifications as they are constructed, driving the engineer towards a more correct specification. We also present a concrete specification language based on this methodology
{"title":"Correct-ed through construction: a model-based approach to embedded systems reality","authors":"Ethan K. Jackson, J. Sztipanovits","doi":"10.1109/ECBS.2006.32","DOIUrl":"https://doi.org/10.1109/ECBS.2006.32","url":null,"abstract":"We present a design methodology for specifying embedded systems that addresses the complex nature of embedded systems design. Our approach uses modern model-based techniques to correct specifications as they are constructed, driving the engineer towards a more correct specification. We also present a concrete specification language based on this methodology","PeriodicalId":430872,"journal":{"name":"13th Annual IEEE International Symposium and Workshop on Engineering of Computer-Based Systems (ECBS'06)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116472605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The motivation and objective for this paper is to demonstrate "personal high performance computing (PHPC)", which requires only a smaller number of computers, resources and space in the secure wireless home networking (WHN) environment. The PHPC is based on a cluster of the 64-bit AMD machines, which can achieve the following: (a) reducing CPU time by 10%-50% for a single task; (b) minimizing the memory and hard-disk workload by 50%; (c) running 64-bit software applications successfully; (d) receiving up to 60% better performance in multi-tasking performance; (e) executing fast, robust and accurate calculations, visualization and server-side applications on 32-bit and 64-bit Windows and Linux; (f) ensuring a secure working environment (g) storing a massive amount of data (12 TB, or 12,000 GB) for database and server applications; and (h) successfully integrating with other emerging technologies such as LAN/wireless networks and entertainment systems
{"title":"Experiments and investigations for the personal high performance computing (PHPC) built on top of the 64-bit processing and clustering systems","authors":"V. Chang","doi":"10.1109/ECBS.2006.42","DOIUrl":"https://doi.org/10.1109/ECBS.2006.42","url":null,"abstract":"The motivation and objective for this paper is to demonstrate \"personal high performance computing (PHPC)\", which requires only a smaller number of computers, resources and space in the secure wireless home networking (WHN) environment. The PHPC is based on a cluster of the 64-bit AMD machines, which can achieve the following: (a) reducing CPU time by 10%-50% for a single task; (b) minimizing the memory and hard-disk workload by 50%; (c) running 64-bit software applications successfully; (d) receiving up to 60% better performance in multi-tasking performance; (e) executing fast, robust and accurate calculations, visualization and server-side applications on 32-bit and 64-bit Windows and Linux; (f) ensuring a secure working environment (g) storing a massive amount of data (12 TB, or 12,000 GB) for database and server applications; and (h) successfully integrating with other emerging technologies such as LAN/wireless networks and entertainment systems","PeriodicalId":430872,"journal":{"name":"13th Annual IEEE International Symposium and Workshop on Engineering of Computer-Based Systems (ECBS'06)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115859015","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hamoudi Kalla, J. Talpin, David Berner, L. Besnard
For complex systems that are reusing intellectual property components, functional and compositional design correctness are an important part of the design process. Common system level capture in software programming languages such as C/C++ allow for a comfortable design entry and simulation, but mere simulation is not enough to ensure proper design integration. Validating that reused components are properly connected to each other and function correctly has become a major issue for such designs and requires the use of formal methods. In this paper, we propose an approach in which we automatically translate C/C++ programs into the synchronous formalism SIGNAL, hence enabling the application of formal methods without having to deal with the complex and error prone task to build formal models by hand. The main benefit of considering the model of SIGNAL for C/C++ languages lies in the formal nature of the synchronous language SIGNAL, which supports verification and optimization techniques. The C/C++ into SIGNAL transformation process is performed in two steps. We first translate C/C++ programs into an intermediate Static Single Assignment form, and next we translate this into SIGNAL programs. Our implementation of the SIGNAL generation is inserted in the GNU compiler collection source code as an additional front end optimization pass. It does benefit from both GCC code optimization techniques as well as the optimizations of the SIGNAL compiler
{"title":"Automated translation of C/C++ models into a synchronous formalism","authors":"Hamoudi Kalla, J. Talpin, David Berner, L. Besnard","doi":"10.1109/ECBS.2006.27","DOIUrl":"https://doi.org/10.1109/ECBS.2006.27","url":null,"abstract":"For complex systems that are reusing intellectual property components, functional and compositional design correctness are an important part of the design process. Common system level capture in software programming languages such as C/C++ allow for a comfortable design entry and simulation, but mere simulation is not enough to ensure proper design integration. Validating that reused components are properly connected to each other and function correctly has become a major issue for such designs and requires the use of formal methods. In this paper, we propose an approach in which we automatically translate C/C++ programs into the synchronous formalism SIGNAL, hence enabling the application of formal methods without having to deal with the complex and error prone task to build formal models by hand. The main benefit of considering the model of SIGNAL for C/C++ languages lies in the formal nature of the synchronous language SIGNAL, which supports verification and optimization techniques. The C/C++ into SIGNAL transformation process is performed in two steps. We first translate C/C++ programs into an intermediate Static Single Assignment form, and next we translate this into SIGNAL programs. Our implementation of the SIGNAL generation is inserted in the GNU compiler collection source code as an additional front end optimization pass. It does benefit from both GCC code optimization techniques as well as the optimizations of the SIGNAL compiler","PeriodicalId":430872,"journal":{"name":"13th Annual IEEE International Symposium and Workshop on Engineering of Computer-Based Systems (ECBS'06)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117005700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Zhong-wang Zhou, G. Jin, Doudou Dong, Jinglun Zhou
Due to the difficulty of reliability analysis of multistate systems, a new method based on Bayesian networks is proposed through an example. Reliability block diagram and logic operators are firstly established according to the hierarchy of structure and function of multistate systems, and the Bayesian networks is constructed based on the reliability block diagram, distribution of components and logic operators, then the analysis is performed. The paper shows that the new method based on Bayesian networks could model generic multistate systems and basic inference techniques on Bayesian networks may be used to obtain classical parameters in reliability analysis (i.e. probability of the top event or of any subsystem, etc.). Moreover, by using Bayesian networks, some additional information can be obtained at the analysis level which could be used to perform diagnosis and complex common cause problems can be handled conveniently. The comparison with traditional method is carried out by means of an example of radar system taken from literature
{"title":"Reliability analysis of multistate systems based on Bayesian networks","authors":"Zhong-wang Zhou, G. Jin, Doudou Dong, Jinglun Zhou","doi":"10.1109/ECBS.2006.58","DOIUrl":"https://doi.org/10.1109/ECBS.2006.58","url":null,"abstract":"Due to the difficulty of reliability analysis of multistate systems, a new method based on Bayesian networks is proposed through an example. Reliability block diagram and logic operators are firstly established according to the hierarchy of structure and function of multistate systems, and the Bayesian networks is constructed based on the reliability block diagram, distribution of components and logic operators, then the analysis is performed. The paper shows that the new method based on Bayesian networks could model generic multistate systems and basic inference techniques on Bayesian networks may be used to obtain classical parameters in reliability analysis (i.e. probability of the top event or of any subsystem, etc.). Moreover, by using Bayesian networks, some additional information can be obtained at the analysis level which could be used to perform diagnosis and complex common cause problems can be handled conveniently. The comparison with traditional method is carried out by means of an example of radar system taken from literature","PeriodicalId":430872,"journal":{"name":"13th Annual IEEE International Symposium and Workshop on Engineering of Computer-Based Systems (ECBS'06)","volume":"61 28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125012330","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hassan Ghasemzadeh, Sepideh Mazrouee, M. R. Kakoee
Although the LRU replacement algorithm has been widely used in cache memory management, it is well-known for its inability to be easily implemented in hardware. Most of primary caches employ a simple block replacement algorithm like pseudo LRU to avoid the disadvantages of a complex hardware design. In this paper, we propose a novel block replacement scheme, MPLRU (modified pseudo LRU), by exploiting second chance concept in pseudo LRU algorithm. A comprehensive comparison is made between our algorithm and both true LRU and other conventional schemes such as FIFO, random and pseudo LRU. Experimental results show that MPLRU significantly reduces the number of cache misses compared to the other algorithms. Simulation results reveal that in average our algorithm can provide a value of 8.52% improvement on the miss ratio compared to the pseudo LRU algorithm. Moreover, it provides 7.93% and 11.57%performance improvement compared to FIFO and random replacement policies respectively
{"title":"Modified pseudo LRU replacement algorithm","authors":"Hassan Ghasemzadeh, Sepideh Mazrouee, M. R. Kakoee","doi":"10.1109/ECBS.2006.52","DOIUrl":"https://doi.org/10.1109/ECBS.2006.52","url":null,"abstract":"Although the LRU replacement algorithm has been widely used in cache memory management, it is well-known for its inability to be easily implemented in hardware. Most of primary caches employ a simple block replacement algorithm like pseudo LRU to avoid the disadvantages of a complex hardware design. In this paper, we propose a novel block replacement scheme, MPLRU (modified pseudo LRU), by exploiting second chance concept in pseudo LRU algorithm. A comprehensive comparison is made between our algorithm and both true LRU and other conventional schemes such as FIFO, random and pseudo LRU. Experimental results show that MPLRU significantly reduces the number of cache misses compared to the other algorithms. Simulation results reveal that in average our algorithm can provide a value of 8.52% improvement on the miss ratio compared to the pseudo LRU algorithm. Moreover, it provides 7.93% and 11.57%performance improvement compared to FIFO and random replacement policies respectively","PeriodicalId":430872,"journal":{"name":"13th Annual IEEE International Symposium and Workshop on Engineering of Computer-Based Systems (ECBS'06)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128482050","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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