This paper presents a detailed technical description of a large-scale evolvable hardware system for evolving complex digital circuits directly in silicon at high speed. The core of the system is a three-dimensional array of reconfigurable logic with 5.2 million fine-grained function units and 1.2 Gbyte distributed memory. An application example is presented, describing an evolution of cellular automata based neural networks and a simulation of a hardware-based 75-million neuron artificial brain in real time. The system was developed in 1997-2000 at Genobyte, Inc. (Boulder, Colorado) for ATR HIP (Kyoto, Japan), and is marketed as CAM-Brain Machine (CBM). CBM features a true run-time logic reconfiguration, a hardware implementation of chromosome crossover and mutation, and a hardware-based fitness evaluation. CBM also features a sophisticated genotype-phenotype mapping through the process of embryonic growth.
本文介绍了一种大规模可演化硬件系统的详细技术描述，该系统可直接在硅上高速演化复杂的数字电路。该系统的核心是一个可重构逻辑的三维阵列，拥有520万个细粒度功能单元和1.2 g字节的分布式内存。给出了一个应用实例，描述了基于元胞自动机的神经网络的进化和基于硬件的7500万个神经元人工大脑的实时仿真。该系统于1997-2000年在Genobyte公司(Boulder, Colorado)为ATR HIP (Kyoto, Japan)开发，并以CAM-Brain Machine (CBM)的名称销售。CBM具有真正的运行时逻辑重新配置、染色体交叉和突变的硬件实现以及基于硬件的适应度评估。CBM还通过胚胎生长过程具有复杂的基因型-表型定位。
{"title":"Evolving hardware on a large scale","authors":"M. Korkin, Gary Fehr, G. Jeffery","doi":"10.1109/EH.2000.869355","DOIUrl":"https://doi.org/10.1109/EH.2000.869355","url":null,"abstract":"This paper presents a detailed technical description of a large-scale evolvable hardware system for evolving complex digital circuits directly in silicon at high speed. The core of the system is a three-dimensional array of reconfigurable logic with 5.2 million fine-grained function units and 1.2 Gbyte distributed memory. An application example is presented, describing an evolution of cellular automata based neural networks and a simulation of a hardware-based 75-million neuron artificial brain in real time. The system was developed in 1997-2000 at Genobyte, Inc. (Boulder, Colorado) for ATR HIP (Kyoto, Japan), and is marketed as CAM-Brain Machine (CBM). CBM features a true run-time logic reconfiguration, a hardware implementation of chromosome crossover and mutation, and a hardware-based fitness evaluation. CBM also features a sophisticated genotype-phenotype mapping through the process of embryonic growth.","PeriodicalId":432338,"journal":{"name":"Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware","volume":"71 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128959663","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ron Levy, S. Lepri, E. Sanchez, Gilles Ritter, M. Sipper
We describe a completely autonomous evolutionary hardware system, which is able to recognize handwritten decimal digits. The system can adapt itself to different users on the fly. A working prototype has been implemented on an FPGA using VHDL, following the positive results of a C-based simulation.
{"title":"State of the art: an evolving FPGA-based board for handwritten-digit recognition","authors":"Ron Levy, S. Lepri, E. Sanchez, Gilles Ritter, M. Sipper","doi":"10.1109/EH.2000.869361","DOIUrl":"https://doi.org/10.1109/EH.2000.869361","url":null,"abstract":"We describe a completely autonomous evolutionary hardware system, which is able to recognize handwritten decimal digits. The system can adapt itself to different users on the fly. A working prototype has been implemented on an FPGA using VHDL, following the positive results of a C-based simulation.","PeriodicalId":432338,"journal":{"name":"Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122578206","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper introduces a new methodology of evolving electronic circuits by which the process of evolutionary design is guaranteed to produce a functionally correct solution. The method employs a mapping to represent an electronic circuit on an array of logic cells that is further encoded within a genotype. The mapping is many-to-one and thus there are many genotypes that have equal fitness values. Genotypes with equal fitness values define subgraphs in the resulting fitness landscapes referred to as neutral networks. This is further used in the design of a neutral network that connects the conventional with other more efficient designs. To explore such a network a navigation strategy is defined by which the space of all functionally correct circuits can be explored. The paper shows that very efficient digital circuits can be obtained by evolving from the conventional designs. Results for several binary multiplier circuits such as the three and four-bit multipliers are reported. The evolved solution for the three-bit multiplier consists of 23 two-input logic gates that in terms of number of two-input gates used is 23.3% more efficient than the most efficient known conventional design. The logic operators required to implement this circuit are 14 ANDs, 9 XORs, and 2 inversions (NOT). The evolved four-bit multiplier consists of 57 two-input logic gates that is 10.9% more efficient (in terms of number of two-input gates used) than the most efficient known conventional design. The optimal size of the target circuits is also studied by measuring the length of the neutral walks from the obtained designs.
{"title":"Towards the automatic design of more efficient digital circuits","authors":"Vesselin K. Vassilev, D. Job, J. Miller","doi":"10.1109/EH.2000.869353","DOIUrl":"https://doi.org/10.1109/EH.2000.869353","url":null,"abstract":"This paper introduces a new methodology of evolving electronic circuits by which the process of evolutionary design is guaranteed to produce a functionally correct solution. The method employs a mapping to represent an electronic circuit on an array of logic cells that is further encoded within a genotype. The mapping is many-to-one and thus there are many genotypes that have equal fitness values. Genotypes with equal fitness values define subgraphs in the resulting fitness landscapes referred to as neutral networks. This is further used in the design of a neutral network that connects the conventional with other more efficient designs. To explore such a network a navigation strategy is defined by which the space of all functionally correct circuits can be explored. The paper shows that very efficient digital circuits can be obtained by evolving from the conventional designs. Results for several binary multiplier circuits such as the three and four-bit multipliers are reported. The evolved solution for the three-bit multiplier consists of 23 two-input logic gates that in terms of number of two-input gates used is 23.3% more efficient than the most efficient known conventional design. The logic operators required to implement this circuit are 14 ANDs, 9 XORs, and 2 inversions (NOT). The evolved four-bit multiplier consists of 57 two-input logic gates that is 10.9% more efficient (in terms of number of two-input gates used) than the most efficient known conventional design. The optimal size of the target circuits is also studied by measuring the length of the neutral walks from the obtained designs.","PeriodicalId":432338,"journal":{"name":"Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware","volume":"27 4 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130349359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Active flow control can provide a leap in the performance of engineering configurations. Although a number of sensor and actuator configurations have been proposed the task of identifying optimal parameters for control devices is based on engineering intuition usually gathered from uncontrolled flow experiments. We propose a clustering genetic algorithm that adaptively identifies critical points in the controlled flow field and adjusts the actuator parameters through an evolutionary process. We demonstrate the capabilities of the algorithm for the fundamental prototypical problem of an actively controlled circular cylinder. The flow is controlled using surface-mounted vortex generators; the actuators used are belts mounted on the cylinder surface, that modify the tangential velocity on the cylinder surface, and jet actuators, that modify the normal velocity component on the surface. The proposed genetic algorithm performs the optimization of the actuators parameters, yielding up to 50% drag reduction. At the same time the genetic algorithm performs a sensitivity analysis of the optima it finds, thus allowing a deeper understanding of the underlying physics and also an estimation of which actuator would be easier to implement in a real experiment.
{"title":"A clustering genetic algorithm for actuator optimization in flow control","authors":"M. Milano, P. Koumoutsakos","doi":"10.1109/EH.2000.869364","DOIUrl":"https://doi.org/10.1109/EH.2000.869364","url":null,"abstract":"Active flow control can provide a leap in the performance of engineering configurations. Although a number of sensor and actuator configurations have been proposed the task of identifying optimal parameters for control devices is based on engineering intuition usually gathered from uncontrolled flow experiments. We propose a clustering genetic algorithm that adaptively identifies critical points in the controlled flow field and adjusts the actuator parameters through an evolutionary process. We demonstrate the capabilities of the algorithm for the fundamental prototypical problem of an actively controlled circular cylinder. The flow is controlled using surface-mounted vortex generators; the actuators used are belts mounted on the cylinder surface, that modify the tangential velocity on the cylinder surface, and jet actuators, that modify the normal velocity component on the surface. The proposed genetic algorithm performs the optimization of the actuators parameters, yielding up to 50% drag reduction. At the same time the genetic algorithm performs a sensitivity analysis of the optima it finds, thus allowing a deeper understanding of the underlying physics and also an estimation of which actuator would be easier to implement in a real experiment.","PeriodicalId":432338,"journal":{"name":"Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129960285","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We are interested in discovering how and why circuits developed using evolutionary methods tend to be more robust than hand designed ones. To this end, we compare evolved circuits to known, minimal sorting networks. We introduce a new, size-independent metric, called bitwise stability (BS), which measures how well a network performed when subjected to real-world types of errors. In particular, we examine stuck-on-one, stuck-on-zero and passthrough errors, a generalization of a short circuit. Networks were evolved using tree structured and linear encoded chromosomes. We found that evolution improves bitwise stability and that tree structures tend to confer more bitwise stability than linear structured chromosomes. We discuss how the size of a sorting network affects its robustness and our discovery that bigger does not necessarily mean better.
{"title":"Size versus robustness in evolved sorting networks: is bigger better?","authors":"J. Masner, J. Cavalieri, J. Frenzel, J. Foster","doi":"10.1109/EH.2000.869345","DOIUrl":"https://doi.org/10.1109/EH.2000.869345","url":null,"abstract":"We are interested in discovering how and why circuits developed using evolutionary methods tend to be more robust than hand designed ones. To this end, we compare evolved circuits to known, minimal sorting networks. We introduce a new, size-independent metric, called bitwise stability (BS), which measures how well a network performed when subjected to real-world types of errors. In particular, we examine stuck-on-one, stuck-on-zero and passthrough errors, a generalization of a short circuit. Networks were evolved using tree structured and linear encoded chromosomes. We found that evolution improves bitwise stability and that tree structures tend to confer more bitwise stability than linear structured chromosomes. We discuss how the size of a sorting network affects its robustness and our discovery that bigger does not necessarily mean better.","PeriodicalId":432338,"journal":{"name":"Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129834328","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Advantages of self-reconfigurable modular robots over conventional robots include physical adaptability, robustness in the presence of failures, and economies of scale. Creating control software for modular robots is one of the central challenges to realizing their potential advantages. Modular robots differ enough from traditional robots that new techniques must be found to create software to control them. The novel difficulties are due to the fact that modular robots are ideally controlled in a decentralized manner, dynamically change their connectivity topology, may contain hundreds or thousands of modules, and are expected to perform tasks properly even when some modules fail. We demonstrate the use of genetic programming to automatically create distributed controllers for self-reconfigurable modular robots.
{"title":"Design of decentralized controllers for self-reconfigurable modular robots using genetic programming","authors":"F. H. Bennett, E. Rieffel","doi":"10.1109/EH.2000.869341","DOIUrl":"https://doi.org/10.1109/EH.2000.869341","url":null,"abstract":"Advantages of self-reconfigurable modular robots over conventional robots include physical adaptability, robustness in the presence of failures, and economies of scale. Creating control software for modular robots is one of the central challenges to realizing their potential advantages. Modular robots differ enough from traditional robots that new techniques must be found to create software to control them. The novel difficulties are due to the fact that modular robots are ideally controlled in a decentralized manner, dynamically change their connectivity topology, may contain hundreds or thousands of modules, and are expected to perform tasks properly even when some modules fail. We demonstrate the use of genetic programming to automatically create distributed controllers for self-reconfigurable modular robots.","PeriodicalId":432338,"journal":{"name":"Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121421354","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Milton Jonathan, M. Pacheco, M. Vellasco, R. Zebulum
This paper reviews the multiobjective fitness evaluation method called energy minimization and presents an analysis of the method's behavior when used in a genetic algorithm applied to the synthesis of single-ended Miller operational amplifiers. A modified model is proposed in order to overcome some of the weaknesses pointed out and improve the model's performance. Finally, experimental results are presented and analyzed, leading to an overall evaluation of the benefits provided by the proposed modifications.
{"title":"Multiobjective optimization techniques: a study of the energy minimization method and its application to the synthesis of ota amplifiers","authors":"Milton Jonathan, M. Pacheco, M. Vellasco, R. Zebulum","doi":"10.1109/EH.2000.869351","DOIUrl":"https://doi.org/10.1109/EH.2000.869351","url":null,"abstract":"This paper reviews the multiobjective fitness evaluation method called energy minimization and presents an analysis of the method's behavior when used in a genetic algorithm applied to the synthesis of single-ended Miller operational amplifiers. A modified model is proposed in order to overcome some of the weaknesses pointed out and improve the model's performance. Finally, experimental results are presented and analyzed, leading to an overall evaluation of the benefits provided by the proposed modifications.","PeriodicalId":432338,"journal":{"name":"Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123545254","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This paper demonstrates that generic programming can be used to create a circuit-constructing computer program that contains both conditional operations and inputs (free variables). The conditional operations and free variables enable a single genetically evolved program to yield functionally and topologically different electrical circuits. The conditional operations can trigger the execution of alternative sequences of steps based on the particular values of the free variables. The particular values of the free variables can also determine the component value of the circuit's components. Thus, a single evolved computer program can represent the solution to many instances of a problem. This principle is illustrated by evolving a single computer program that yields a lowpass or a highpass filter whose passband and stopband boundaries depend on the program's inputs.
{"title":"Use of conditional developmental operators and free variables in automatically synthesizing generalized circuits using genetic programming","authors":"J. Koza, Jessen Yu, W. Mydlowec, M. A. Keane","doi":"10.1109/EH.2000.869337","DOIUrl":"https://doi.org/10.1109/EH.2000.869337","url":null,"abstract":"This paper demonstrates that generic programming can be used to create a circuit-constructing computer program that contains both conditional operations and inputs (free variables). The conditional operations and free variables enable a single genetically evolved program to yield functionally and topologically different electrical circuits. The conditional operations can trigger the execution of alternative sequences of steps based on the particular values of the free variables. The particular values of the free variables can also determine the component value of the circuit's components. Thus, a single evolved computer program can represent the solution to many instances of a problem. This principle is illustrated by evolving a single computer program that yields a lowpass or a highpass filter whose passband and stopband boundaries depend on the program's inputs.","PeriodicalId":432338,"journal":{"name":"Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125533369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
H. D. Garis, A. Buller, Thierry Dob, Jean-Christophe Honlet, Padma Guttikonda, Derek Decesare
This paper introduces a concept which we believe will play a fundamental role in the growing field of "evolutionary engineering", namely the idea that there are limits to what can be evolved using a finite number of bits in a chromosome. For example, if one tries to evolve a neural network circuit module to give a time varying analog output signal which tracks an analog output time varying target signal, then the actual evolved output curve will follow the target curve quite well for a certain time period, then diverge. If one puts more bits into the chromosome used to evolve the signal, then The evolved signal will track the target signal for longer, but again will eventually diverge. Hence there is a finite "evolvable capacity" for a module evolved with a given number of bits. We label this concept "modular evolvable capacity" or simply MEC. MECs are important when one attempts to assemble large numbers of evolved modules to build such systems as artificial brains. STARLAB will attempt to use its CAM-Brain Machine (CBM) to evolve and assemble 64000 such modules to build an artificial brain. The fact that each module has its MEC, places constraints upon what "evolutionary engineers (EEs)", or in this case "brain architects (BAs)" can do. Such limits are unavoidable and have a fundamental practical impact on the daily work of EEs and BAs. This paper aims to show how multimodule systems with effectively unlimited evolvable capacities may be buildable using modules with limited MECs.
{"title":"Building multimodule systems with unlimited evolvable capacities from modules with limited evolvable capacities (MECs)","authors":"H. D. Garis, A. Buller, Thierry Dob, Jean-Christophe Honlet, Padma Guttikonda, Derek Decesare","doi":"10.1109/EH.2000.869360","DOIUrl":"https://doi.org/10.1109/EH.2000.869360","url":null,"abstract":"This paper introduces a concept which we believe will play a fundamental role in the growing field of \"evolutionary engineering\", namely the idea that there are limits to what can be evolved using a finite number of bits in a chromosome. For example, if one tries to evolve a neural network circuit module to give a time varying analog output signal which tracks an analog output time varying target signal, then the actual evolved output curve will follow the target curve quite well for a certain time period, then diverge. If one puts more bits into the chromosome used to evolve the signal, then The evolved signal will track the target signal for longer, but again will eventually diverge. Hence there is a finite \"evolvable capacity\" for a module evolved with a given number of bits. We label this concept \"modular evolvable capacity\" or simply MEC. MECs are important when one attempts to assemble large numbers of evolved modules to build such systems as artificial brains. STARLAB will attempt to use its CAM-Brain Machine (CBM) to evolve and assemble 64000 such modules to build an artificial brain. The fact that each module has its MEC, places constraints upon what \"evolutionary engineers (EEs)\", or in this case \"brain architects (BAs)\" can do. Such limits are unavoidable and have a fundamental practical impact on the daily work of EEs and BAs. This paper aims to show how multimodule systems with effectively unlimited evolvable capacities may be buildable using modules with limited MECs.","PeriodicalId":432338,"journal":{"name":"Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129500259","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
N. Marston, E. Takahashi, M. Murakawa, Y. Kasai, T. Higuchi, T. Adachi, K. Takasuka
Genetic-algorithm based techniques have been used to successfully calibrate both analogue and digital VLSI chips. This paper investigates the potential of applying the developed techniques to a generic high-speed digital system, which comprises an analogue-to-digital converter and digital logic integrated on a single chip. It is concluded that evolvable calibration techniques are most likely to be applied to VLSI design where the actual value of a variable is critical rather than the more common instance of the variable having to be greater than a given value or the quantity of interest is the ratio of two matched components. Probably the best example of this is delay. As clock frequencies approach 1 GHz variation of buffer delay and clock skew become increasingly important.
{"title":"An evolutionary approach to GHz digital systems","authors":"N. Marston, E. Takahashi, M. Murakawa, Y. Kasai, T. Higuchi, T. Adachi, K. Takasuka","doi":"10.1109/EH.2000.869350","DOIUrl":"https://doi.org/10.1109/EH.2000.869350","url":null,"abstract":"Genetic-algorithm based techniques have been used to successfully calibrate both analogue and digital VLSI chips. This paper investigates the potential of applying the developed techniques to a generic high-speed digital system, which comprises an analogue-to-digital converter and digital logic integrated on a single chip. It is concluded that evolvable calibration techniques are most likely to be applied to VLSI design where the actual value of a variable is critical rather than the more common instance of the variable having to be greater than a given value or the quantity of interest is the ratio of two matched components. Probably the best example of this is delay. As clock frequencies approach 1 GHz variation of buffer delay and clock skew become increasingly important.","PeriodicalId":432338,"journal":{"name":"Proceedings. The Second NASA/DoD Workshop on Evolvable Hardware","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-07-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131414427","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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