Pub Date : 1995-04-19DOI: 10.1109/ICAPP.1995.472240
V. Murthy, E. Krishnamurthy
A transactional paradigm is suggested for computer-assisted parallelization of programs and register-cache scheduling. It can serve as a building tool for pipelining, data parallellism, or generic parallellism in a variety of architectures and the cost of execution can be estimated realistically.<>
{"title":"Transactional paradigm: applications to distributed programming","authors":"V. Murthy, E. Krishnamurthy","doi":"10.1109/ICAPP.1995.472240","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472240","url":null,"abstract":"A transactional paradigm is suggested for computer-assisted parallelization of programs and register-cache scheduling. It can serve as a building tool for pipelining, data parallellism, or generic parallellism in a variety of architectures and the cost of execution can be estimated realistically.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"34 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121647291","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-04-19DOI: 10.1109/ICAPP.1995.472168
T. Braunl
Parallaxis is a machine-independent language for data-parallel programming, based on sequential Modula-2. Programming in Parallaxis is done on a level of abstraction with virtual processors and virtual connections, which may be defined by the application programmer. This paper describes Parallaxis-III, the current version of the language definition, together with a number of parallel sample algorithms.<>
{"title":"Parallaxis-III: a structured data-parallel programming language","authors":"T. Braunl","doi":"10.1109/ICAPP.1995.472168","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472168","url":null,"abstract":"Parallaxis is a machine-independent language for data-parallel programming, based on sequential Modula-2. Programming in Parallaxis is done on a level of abstraction with virtual processors and virtual connections, which may be defined by the application programmer. This paper describes Parallaxis-III, the current version of the language definition, together with a number of parallel sample algorithms.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123786744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-04-19DOI: 10.1109/ICAPP.1995.472298
P. Bonnin, E. Pissaloux, T. Dillon
The research presented here focuses on the general problem of finding tools and methods for parallel machine evaluation. "Benchmarks" are the most popular tools for machines speed comparison, unfortunately, they do not give any information on the most convenient hardware structures for implementation of a given vision problem. This paper tries to overcome this problem, and proposes a characterization of a tool for the evaluation of parallel architecture (which is a generalization of the benchmark concept); however, here we focus on the area of computer vision.<>
{"title":"Towards a choice of region algorithms for the evaluation of parallel vision architectures","authors":"P. Bonnin, E. Pissaloux, T. Dillon","doi":"10.1109/ICAPP.1995.472298","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472298","url":null,"abstract":"The research presented here focuses on the general problem of finding tools and methods for parallel machine evaluation. \"Benchmarks\" are the most popular tools for machines speed comparison, unfortunately, they do not give any information on the most convenient hardware structures for implementation of a given vision problem. This paper tries to overcome this problem, and proposes a characterization of a tool for the evaluation of parallel architecture (which is a generalization of the benchmark concept); however, here we focus on the area of computer vision.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122500039","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-04-19DOI: 10.1109/ICAPP.1995.472219
Chi-Chang Chen, Jianer Chen
In this paper, we present a homomorphism from a higher dimensional de Bruijn graph to a lower dimensional de Bruijn graph. This homomorphism is simple and efficient. Applications of this homomorphism on embedding the large size complete binary trees, rings, and shuffle-exchange networks to the smaller binary de Bruijn networks are presented.<>
{"title":"A homomorphism of the de Bruijn graphs and its applications","authors":"Chi-Chang Chen, Jianer Chen","doi":"10.1109/ICAPP.1995.472219","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472219","url":null,"abstract":"In this paper, we present a homomorphism from a higher dimensional de Bruijn graph to a lower dimensional de Bruijn graph. This homomorphism is simple and efficient. Applications of this homomorphism on embedding the large size complete binary trees, rings, and shuffle-exchange networks to the smaller binary de Bruijn networks are presented.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122900840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-04-19DOI: 10.1109/ICAPP.1995.472268
M. Alderighi, D. Crosetto, F. d'Ovidio, E. Gummati, G. Sechi
Recent years have witnessed a growing interest in the study of neural networks. A lot of work has been on understanding how various computational problems can be solved adopting these models. This paper describes an asynchronous feedback neural network, the photon event identification problem in an astrophysics experiment, and shows some promising results.<>
{"title":"A feedback neural network for signal processing and event recognition","authors":"M. Alderighi, D. Crosetto, F. d'Ovidio, E. Gummati, G. Sechi","doi":"10.1109/ICAPP.1995.472268","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472268","url":null,"abstract":"Recent years have witnessed a growing interest in the study of neural networks. A lot of work has been on understanding how various computational problems can be solved adopting these models. This paper describes an asynchronous feedback neural network, the photon event identification problem in an astrophysics experiment, and shows some promising results.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115160358","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-04-19DOI: 10.1109/ICAPP.1995.472285
C. Chan, Meiling Zhu
The paper proposes an architecture and implementation of a motion control system, with a master-slave multiprocessor mode. Some major problems which must be considered in multiprocessor systems design, including multiprocessor system architecture, interconnection network, hardware circuit design and software design are studied.<>
{"title":"Implementation of real-time parallel processing in a motion control system","authors":"C. Chan, Meiling Zhu","doi":"10.1109/ICAPP.1995.472285","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472285","url":null,"abstract":"The paper proposes an architecture and implementation of a motion control system, with a master-slave multiprocessor mode. Some major problems which must be considered in multiprocessor systems design, including multiprocessor system architecture, interconnection network, hardware circuit design and software design are studied.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"188 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133526561","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-04-19DOI: 10.1109/ICAPP.1995.472288
P. Tagle, N. K. Sharma
To support broadband integrated services digital networks (B-ISDN), switching networks must have the ability to provide both multipoint connections (multicasting) and point-to-point connections (unicasting). This paper proposes a multicast switching network based on a recently proposed routing network which consists of two banyan networks with links at every stage to allow cell transfer to and from each banyan plane, thereby offering multiple paths between each input-output pair. The proposed multicast network employs the copy and routing networks in a parallel configuration. This approach allows for unicast cells to proceed to the routing network without additional delay and keeps the copy network free of unicast traffic which results in a larger amount of the multicast requests to be successfully replicated. Using simulations, the proposed multicast network was shown to offer better performance than other networks in terms of cell loss rates.<>
{"title":"A multicast switching network for B-ISDN","authors":"P. Tagle, N. K. Sharma","doi":"10.1109/ICAPP.1995.472288","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472288","url":null,"abstract":"To support broadband integrated services digital networks (B-ISDN), switching networks must have the ability to provide both multipoint connections (multicasting) and point-to-point connections (unicasting). This paper proposes a multicast switching network based on a recently proposed routing network which consists of two banyan networks with links at every stage to allow cell transfer to and from each banyan plane, thereby offering multiple paths between each input-output pair. The proposed multicast network employs the copy and routing networks in a parallel configuration. This approach allows for unicast cells to proceed to the routing network without additional delay and keeps the copy network free of unicast traffic which results in a larger amount of the multicast requests to be successfully replicated. Using simulations, the proposed multicast network was shown to offer better performance than other networks in terms of cell loss rates.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133664860","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-04-19DOI: 10.1109/ICAPP.1995.472282
Henry Y. H. Chuang, Ling Chen
The Euclidean distance transform (EDT) converts a binary image into one where each pixel has a value equal to its Euclidean distance to the nearest foreground pixel. A parallel EDT algorithm on SIMD hypercube computer is presented here. For an n/spl times/n image, the algorithm has a time complexity of O(n) on an n/sup 2/ nodes machine. With modifications to minimize dependency among partitions, the algorithm can be adapted to compute large EDT problems on smaller hypercubes. On a hypercube of t/sup 2/ nodes, the time complexity of the modified algorithm is O(n/sup 2//t log n/t).<>
{"title":"SIMD hypercube algorithm for complete Euclidean distance transform","authors":"Henry Y. H. Chuang, Ling Chen","doi":"10.1109/ICAPP.1995.472282","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472282","url":null,"abstract":"The Euclidean distance transform (EDT) converts a binary image into one where each pixel has a value equal to its Euclidean distance to the nearest foreground pixel. A parallel EDT algorithm on SIMD hypercube computer is presented here. For an n/spl times/n image, the algorithm has a time complexity of O(n) on an n/sup 2/ nodes machine. With modifications to minimize dependency among partitions, the algorithm can be adapted to compute large EDT problems on smaller hypercubes. On a hypercube of t/sup 2/ nodes, the time complexity of the modified algorithm is O(n/sup 2//t log n/t).<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"47 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133992065","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-04-19DOI: 10.1109/ICAPP.1995.472260
Seong Leong Ng, B. Dewar
We propose a fault tolerant multistage interconnection network (MIN) design that utilises load sharing amongst multiple buffered banyan switch planes, which provides excellent performance and good reliability allows on-line repair and easy maintenance, and offers an easy and effective way to implement priority traffic transmission. Our simulations clearly show that replicated load sharing shared buffered banyan networks have better performance than shared buffered banyan networks employing speedup. Analytical reliability results without repair for these systems are compared to those of an augmented delta network using speedup. The steady state equations to calculate the availability, mean time to failure (MTTF), and mean time to repair (MTTR) of these systems is also presented.<>
{"title":"A fault tolerant load sharing replicated buffered banyan network","authors":"Seong Leong Ng, B. Dewar","doi":"10.1109/ICAPP.1995.472260","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472260","url":null,"abstract":"We propose a fault tolerant multistage interconnection network (MIN) design that utilises load sharing amongst multiple buffered banyan switch planes, which provides excellent performance and good reliability allows on-line repair and easy maintenance, and offers an easy and effective way to implement priority traffic transmission. Our simulations clearly show that replicated load sharing shared buffered banyan networks have better performance than shared buffered banyan networks employing speedup. Analytical reliability results without repair for these systems are compared to those of an augmented delta network using speedup. The steady state equations to calculate the availability, mean time to failure (MTTF), and mean time to repair (MTTR) of these systems is also presented.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123615069","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-04-19DOI: 10.1109/ICAPP.1995.472186
J. G. Solheim, G. Myklebust
An important property of a parallel computer system, is the interprocessor communication network. This paper addresses the reconfigurable aspects of the RENNS Communication Subsystem. The Subsystem is implemented in Logic Cell Arrays, LCAs, and is therefore reconfigurable to meet the requirements of different applications. Two of the training algorithms for Artificial Neural Networks implemented on RENNS, Back Propagation and Self-Organizing Maps, are briefly described, and it is shown how the communication system can be configured to speed up these algorithms.<>
{"title":"RENNS-a reconfigurable computer system for artificial neural networks","authors":"J. G. Solheim, G. Myklebust","doi":"10.1109/ICAPP.1995.472186","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472186","url":null,"abstract":"An important property of a parallel computer system, is the interprocessor communication network. This paper addresses the reconfigurable aspects of the RENNS Communication Subsystem. The Subsystem is implemented in Logic Cell Arrays, LCAs, and is therefore reconfigurable to meet the requirements of different applications. Two of the training algorithms for Artificial Neural Networks implemented on RENNS, Back Propagation and Self-Organizing Maps, are briefly described, and it is shown how the communication system can be configured to speed up these algorithms.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"117 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122014718","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：