Pub Date : 1995-04-19DOI: 10.1109/ICAPP.1995.472171
P. Faudemay, L. Winckel
In this paper, we present an abstract model of the RAPID-2 SIMD architecture. RAPID-2 is a massively parallel add-on board for PCs. It implements a "paginated set-associative" model of architecture, and has systolic capabilities. The L1 language implements the abstract model. L1 is a co-specification language for the programming and micro-programming of RAPID-2. It is derived from C. In order to check their semantic, L1 programs can be emulated in a C++ environment. In the near future, they should be compiled into C application programs and the corresponding microprograms.<>
{"title":"A high level language for the RAPID-2 massively parallel accelerator board","authors":"P. Faudemay, L. Winckel","doi":"10.1109/ICAPP.1995.472171","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472171","url":null,"abstract":"In this paper, we present an abstract model of the RAPID-2 SIMD architecture. RAPID-2 is a massively parallel add-on board for PCs. It implements a \"paginated set-associative\" model of architecture, and has systolic capabilities. The L1 language implements the abstract model. L1 is a co-specification language for the programming and micro-programming of RAPID-2. It is derived from C. In order to check their semantic, L1 programs can be emulated in a C++ environment. In the near future, they should be compiled into C application programs and the corresponding microprograms.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126469071","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-04-19DOI: 10.1109/ICAPP.1995.472167
M. Esonu, A. Al-Khalili, S. Hariri
Progress in VLSI and WSI technologies has resulted in the manufacture of special purpose VLSI chips with multiple copies of low-cost processors. These processors can be used to design high performance systems such as systolic arrays. This paper proposes a new systematic approach which can be used to detect and correct errors in systolic array architectures. The approach relies on space-time mapping of algorithms into systolic arrays. Fault-tolerant algorithms are designed by introducing redundant computations at the algorithmic level. This is done by deriving several versions of a given algorithm, each of which can be mapped into respective systolic architecture. Fault-tolerant systolic array is constructed by merging the corresponding systolic array of several versions of the algorithm.<>
{"title":"Mapping nested loop algorithms into fault-tolerant systolic array architectures","authors":"M. Esonu, A. Al-Khalili, S. Hariri","doi":"10.1109/ICAPP.1995.472167","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472167","url":null,"abstract":"Progress in VLSI and WSI technologies has resulted in the manufacture of special purpose VLSI chips with multiple copies of low-cost processors. These processors can be used to design high performance systems such as systolic arrays. This paper proposes a new systematic approach which can be used to detect and correct errors in systolic array architectures. The approach relies on space-time mapping of algorithms into systolic arrays. Fault-tolerant algorithms are designed by introducing redundant computations at the algorithmic level. This is done by deriving several versions of a given algorithm, each of which can be mapped into respective systolic architecture. Fault-tolerant systolic array is constructed by merging the corresponding systolic array of several versions of the algorithm.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"2014 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128024685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-04-19DOI: 10.1109/ICAPP.1995.472215
W. Liang, B. McKay
It appears that no NC algorithms have previously appeared for testing a directed graph for k-edge connectivity or k-vertex connectivity, even for fixed k>1. Using an elementary flow method we give such algorithms, with time complexity O(k log n) using nP(n,m) or (n+k/sup 2/)P(n,m) processors, respectively. Here, n is the number of vertices, m is the number of edges, P(n,m) is the number of processors needed to find some path in time O(log n) time between two specified vertices in a directed graph with O(n) vertices and O(m) edges, and the computation model is a CRCW PRAM. These algorithms of course apply also to undirected graphs, but using sparse certificates we can improve the factors P(n,m) to P(n,kn) for both types of connectivity. This is better in time by a factor of O(k) over previous algorithms for undirected graphs. We also note that edge connectivity is NC-reducible to vertex connectivity even if k is not fixed.<>
{"title":"Fast parallel algorithms for testing k-connectivity of directed and undirected graphs","authors":"W. Liang, B. McKay","doi":"10.1109/ICAPP.1995.472215","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472215","url":null,"abstract":"It appears that no NC algorithms have previously appeared for testing a directed graph for k-edge connectivity or k-vertex connectivity, even for fixed k>1. Using an elementary flow method we give such algorithms, with time complexity O(k log n) using nP(n,m) or (n+k/sup 2/)P(n,m) processors, respectively. Here, n is the number of vertices, m is the number of edges, P(n,m) is the number of processors needed to find some path in time O(log n) time between two specified vertices in a directed graph with O(n) vertices and O(m) edges, and the computation model is a CRCW PRAM. These algorithms of course apply also to undirected graphs, but using sparse certificates we can improve the factors P(n,m) to P(n,kn) for both types of connectivity. This is better in time by a factor of O(k) over previous algorithms for undirected graphs. We also note that edge connectivity is NC-reducible to vertex connectivity even if k is not fixed.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127287316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-04-19DOI: 10.1109/ICAPP.1995.472214
C. Mazzoni, H. Essafi, P. Julien, O. Jamet
The aim of this work is to reduce the computation time needed to produce the Digital Elevation Models (DEM) by using a parallel machine. It is made in collaboration between the French "Institut Geographique National" (IGN) and LETI-DEIN, a department of the French Atomic Energy Commission (CEA). The IGN has developed a system which provides accurate DEM, that is used to produce the commercialized topographic map. The kernel of this system is the correlator. The correlator is a part of software which automatically matches pairs of homologous points (i.e. a pair of points representing the same ground detail), and supplies disparities. Nevertheless the correlator is expensive in computing time. CEA-LETI. is involved in parallel architecture and image processing and has developed a SIMD (Single Instruction Multiple Data) parallel architecture called SYMPATI 2. This structure constitute the kernel of the parallel OPENVISION system that is commercialized by Centralp Automatisme. In order to reduce the computation time and to produce the DEM with the same accuracy than the scalar approach, this two partners tried to parallize the IGN's correlator on the OPENVISION system.<>
{"title":"Stereocorrelation on the parallel OPENVISION system","authors":"C. Mazzoni, H. Essafi, P. Julien, O. Jamet","doi":"10.1109/ICAPP.1995.472214","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472214","url":null,"abstract":"The aim of this work is to reduce the computation time needed to produce the Digital Elevation Models (DEM) by using a parallel machine. It is made in collaboration between the French \"Institut Geographique National\" (IGN) and LETI-DEIN, a department of the French Atomic Energy Commission (CEA). The IGN has developed a system which provides accurate DEM, that is used to produce the commercialized topographic map. The kernel of this system is the correlator. The correlator is a part of software which automatically matches pairs of homologous points (i.e. a pair of points representing the same ground detail), and supplies disparities. Nevertheless the correlator is expensive in computing time. CEA-LETI. is involved in parallel architecture and image processing and has developed a SIMD (Single Instruction Multiple Data) parallel architecture called SYMPATI 2. This structure constitute the kernel of the parallel OPENVISION system that is commercialized by Centralp Automatisme. In order to reduce the computation time and to produce the DEM with the same accuracy than the scalar approach, this two partners tried to parallize the IGN's correlator on the OPENVISION system.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"26 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121606759","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-04-19DOI: 10.1109/ICAPP.1995.472195
Wei Chen, K. Wada, K. Kawaguchi
We present a parallel method for finding the convex hull of a set of discs in the CREW PRAM model. We show that the convex hull of n discs can be computed in O(log/sup 1+/spl epsiv// n) time using O(n/log/sup /spl epsiv// n) processors, where /spl epsiv/ is any positive constant. We also show that it can be constructed in O(log n loglog n) time using O(n log n) processors. The first result achieves cost optimal and the second one runs faster. The main technique which we used in the algorithm is a complex divide-and-conquer technique.<>
{"title":"A parallel method for finding the convex hull of discs","authors":"Wei Chen, K. Wada, K. Kawaguchi","doi":"10.1109/ICAPP.1995.472195","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472195","url":null,"abstract":"We present a parallel method for finding the convex hull of a set of discs in the CREW PRAM model. We show that the convex hull of n discs can be computed in O(log/sup 1+/spl epsiv// n) time using O(n/log/sup /spl epsiv// n) processors, where /spl epsiv/ is any positive constant. We also show that it can be constructed in O(log n loglog n) time using O(n log n) processors. The first result achieves cost optimal and the second one runs faster. The main technique which we used in the algorithm is a complex divide-and-conquer technique.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127773577","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-04-19DOI: 10.1109/ICAPP.1995.472210
B. Arion, Y. Ni, F. Devos
This paper presents a novel stereo architecture to implement a stereovision algorithm suited to obstacle detection and collision avoidance applications in real-time environments. The algorithm is derived from the spatio-frequency analysis proposed by Marr and Poggio (1979), with the matching primitives resulting from a local extremum extraction in the band-pass filtered stereopair images. A VLSI implementation is motivated both by the high processing speed required in such a real-time content and by the simplicity and regularity of the algorithm. We have therefore designed a retina-like architecture, with an in-line parallel processing unit interfaced with an on-chip photodiode matrix sensor. This stereo retina system has been succesfully simulated with real scenes images taken from a running car on a highway. A 128-pixel line CMOS retina has been designed and fabricated. First-hand experiments are positive.<>
{"title":"A novel stereovision architecture for real-time obstacle detection","authors":"B. Arion, Y. Ni, F. Devos","doi":"10.1109/ICAPP.1995.472210","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472210","url":null,"abstract":"This paper presents a novel stereo architecture to implement a stereovision algorithm suited to obstacle detection and collision avoidance applications in real-time environments. The algorithm is derived from the spatio-frequency analysis proposed by Marr and Poggio (1979), with the matching primitives resulting from a local extremum extraction in the band-pass filtered stereopair images. A VLSI implementation is motivated both by the high processing speed required in such a real-time content and by the simplicity and regularity of the algorithm. We have therefore designed a retina-like architecture, with an in-line parallel processing unit interfaced with an on-chip photodiode matrix sensor. This stereo retina system has been succesfully simulated with real scenes images taken from a running car on a highway. A 128-pixel line CMOS retina has been designed and fabricated. First-hand experiments are positive.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129016407","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-04-19DOI: 10.1109/ICAPP.1995.472191
Glenn R. Wightwick, L. Leslie, S. F. Wail
A limited-area numeric weather prediction model specifically targeted for parallel computers has been successfully implemented an an IBM SP2 distributed-memory parallel computer. The model employs an explicit finite-difference scheme and was parallelised using a simple domain decomposition technique. On a twelve processor SP2, a 24 hour forecast using archived operational data and including a sophisticated representation of physical processes was run at a range of resolutions between 150 km and 19 km and near-linear speedups were achieved. Major weather centres have indicated a requirement for regional prediction models to be run at resolutions of approximately 5 km by the end of the decade. Based on this work, it appears that this target can be achieved through the use of scalable parallel computers.<>
{"title":"A numeric weather prediction model for the IBM SP2 parallel computer","authors":"Glenn R. Wightwick, L. Leslie, S. F. Wail","doi":"10.1109/ICAPP.1995.472191","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472191","url":null,"abstract":"A limited-area numeric weather prediction model specifically targeted for parallel computers has been successfully implemented an an IBM SP2 distributed-memory parallel computer. The model employs an explicit finite-difference scheme and was parallelised using a simple domain decomposition technique. On a twelve processor SP2, a 24 hour forecast using archived operational data and including a sophisticated representation of physical processes was run at a range of resolutions between 150 km and 19 km and near-linear speedups were achieved. Major weather centres have indicated a requirement for regional prediction models to be run at resolutions of approximately 5 km by the end of the decade. Based on this work, it appears that this target can be achieved through the use of scalable parallel computers.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129033805","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-04-19DOI: 10.1109/ICAPP.1995.472252
Dong Wang, Hiroaki Kobayashi, Tadao Nakamura
This paper presents a hierarchical parallel execution model for Prolog programs, the execution model is based on Or-parallelism/And-parallelism as coarse-grain parallelism, and parallel unification as fine-grain parallelism. At the coarse-grain parallelism level we propose an extended And-Or tree. Consequently, the tree can exploit high degree of parallelism from Prolog programs. Exploiting parallelism of Prolog programs is based an the binding-arrays method for Or-parallelism and the restricted And-parallelism (RAP) method for And-parallelism. At the fine-grain parallelism level, parallel unification is performed. In general, the parallel unification consists of parallel argument matching and consistency checking. However, since the RAP method does not need consistency checking, consistency checking at the fine-grain parallelism level is also removed. The measurements of the parallelism degree of this model are also to be presented in this paper.<>
提出了一种Prolog程序的分层并行执行模型，该模型以or -并行/ and -并行为粗粒度并行，并行统一为细粒度并行。在粗粒度并行级，我们提出了一个扩展的And-Or树。因此，树可以利用Prolog程序的高度并行性。利用Prolog程序的并行性是基于or并行性的绑定数组方法和and并行性的限制and并行(RAP)方法。在细粒度并行级，执行并行统一。一般来说，并行统一包括并行参数匹配和一致性检查。但是，由于RAP方法不需要一致性检查，因此也去掉了细粒度并行级的一致性检查。本文还给出了该模型平行度的测量方法。
{"title":"Design and performance measurements of an execution model for the parallel processing of Prolog programs","authors":"Dong Wang, Hiroaki Kobayashi, Tadao Nakamura","doi":"10.1109/ICAPP.1995.472252","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472252","url":null,"abstract":"This paper presents a hierarchical parallel execution model for Prolog programs, the execution model is based on Or-parallelism/And-parallelism as coarse-grain parallelism, and parallel unification as fine-grain parallelism. At the coarse-grain parallelism level we propose an extended And-Or tree. Consequently, the tree can exploit high degree of parallelism from Prolog programs. Exploiting parallelism of Prolog programs is based an the binding-arrays method for Or-parallelism and the restricted And-parallelism (RAP) method for And-parallelism. At the fine-grain parallelism level, parallel unification is performed. In general, the parallel unification consists of parallel argument matching and consistency checking. However, since the RAP method does not need consistency checking, consistency checking at the fine-grain parallelism level is also removed. The measurements of the parallelism degree of this model are also to be presented in this paper.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114926995","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-04-19DOI: 10.1109/ICAPP.1995.472198
Author Lau, K. Leung, N. Yung, Y. Cheung
This paper introduces the doubly-linked list (DLL) protocol for distributed shared memory (DSM) multiprocessor systems. The protocol makes use of two linked lists to keep track of valid copies of pages in the system, thus eliminating the use of copysets. Simulation studies show that the DLL protocol achieved considerable speed-up for common mathematical problems including a linear equations solver and a matrix multiplier. Performance improvement of up to 51.9% over the dynamic distributed manager algorithm is obtained. Further improvement and possible modification of the protocol are also discussed.<>
{"title":"On the doubly-linked list protocol for distributed shared memory multiprocessor systems","authors":"Author Lau, K. Leung, N. Yung, Y. Cheung","doi":"10.1109/ICAPP.1995.472198","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472198","url":null,"abstract":"This paper introduces the doubly-linked list (DLL) protocol for distributed shared memory (DSM) multiprocessor systems. The protocol makes use of two linked lists to keep track of valid copies of pages in the system, thus eliminating the use of copysets. Simulation studies show that the DLL protocol achieved considerable speed-up for common mathematical problems including a linear equations solver and a matrix multiplier. Performance improvement of up to 51.9% over the dynamic distributed manager algorithm is obtained. Further improvement and possible modification of the protocol are also discussed.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"110 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130799477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 1995-04-19DOI: 10.1109/ICAPP.1995.472265
M. Alderighi, D. Crosetto, S. D'Angelo, G. Sechi
This report describes an implementation on the 3D-flow system developed at the Superconducting Super Collider Lab. of the algorithms and equipment to recognize valid photon events using a morphological analysis of the signals of an intensified CCD in the photon counting mode. The analysis consists of calculating the coordinates of a matrix corresponding to the exact position of each incident photon on the channel plate. Several off-line calculations with efficiency studies aiming at finding the best algorithm for event reconstruction have been performed. This off-line algorithm can be accomplished in real time at the CCD input rate (up to 2000 frames/sec). The communication-intensive nature of the algorithm and of the topology of this application and the particular architecture of the 3D-flow system lead to a very efficient implementation. The existing hardware simulator allows studies of the entire system before actual construction.<>
{"title":"Implementing photon event recognition algorithms on a 3D-flow system","authors":"M. Alderighi, D. Crosetto, S. D'Angelo, G. Sechi","doi":"10.1109/ICAPP.1995.472265","DOIUrl":"https://doi.org/10.1109/ICAPP.1995.472265","url":null,"abstract":"This report describes an implementation on the 3D-flow system developed at the Superconducting Super Collider Lab. of the algorithms and equipment to recognize valid photon events using a morphological analysis of the signals of an intensified CCD in the photon counting mode. The analysis consists of calculating the coordinates of a matrix corresponding to the exact position of each incident photon on the channel plate. Several off-line calculations with efficiency studies aiming at finding the best algorithm for event reconstruction have been performed. This off-line algorithm can be accomplished in real time at the CCD input rate (up to 2000 frames/sec). The communication-intensive nature of the algorithm and of the topology of this application and the particular architecture of the 3D-flow system lead to a very efficient implementation. The existing hardware simulator allows studies of the entire system before actual construction.<<ETX>>","PeriodicalId":448130,"journal":{"name":"Proceedings 1st International Conference on Algorithms and Architectures for Parallel Processing","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1995-04-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131565090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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