Pub Date : 2022-10-14DOI: 10.1109/IET-ICETA56553.2022.9971670
H. Tzeng, J. Hsiung, Zhi-Fang Xu
Recently, the cane umbrella products have been more and more widely used in all kinds of aged fields. With the decline in fertility in the birth of fewer children, the population will step into an aged society. The convenience of the elderly activities is also a major factor affecting their body and mind. Therefore, the development of assistive devices for the elderly is very important. Based on the above considerations, this study focus on design and improve cane umbrella, which combines the characteristics of trekking poles and folding umbrellas. The main purpose was to install a solar panel power generation mechanism at the top of the umbrella grip. The attached safety warning LED light is as an alarm buzzer system with certain frequency flashing. The crutch head adopts an articulated design to enhance the grip. In conclusion, the product takes the alarm function and night safety into considerations. Furthermore, it has a folding function and is easy to carry. It also has the appearance beautification effect of the work, realizes happy goes out, and feels warm when returning home safely.
{"title":"A Study of Innovative Multi-functional Folding Umbrella with Solar Energy","authors":"H. Tzeng, J. Hsiung, Zhi-Fang Xu","doi":"10.1109/IET-ICETA56553.2022.9971670","DOIUrl":"https://doi.org/10.1109/IET-ICETA56553.2022.9971670","url":null,"abstract":"Recently, the cane umbrella products have been more and more widely used in all kinds of aged fields. With the decline in fertility in the birth of fewer children, the population will step into an aged society. The convenience of the elderly activities is also a major factor affecting their body and mind. Therefore, the development of assistive devices for the elderly is very important. Based on the above considerations, this study focus on design and improve cane umbrella, which combines the characteristics of trekking poles and folding umbrellas. The main purpose was to install a solar panel power generation mechanism at the top of the umbrella grip. The attached safety warning LED light is as an alarm buzzer system with certain frequency flashing. The crutch head adopts an articulated design to enhance the grip. In conclusion, the product takes the alarm function and night safety into considerations. Furthermore, it has a folding function and is easy to carry. It also has the appearance beautification effect of the work, realizes happy goes out, and feels warm when returning home safely.","PeriodicalId":46240,"journal":{"name":"IET Networks","volume":null,"pages":null},"PeriodicalIF":1.4,"publicationDate":"2022-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79439699","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-14DOI: 10.1109/IET-ICETA56553.2022.9971488
Yao-Wen Chang, Chih-Chi Huang, Y. Hwang
This paper presents an experimental trial of implementing a face mask detection system based on a high-level synthesis (HLS) design flow and the concept of hardware/ software codesign. The target platform is a low-cost Xilinx PYNQ-Z2 FPGA board, which is connected to a host computer and serves as a hardware accelerator performing the task of face mask detection. The development is under a PYNQ framework supporting applications, software and hardware designs. In applications, a Jupyter Notebook is used for system level control. In hardware design, a Vivado HLS IP flow is used to design the hardware computing kernel and implement the interface (overlay) between hardware and software sections. To simplify the hardware implementation complexity, the face mask detection algorithm adopts an ISP approach in lieu of complicated CNN models. The algorithm consists of color space transform, skin color detection, morphological operations, connected components labeling and horizontal edge detection. Despite its algorithmic simplicity, the proposed scheme supports multi-object detection and can exclude the interferences from non-face parts. Each module is described in C++ and translated to a corresponding hardware design module via HLS. These modules are then combined to form a hardware accelerator and integrated to the PYNQ framework. The implementation result indicates the detection FPS can reach 18.
{"title":"A Face Mask Detection System Based on High Level Synthesis and Hardware Software Codesign","authors":"Yao-Wen Chang, Chih-Chi Huang, Y. Hwang","doi":"10.1109/IET-ICETA56553.2022.9971488","DOIUrl":"https://doi.org/10.1109/IET-ICETA56553.2022.9971488","url":null,"abstract":"This paper presents an experimental trial of implementing a face mask detection system based on a high-level synthesis (HLS) design flow and the concept of hardware/ software codesign. The target platform is a low-cost Xilinx PYNQ-Z2 FPGA board, which is connected to a host computer and serves as a hardware accelerator performing the task of face mask detection. The development is under a PYNQ framework supporting applications, software and hardware designs. In applications, a Jupyter Notebook is used for system level control. In hardware design, a Vivado HLS IP flow is used to design the hardware computing kernel and implement the interface (overlay) between hardware and software sections. To simplify the hardware implementation complexity, the face mask detection algorithm adopts an ISP approach in lieu of complicated CNN models. The algorithm consists of color space transform, skin color detection, morphological operations, connected components labeling and horizontal edge detection. Despite its algorithmic simplicity, the proposed scheme supports multi-object detection and can exclude the interferences from non-face parts. Each module is described in C++ and translated to a corresponding hardware design module via HLS. These modules are then combined to form a hardware accelerator and integrated to the PYNQ framework. The implementation result indicates the detection FPS can reach 18.","PeriodicalId":46240,"journal":{"name":"IET Networks","volume":null,"pages":null},"PeriodicalIF":1.4,"publicationDate":"2022-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84925099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-14DOI: 10.1109/IET-ICETA56553.2022.9971607
Chia-Chuan Wu, William Cheng-Yu Ma, Yu‐Xuan Wang, Mao‐Chou Tai, Yu-An Chen, Hong-Yi Tu, Sheng-Yao Chou, Ya-Ting Chien, T. Chang
In this work, the electrical characteristics of the low-temperature polysilicon thin-film transistors (LTPS TFTs) fabricated at low-temperature process were investigated. To improve the process of AMOLED displays, a lower fabrication temperature is necessary to adopt and investigate since a lower fabrication temperature is suitable for flexible electronics. In general, the fabrication temperature of LTPS TFTs is about $400 ^{circ}mathrm{C}$. Therefore, to clarify the impact of lower fabrication temperature, $400 ^{circ}mathrm{C}$, $370 ^{circ}mathrm{C}$, and $350 ^{circ}mathrm{C}$ are chosen as the maximum processing temperature during device fabrication for three TFT samples, respectively. It is found that the lower fabrication temperature device has lower on-current and higher on-resistance. However, a lower off-state leakage current is observed while the process temperature is declining due to trap-assisted thermal field emission. Silvaco TCAD simulation is discussed to support our findings.
{"title":"Investigation of Electrical Characteristics in Low-Temperature Polycrystalline Silicon Thin-Film Transistors Fabricated at Low-Temperature Process","authors":"Chia-Chuan Wu, William Cheng-Yu Ma, Yu‐Xuan Wang, Mao‐Chou Tai, Yu-An Chen, Hong-Yi Tu, Sheng-Yao Chou, Ya-Ting Chien, T. Chang","doi":"10.1109/IET-ICETA56553.2022.9971607","DOIUrl":"https://doi.org/10.1109/IET-ICETA56553.2022.9971607","url":null,"abstract":"In this work, the electrical characteristics of the low-temperature polysilicon thin-film transistors (LTPS TFTs) fabricated at low-temperature process were investigated. To improve the process of AMOLED displays, a lower fabrication temperature is necessary to adopt and investigate since a lower fabrication temperature is suitable for flexible electronics. In general, the fabrication temperature of LTPS TFTs is about $400 ^{circ}mathrm{C}$. Therefore, to clarify the impact of lower fabrication temperature, $400 ^{circ}mathrm{C}$, $370 ^{circ}mathrm{C}$, and $350 ^{circ}mathrm{C}$ are chosen as the maximum processing temperature during device fabrication for three TFT samples, respectively. It is found that the lower fabrication temperature device has lower on-current and higher on-resistance. However, a lower off-state leakage current is observed while the process temperature is declining due to trap-assisted thermal field emission. Silvaco TCAD simulation is discussed to support our findings.","PeriodicalId":46240,"journal":{"name":"IET Networks","volume":null,"pages":null},"PeriodicalIF":1.4,"publicationDate":"2022-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85391973","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-14DOI: 10.1109/IET-ICETA56553.2022.9971482
Xing-Chen Mai, Shen-Li Chen, Jhong-Yi Lai, Zhi-Wei Liu, Yu-Jie Chung
In this paper, a TSMC $0.18- {mu} mathrm{m}$ BCD process is used to realize high-voltage n-LDMOS devices. And then, the source side $n^{{+}}$ layer of the reference device is removed, so that the source terminal will make a parasitic Schottky device. Next, in this paper, we will evaluate its impacts on the discharge current capability. There are four kinds of tested devices in this work, which are the reference, with whole source -Schottky MM, and removed half source electrode MN and maked half Schottky in source end NM type devices, respectively. According to the TLP testing results, three important values of snapback curve can be obtained: trigger voltage (${mathrm{V}}_{{mathrm t1}}$), holding voltage (${mathrm{V}}_{{mathrm{h}}}$), and secondary breakdown current (${mathrm{I}}_{{mathrm{t}}2}$). Finally, it can be concluded that if a Schottky device is added to the source terminal, the on-resistance will be increased due to the series connection of this Schottky device, then the trigger voltage can be increased about 2V and holding voltage increased about 8V.
{"title":"ESD-immunity Study of High-voltage nLDMOS with Vertical Parasitic Schottky Structures in the Source End","authors":"Xing-Chen Mai, Shen-Li Chen, Jhong-Yi Lai, Zhi-Wei Liu, Yu-Jie Chung","doi":"10.1109/IET-ICETA56553.2022.9971482","DOIUrl":"https://doi.org/10.1109/IET-ICETA56553.2022.9971482","url":null,"abstract":"In this paper, a TSMC $0.18- {mu} mathrm{m}$ BCD process is used to realize high-voltage n-LDMOS devices. And then, the source side $n^{{+}}$ layer of the reference device is removed, so that the source terminal will make a parasitic Schottky device. Next, in this paper, we will evaluate its impacts on the discharge current capability. There are four kinds of tested devices in this work, which are the reference, with whole source -Schottky MM, and removed half source electrode MN and maked half Schottky in source end NM type devices, respectively. According to the TLP testing results, three important values of snapback curve can be obtained: trigger voltage (${mathrm{V}}_{{mathrm t1}}$), holding voltage (${mathrm{V}}_{{mathrm{h}}}$), and secondary breakdown current (${mathrm{I}}_{{mathrm{t}}2}$). Finally, it can be concluded that if a Schottky device is added to the source terminal, the on-resistance will be increased due to the series connection of this Schottky device, then the trigger voltage can be increased about 2V and holding voltage increased about 8V.","PeriodicalId":46240,"journal":{"name":"IET Networks","volume":null,"pages":null},"PeriodicalIF":1.4,"publicationDate":"2022-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84091784","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-14DOI: 10.1109/IET-ICETA56553.2022.9971497
Yi-Ren Chen, Shih-Hsu Huang
Hardware obfuscation is a useful technique for IP (intellectual property) protection. Several previous works have paid attention to the design of obfuscated FSM (finite state machine). Their common way is to insert an extra obfuscation mode to prevent the attackers from entering the normal mode. Based on the concept of obfuscation mode, in this paper, we study the design flow for FPGA implementation. The proposed design flow includes two main steps: RTL coding (for the obfuscation mode) followed by FPGA synthesis. Experiments with a real circuit show that the FPGA implementation can work without any degradation on circuit speed.
{"title":"Design Flow for The Implementation of Obfuscated Finite State Machines","authors":"Yi-Ren Chen, Shih-Hsu Huang","doi":"10.1109/IET-ICETA56553.2022.9971497","DOIUrl":"https://doi.org/10.1109/IET-ICETA56553.2022.9971497","url":null,"abstract":"Hardware obfuscation is a useful technique for IP (intellectual property) protection. Several previous works have paid attention to the design of obfuscated FSM (finite state machine). Their common way is to insert an extra obfuscation mode to prevent the attackers from entering the normal mode. Based on the concept of obfuscation mode, in this paper, we study the design flow for FPGA implementation. The proposed design flow includes two main steps: RTL coding (for the obfuscation mode) followed by FPGA synthesis. Experiments with a real circuit show that the FPGA implementation can work without any degradation on circuit speed.","PeriodicalId":46240,"journal":{"name":"IET Networks","volume":null,"pages":null},"PeriodicalIF":1.4,"publicationDate":"2022-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86133853","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-14DOI: 10.1109/IET-ICETA56553.2022.9971618
Y. Lin, Y. Chiu, E. Chang
Normally-off p-GaN gate high electron mobility transistor (HEMT) on Si substrate using the back-side via process was investigated. We removed the Si substrate and part of the GaN carbon-doped layer. A 100 nm thickness of SiO2 layer is deposited on the back-side via to obstruct the buffer leakage, and a 1um thick gold is electroplated to improve the self-heating effect. With and without the backside via process, the threshold voltages are 0.92 and 1.45 V, the on/off drain current ratios are 5×1010 and 5×108, the subthreshold swings are 154 and 224 mV/dec, the static on-resistances are 24.77 and 27.55 Ω.mm, and the dynamic on-resistance ratios are 1.18 and 1.3.
{"title":"Investigation of p-GaN Gate HEMT using Removal Si Substrate and part of Buffer Layer","authors":"Y. Lin, Y. Chiu, E. Chang","doi":"10.1109/IET-ICETA56553.2022.9971618","DOIUrl":"https://doi.org/10.1109/IET-ICETA56553.2022.9971618","url":null,"abstract":"Normally-off p-GaN gate high electron mobility transistor (HEMT) on Si substrate using the back-side via process was investigated. We removed the Si substrate and part of the GaN carbon-doped layer. A 100 nm thickness of SiO2 layer is deposited on the back-side via to obstruct the buffer leakage, and a 1um thick gold is electroplated to improve the self-heating effect. With and without the backside via process, the threshold voltages are 0.92 and 1.45 V, the on/off drain current ratios are 5×1010 and 5×108, the subthreshold swings are 154 and 224 mV/dec, the static on-resistances are 24.77 and 27.55 Ω.mm, and the dynamic on-resistance ratios are 1.18 and 1.3.","PeriodicalId":46240,"journal":{"name":"IET Networks","volume":null,"pages":null},"PeriodicalIF":1.4,"publicationDate":"2022-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89054197","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
We propose methods for object detection based on remote sensing images. This method further improves detection accuracy and decreases error rates. Modified YOLOv4 is an accelerated neural network model based on the YOLO (YouOnly-Look-Once) object detection method. It outperforms existing networks in terms of execution time and detection performance. The experimental results show improved mAP (mean average precision) performance of the proposed method for object detection in remote sensing images. We thus propose a novel system for automatic object detection for high-resolution remote sensing images.
{"title":"Using Modified YOLOv4 for Military Target Detection","authors":"Jung-Hung Pan, Chiu-Chin Lin, Jen-Chun Lee, Chung-Hsien Chen","doi":"10.1109/IET-ICETA56553.2022.9971558","DOIUrl":"https://doi.org/10.1109/IET-ICETA56553.2022.9971558","url":null,"abstract":"We propose methods for object detection based on remote sensing images. This method further improves detection accuracy and decreases error rates. Modified YOLOv4 is an accelerated neural network model based on the YOLO (YouOnly-Look-Once) object detection method. It outperforms existing networks in terms of execution time and detection performance. The experimental results show improved mAP (mean average precision) performance of the proposed method for object detection in remote sensing images. We thus propose a novel system for automatic object detection for high-resolution remote sensing images.","PeriodicalId":46240,"journal":{"name":"IET Networks","volume":null,"pages":null},"PeriodicalIF":1.4,"publicationDate":"2022-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83501467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-14DOI: 10.1109/IET-ICETA56553.2022.9971568
Su Kuan-Ying, Chen Ming-Fei, Tsai Po-Cheng, Tsai Cheng-Han
The purpose of this research is to develop a real-time bicycle frame's defect detection system using YOLO (You Only Look Once) and machine vision. Firstly, the defect locations are manually selected and a database is established. Next, a Darknet method is used to train the YOLO model. Its static detection accuracy rate is 92.6%, and then the static training model is combined with a robotic arm and an industrial camera to perform dynamic detection verification. The result shows that its detection rate reaches 87%. Finally, the above-mentioned defect detection technology is used with the detection machine to complete the development of the online defect detection system.
本研究的目的是利用YOLO (You Only Look Once)和机器视觉技术开发一种自行车车架缺陷实时检测系统。首先，手工选择缺陷位置并建立缺陷数据库。其次，采用暗网方法对YOLO模型进行训练。其静态检测准确率为92.6%，然后将静态训练模型与机械臂和工业相机相结合，进行动态检测验证。结果表明，该方法的检出率可达87%。最后将上述缺陷检测技术与检测机结合使用，完成在线缺陷检测系统的开发。
{"title":"Establish a Dynamic Detection System for Metal Bicycle Frame Defects Based on YOLO Object Detection","authors":"Su Kuan-Ying, Chen Ming-Fei, Tsai Po-Cheng, Tsai Cheng-Han","doi":"10.1109/IET-ICETA56553.2022.9971568","DOIUrl":"https://doi.org/10.1109/IET-ICETA56553.2022.9971568","url":null,"abstract":"The purpose of this research is to develop a real-time bicycle frame's defect detection system using YOLO (You Only Look Once) and machine vision. Firstly, the defect locations are manually selected and a database is established. Next, a Darknet method is used to train the YOLO model. Its static detection accuracy rate is 92.6%, and then the static training model is combined with a robotic arm and an industrial camera to perform dynamic detection verification. The result shows that its detection rate reaches 87%. Finally, the above-mentioned defect detection technology is used with the detection machine to complete the development of the online defect detection system.","PeriodicalId":46240,"journal":{"name":"IET Networks","volume":null,"pages":null},"PeriodicalIF":1.4,"publicationDate":"2022-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88138545","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-14DOI: 10.1109/IET-ICETA56553.2022.9971486
Shao-Huai Wang, Pin-Chieh Hsieh, Tzu-Yao Su, Jhih-Yuan Gao, Min-Hua Lu, Yunqi Fan
In this paper, we proposed COVID-19 lung CT (computed tomography) images recognition with superscalar winograd circuit based on VGG19. We adopt the VGG-19 machine learning architecture to recognize lung CT images and speed up neural network operations through Superscalar Winograd Circuit. After a series of experiments, our proposed method has a high pneumonia recognition rate and high computational efficiency.
{"title":"COVID-19 Lung CT Images Recognition with Superscalar Winograd Circuit Based on VGG19","authors":"Shao-Huai Wang, Pin-Chieh Hsieh, Tzu-Yao Su, Jhih-Yuan Gao, Min-Hua Lu, Yunqi Fan","doi":"10.1109/IET-ICETA56553.2022.9971486","DOIUrl":"https://doi.org/10.1109/IET-ICETA56553.2022.9971486","url":null,"abstract":"In this paper, we proposed COVID-19 lung CT (computed tomography) images recognition with superscalar winograd circuit based on VGG19. We adopt the VGG-19 machine learning architecture to recognize lung CT images and speed up neural network operations through Superscalar Winograd Circuit. After a series of experiments, our proposed method has a high pneumonia recognition rate and high computational efficiency.","PeriodicalId":46240,"journal":{"name":"IET Networks","volume":null,"pages":null},"PeriodicalIF":1.4,"publicationDate":"2022-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86867342","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2022-10-14DOI: 10.1109/IET-ICETA56553.2022.9971521
C. Chen, Yi-Feng Lin, Wei-Cheng Chen, Jing-Yuan Lin, H. Chiu
This paper presents the hybrid control of a fullbridge LLC series resonant converter as the application of an electric vehicle charging system. the hybrid control combines three control methods to achieve wide a output voltage range of about $75sim 475 V$, three control methods including the pulse-frequency control method, phase-shift control method, and burst mode. finally, a wide-range output voltage LLC resonant converter prototype is realized. The specification of the prototype is a DC input voltage of SOO V, an output voltage of 75-475V, and maximum output power of 7.5 kW. The peak efficiency is 97.2 %.
本文介绍了全桥LLC串联谐振变换器的混合控制在电动汽车充电系统中的应用。混合控制结合了三种控制方法，包括脉冲频率控制方法、相移控制方法和突发控制方式，实现了约75 μ m 475 V的宽输出电压范围。最后，实现了大范围输出电压LLC谐振变换器样机。样机的规格为直流输入电压SOO V，输出电压75 ~ 475v，最大输出功率7.5 kW。峰值效率为97.2%。
{"title":"Wide Range Output Voltage LLC Resonant Converter for Electric Vehicle Charging System","authors":"C. Chen, Yi-Feng Lin, Wei-Cheng Chen, Jing-Yuan Lin, H. Chiu","doi":"10.1109/IET-ICETA56553.2022.9971521","DOIUrl":"https://doi.org/10.1109/IET-ICETA56553.2022.9971521","url":null,"abstract":"This paper presents the hybrid control of a fullbridge LLC series resonant converter as the application of an electric vehicle charging system. the hybrid control combines three control methods to achieve wide a output voltage range of about $75sim 475 V$, three control methods including the pulse-frequency control method, phase-shift control method, and burst mode. finally, a wide-range output voltage LLC resonant converter prototype is realized. The specification of the prototype is a DC input voltage of SOO V, an output voltage of 75-475V, and maximum output power of 7.5 kW. The peak efficiency is 97.2 %.","PeriodicalId":46240,"journal":{"name":"IET Networks","volume":null,"pages":null},"PeriodicalIF":1.4,"publicationDate":"2022-10-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"90733902","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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