The KSTAR Fast Interlock System (FIS) has the primary role of protecting the devices installed in the vacuum vessel of tokamak such as Plasma Facing Components (PFCs) by immediately stopping the KSTAR heating devices, following the event handling actions of the Plasma Control System (PCS). Furthermore, the FIS assists the PCS event handling operations by redundantly detecting abnormal Plasma Current (IP) events. The initially implemented detection logic for the IP minimum fault event has been successfully evaluated and operated. In this paper, we implement another logic detecting the IP error fault event that the discrepancy between the target IP and the measured IP exceeds the criteria. As the architecture design, we assign more complicated tasks such as the waveform generation to the host server and the error fault-checking task requiring real-time operation to the target controller. Second, the Direct Memory Access (DMA) method for data communication is adopted; thus, the target controller can conduct the detection logic and the data communication in parallel without real-time performance degradation. Third, we design proper timing of the data communication for stable operation. On the host side, we employ ITER Real-Time Framework (RTF) technology for initiating the data communication with precise timing and controlling the precise execution cycle. Finally, we apply the bypass logic to prevent conflict with the same detecting operation of the PCS. We evaluate the functionality of the IP error fault detection logic in the KSTAR plasma experiments.
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