Pub Date : 2019-10-01DOI: 10.1109/iccke48569.2019.8964957
{"title":"[ICCKE 2019 Authors]","authors":"","doi":"10.1109/iccke48569.2019.8964957","DOIUrl":"https://doi.org/10.1109/iccke48569.2019.8964957","url":null,"abstract":"","PeriodicalId":6685,"journal":{"name":"2019 9th International Conference on Computer and Knowledge Engineering (ICCKE)","volume":"14 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82489942","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ICCKE48569.2019.8965087
Mohsen Ramezani, F. Yaghmaee
Today, video searching methods dropped behind the growth of using capturing devices. Action retrieval is a new research field which seeks to use the captured human action for searching the videos. As most human actions consist of similar motions which are repeated over time, we seek to propose a method for eliminating the repetitive motions before retrieving the videos. This method, as a preprocessing step, can decrease the volume of the retrieval computations for each video. Here, a function is used to calculate a value per each pixel as its movement energy. Then, CWT (Continuous Wavelet Transform) is used for mapping the response function of the points into the frequency space to find similar motion patterns more easier. The DTW (Dynamic Time Wrapping) is then applied on the new space to find similar frequency patterns (episodes) over time. Finally, one of the similar episodes, i.e. some sequential frames, remains for the retrieval computations and others are eliminated. The proposed method is evaluated on KTH, UCFYT, and HMDB datasets and results indicate the proper performance of the proposed method. Eliminating the repetitive motions results into significant reduction in retrieval computations and time.
{"title":"Eliminating the Repetitive Motions as a Preprocessing step for Fast Human Action Retrieval","authors":"Mohsen Ramezani, F. Yaghmaee","doi":"10.1109/ICCKE48569.2019.8965087","DOIUrl":"https://doi.org/10.1109/ICCKE48569.2019.8965087","url":null,"abstract":"Today, video searching methods dropped behind the growth of using capturing devices. Action retrieval is a new research field which seeks to use the captured human action for searching the videos. As most human actions consist of similar motions which are repeated over time, we seek to propose a method for eliminating the repetitive motions before retrieving the videos. This method, as a preprocessing step, can decrease the volume of the retrieval computations for each video. Here, a function is used to calculate a value per each pixel as its movement energy. Then, CWT (Continuous Wavelet Transform) is used for mapping the response function of the points into the frequency space to find similar motion patterns more easier. The DTW (Dynamic Time Wrapping) is then applied on the new space to find similar frequency patterns (episodes) over time. Finally, one of the similar episodes, i.e. some sequential frames, remains for the retrieval computations and others are eliminated. The proposed method is evaluated on KTH, UCFYT, and HMDB datasets and results indicate the proper performance of the proposed method. Eliminating the repetitive motions results into significant reduction in retrieval computations and time.","PeriodicalId":6685,"journal":{"name":"2019 9th International Conference on Computer and Knowledge Engineering (ICCKE)","volume":"104 1","pages":"26-31"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80550242","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ICCKE48569.2019.8964826
Navid Ghassemi, A. Shoeibi, M. Rouhani, Hossein Hosseini-Nejad
In this paper, a new scheme for diagnosis of epileptic seizures in EEG signals using Tunable-Q wavelet transform (TQWT) framework is proposed and benchmarked with Bonn dataset. First, a segmentation of the EEG signals into smaller windows is performed, then a high-pass Butterworth filter with a cutoff frequency of 0.5 Hz is applied to eliminate possible noise. After that, a TQWT with parameters J=8, r=3, Q=1 has been utilized for decomposing the segmented EEG Signals into nine sub-bands. Next, a combination of statistical, entropy-based, and fractal dimension features are extracted from each sub-band. Finally, different ensemble learning-based classifiers, specifically, Adaboost, Gradient Boosting (GB), Hist Gradient Boosting (HistGB), and Random Forest (RF) are employed to classify signals. Also, a feature ranking is driven from classifiers to further analyze the importance of each feature in this particular task. Comparing our method to previous ones, introduced scheme outperforms most of the state-of-the-art works in this field, indicating the effectiveness of the proposed epileptic seizures detection method.
{"title":"Epileptic seizures detection in EEG signals using TQWT and ensemble learning","authors":"Navid Ghassemi, A. Shoeibi, M. Rouhani, Hossein Hosseini-Nejad","doi":"10.1109/ICCKE48569.2019.8964826","DOIUrl":"https://doi.org/10.1109/ICCKE48569.2019.8964826","url":null,"abstract":"In this paper, a new scheme for diagnosis of epileptic seizures in EEG signals using Tunable-Q wavelet transform (TQWT) framework is proposed and benchmarked with Bonn dataset. First, a segmentation of the EEG signals into smaller windows is performed, then a high-pass Butterworth filter with a cutoff frequency of 0.5 Hz is applied to eliminate possible noise. After that, a TQWT with parameters J=8, r=3, Q=1 has been utilized for decomposing the segmented EEG Signals into nine sub-bands. Next, a combination of statistical, entropy-based, and fractal dimension features are extracted from each sub-band. Finally, different ensemble learning-based classifiers, specifically, Adaboost, Gradient Boosting (GB), Hist Gradient Boosting (HistGB), and Random Forest (RF) are employed to classify signals. Also, a feature ranking is driven from classifiers to further analyze the importance of each feature in this particular task. Comparing our method to previous ones, introduced scheme outperforms most of the state-of-the-art works in this field, indicating the effectiveness of the proposed epileptic seizures detection method.","PeriodicalId":6685,"journal":{"name":"2019 9th International Conference on Computer and Knowledge Engineering (ICCKE)","volume":"48 1","pages":"403-408"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91352687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ICCKE48569.2019.8965117
R. Kourdy, Amir Rajabzadeh
Network-on-chips are a novel communications infrastructure for decoupling the communication elements from processing cores, with the goal of eliminating the challenges of many cores systems. One of the most important NoCs challenges is fault tolerance. This article tries to resolve the challenge into separate ways i.e., topology and routing. The proposed topology is called fault tolerant Hypercube-base NoC (HNoC) and the proposed routing algorithm is called Fault Tolerant Hypercube-based Routing (FTHR). The FTHR was simulated in a HNoC topology in NS-2 standard simulator. The FTHR was evaluated using 3D to 10D NoCs with 8 to 2014 cores in normal and faulty conditions. The results of the experiments show that the HNoC packet loss by FTHR routing varies between 75.0% and 98.16% depending on the different NoC dimensions. This high degree of fault tolerance is because of router degree and the diversity of paths in HNoC and also applied innovations in the FTHR routing. The results also show that the FTHR routing has reasonable outcome and is capable of tolerance about 100% of router and link faults in permanent and transient timing.
{"title":"FTHR: Fault Tolerant Hypercube-based Routing for NoCs","authors":"R. Kourdy, Amir Rajabzadeh","doi":"10.1109/ICCKE48569.2019.8965117","DOIUrl":"https://doi.org/10.1109/ICCKE48569.2019.8965117","url":null,"abstract":"Network-on-chips are a novel communications infrastructure for decoupling the communication elements from processing cores, with the goal of eliminating the challenges of many cores systems. One of the most important NoCs challenges is fault tolerance. This article tries to resolve the challenge into separate ways i.e., topology and routing. The proposed topology is called fault tolerant Hypercube-base NoC (HNoC) and the proposed routing algorithm is called Fault Tolerant Hypercube-based Routing (FTHR). The FTHR was simulated in a HNoC topology in NS-2 standard simulator. The FTHR was evaluated using 3D to 10D NoCs with 8 to 2014 cores in normal and faulty conditions. The results of the experiments show that the HNoC packet loss by FTHR routing varies between 75.0% and 98.16% depending on the different NoC dimensions. This high degree of fault tolerance is because of router degree and the diversity of paths in HNoC and also applied innovations in the FTHR routing. The results also show that the FTHR routing has reasonable outcome and is capable of tolerance about 100% of router and link faults in permanent and transient timing.","PeriodicalId":6685,"journal":{"name":"2019 9th International Conference on Computer and Knowledge Engineering (ICCKE)","volume":"283 1","pages":"331-338"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76841033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Traffic congestion and gridlocks are considered as main problems of designing an urban motorway network. For this purpose, traffic flow control strategies are presented through recent decades to address this problem. In this paper, an Eligibility Traces based Reinforcement Learning (ETRL) traffic flow control strategy was proposed. This strategy is based on cooperative and integrated control of Ramp Metering (RM) and Variable Speed Limits (VSL). To test the proposed method, first the traffic macroscopic model was calibrated via Genetic Algorithm (GA) optimization to simulate traffic behavior and further, the traffic control strategy is applied to M62 highway stretch in England which is one of the smartest highways, and the results are presented.
{"title":"An Eligibility Traces based Cooperative and Integrated Control Strategy for Traffic Flow Control in Freeways","authors":"Seyed Soroosh Tabadkani Aval, Negar Shojaee Ghandeshtani, Parisa Akbari, N. Eghbal, Amin Noori","doi":"10.1109/ICCKE48569.2019.8965184","DOIUrl":"https://doi.org/10.1109/ICCKE48569.2019.8965184","url":null,"abstract":"Traffic congestion and gridlocks are considered as main problems of designing an urban motorway network. For this purpose, traffic flow control strategies are presented through recent decades to address this problem. In this paper, an Eligibility Traces based Reinforcement Learning (ETRL) traffic flow control strategy was proposed. This strategy is based on cooperative and integrated control of Ramp Metering (RM) and Variable Speed Limits (VSL). To test the proposed method, first the traffic macroscopic model was calibrated via Genetic Algorithm (GA) optimization to simulate traffic behavior and further, the traffic control strategy is applied to M62 highway stretch in England which is one of the smartest highways, and the results are presented.","PeriodicalId":6685,"journal":{"name":"2019 9th International Conference on Computer and Knowledge Engineering (ICCKE)","volume":"28 1","pages":"40-45"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77572967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/iccke48569.2019.8964673
{"title":"[Copyright notice]","authors":"","doi":"10.1109/iccke48569.2019.8964673","DOIUrl":"https://doi.org/10.1109/iccke48569.2019.8964673","url":null,"abstract":"","PeriodicalId":6685,"journal":{"name":"2019 9th International Conference on Computer and Knowledge Engineering (ICCKE)","volume":"40 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78994498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ICCKE48569.2019.8965093
J. Bahri, Hamid Reza Shayegh Borojeni
Electronic voting systems are one of the most important issues in today's world. At the present time, most systems are traditional and centralized, and the counting of votes is done by a central party, and security depends on cryptographic techniques. Therefore, the need to create decentralized voting systems is increasing day by day, so in this way, preservation and counting of votes are done directly with the help of a consensus algorithm. Having the difficulties mentioned above, this paper presents an unbiased electronic voting model in which the votes from ballot boxes are sent to the candidates, and the candidates should confirm the received votes, after candidates' confirmation, they agree on the received votes by running an DE-PBFT consensus, and then add votes in their DAG data structure . In this way, all candidates are responsible for maintaining, validating and counting votes, and the trust through consensus protocols is provided in a decentralized system. The voter's anonymity has also been preserved through ring signature.
{"title":"Electronic voting through DE-PBFT consensus and DAG data structure","authors":"J. Bahri, Hamid Reza Shayegh Borojeni","doi":"10.1109/ICCKE48569.2019.8965093","DOIUrl":"https://doi.org/10.1109/ICCKE48569.2019.8965093","url":null,"abstract":"Electronic voting systems are one of the most important issues in today's world. At the present time, most systems are traditional and centralized, and the counting of votes is done by a central party, and security depends on cryptographic techniques. Therefore, the need to create decentralized voting systems is increasing day by day, so in this way, preservation and counting of votes are done directly with the help of a consensus algorithm. Having the difficulties mentioned above, this paper presents an unbiased electronic voting model in which the votes from ballot boxes are sent to the candidates, and the candidates should confirm the received votes, after candidates' confirmation, they agree on the received votes by running an DE-PBFT consensus, and then add votes in their DAG data structure . In this way, all candidates are responsible for maintaining, validating and counting votes, and the trust through consensus protocols is provided in a decentralized system. The voter's anonymity has also been preserved through ring signature.","PeriodicalId":6685,"journal":{"name":"2019 9th International Conference on Computer and Knowledge Engineering (ICCKE)","volume":"11 1","pages":"391-396"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78084993","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ICCKE48569.2019.8965051
Amir Hossein Fakhteh, Vahid Sattari-Naeini, H. Naji
Software-Defined Network is a new networking generation to increase network flexibility and performance improvement. However, budget constraints, technical limitations and the risk of architectural changes that organizations are encountered with, are barriers to the full implementation of the SDN. For these reasons, Internet Service Providers (ISPs) should replace only a limited number of conventional switches with SDN switches at one time. Put both switches together in a topology, create hybrid SDN. In this paper, we first cluster the switches into two clusters, based on a graph concept which is called closeness-centrality. Afterward, we have one cluster with low closeness centrality and another with high; then, we propose a heuristic migration scheme for deploying SDN switches in hybrid SDNs. We first allocate all existing budget to a cluster at low closeness-centrality and then we upgrade the switches according to the proposed scheme. There are four main issues in this paper: (1) improving the network control ability with a given upgrading budget constraint, (2) minimizing the upgrading cost to achieve the best network control ability, (3) increasing hybrid SDN flexibility and (4) improving network fault tolerance by deploying a link fault recovery algorithm. Also, in order to perform controller placement, we propose a simple solution to provide an acceptable delay between controller and SDN switches. We evaluate our scheme in three real topologies and one synthetic topology. The results show that our scheme can achieve better network control ability and flexibility with the help of graph theory parameters compared to other related papers according to budget constraint.
{"title":"Increasing The Network Control Ability and Flexibility In Incremental Switch Deployment for Hybrid Software-Defined Networks","authors":"Amir Hossein Fakhteh, Vahid Sattari-Naeini, H. Naji","doi":"10.1109/ICCKE48569.2019.8965051","DOIUrl":"https://doi.org/10.1109/ICCKE48569.2019.8965051","url":null,"abstract":"Software-Defined Network is a new networking generation to increase network flexibility and performance improvement. However, budget constraints, technical limitations and the risk of architectural changes that organizations are encountered with, are barriers to the full implementation of the SDN. For these reasons, Internet Service Providers (ISPs) should replace only a limited number of conventional switches with SDN switches at one time. Put both switches together in a topology, create hybrid SDN. In this paper, we first cluster the switches into two clusters, based on a graph concept which is called closeness-centrality. Afterward, we have one cluster with low closeness centrality and another with high; then, we propose a heuristic migration scheme for deploying SDN switches in hybrid SDNs. We first allocate all existing budget to a cluster at low closeness-centrality and then we upgrade the switches according to the proposed scheme. There are four main issues in this paper: (1) improving the network control ability with a given upgrading budget constraint, (2) minimizing the upgrading cost to achieve the best network control ability, (3) increasing hybrid SDN flexibility and (4) improving network fault tolerance by deploying a link fault recovery algorithm. Also, in order to perform controller placement, we propose a simple solution to provide an acceptable delay between controller and SDN switches. We evaluate our scheme in three real topologies and one synthetic topology. The results show that our scheme can achieve better network control ability and flexibility with the help of graph theory parameters compared to other related papers according to budget constraint.","PeriodicalId":6685,"journal":{"name":"2019 9th International Conference on Computer and Knowledge Engineering (ICCKE)","volume":"87 1","pages":"263-268"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83773948","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ICCKE48569.2019.8964942
Mohammad Javad Parvardeh, Shahriar Baradaran Shokouhi
Physically Unclonable Functions (PUFs) are new hardware solution for low cost and secure communication primitives such as hardware authentication and secure key generation. PUFs use the random properties of a device to produce unique data. Ring Oscillator PUFs (RO PUF) are one of the most applicable PUFs because of its good reliability and easy implementation on FPGAs. One major problem of Ro PUFs is limited Challenge-Response pairs number. We consider this problem and introduce a new architecture of RO PUF that increases Challenge-Response pairs of a typical PUF with using minimum resources. In our architecture, we use an XOR gate to prevent direct response disclosure and increase our response unpredictability. In this manner, we increase Challenge-Response pairs up to $frac{{nleft( {n - 1} right)}}{2}$. We also show the result of the unity and uniqueness of our proposed PUF by implementing 110 PUFs on five XC3S400 FPGAs.
{"title":"A Ring Oscillator PUF Architecture With Enhanced Challenge-Response Set","authors":"Mohammad Javad Parvardeh, Shahriar Baradaran Shokouhi","doi":"10.1109/ICCKE48569.2019.8964942","DOIUrl":"https://doi.org/10.1109/ICCKE48569.2019.8964942","url":null,"abstract":"Physically Unclonable Functions (PUFs) are new hardware solution for low cost and secure communication primitives such as hardware authentication and secure key generation. PUFs use the random properties of a device to produce unique data. Ring Oscillator PUFs (RO PUF) are one of the most applicable PUFs because of its good reliability and easy implementation on FPGAs. One major problem of Ro PUFs is limited Challenge-Response pairs number. We consider this problem and introduce a new architecture of RO PUF that increases Challenge-Response pairs of a typical PUF with using minimum resources. In our architecture, we use an XOR gate to prevent direct response disclosure and increase our response unpredictability. In this manner, we increase Challenge-Response pairs up to $frac{{nleft( {n - 1} right)}}{2}$. We also show the result of the unity and uniqueness of our proposed PUF by implementing 110 PUFs on five XC3S400 FPGAs.","PeriodicalId":6685,"journal":{"name":"2019 9th International Conference on Computer and Knowledge Engineering (ICCKE)","volume":"13 1","pages":"444-449"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"88507333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2019-10-01DOI: 10.1109/ICCKE48569.2019.8964968
Maytham Allahi Roodposhti, M. Valinataj
In this paper, a new carry select adder (CSLA) architecture is proposed with a lower area and a higher speed compared to previous CSLAs. The proposed CSLA is a low-area and high-speed design utilizing a new add-one circuit that is used instead of the second ripple carry adder (RCA) with the input carry equal to one (Cin=1) inside each group of the basic CSLA. Moreover, to expedite the add operation, a new grouping structure is proposed instead of the basic square-root (SQRT) grouping as well as utilizing a faster RCA in each group. Despite the fact that the proposed CSLA has not attained the lowest power consumption among all existing designs based on the PDK 45nm standard cell library, but it has achieved the lowest area and delay compared to previous CSLAs. Implementation results show that 8 to 33% area reduction and 12 to 44% speed improvement are achieved in the proposed CSLA compared to previous designs.
{"title":"A Novel Area-Delay Efficient Carry Select Adder Based on New Add-one Circuit","authors":"Maytham Allahi Roodposhti, M. Valinataj","doi":"10.1109/ICCKE48569.2019.8964968","DOIUrl":"https://doi.org/10.1109/ICCKE48569.2019.8964968","url":null,"abstract":"In this paper, a new carry select adder (CSLA) architecture is proposed with a lower area and a higher speed compared to previous CSLAs. The proposed CSLA is a low-area and high-speed design utilizing a new add-one circuit that is used instead of the second ripple carry adder (RCA) with the input carry equal to one (Cin=1) inside each group of the basic CSLA. Moreover, to expedite the add operation, a new grouping structure is proposed instead of the basic square-root (SQRT) grouping as well as utilizing a faster RCA in each group. Despite the fact that the proposed CSLA has not attained the lowest power consumption among all existing designs based on the PDK 45nm standard cell library, but it has achieved the lowest area and delay compared to previous CSLAs. Implementation results show that 8 to 33% area reduction and 12 to 44% speed improvement are achieved in the proposed CSLA compared to previous designs.","PeriodicalId":6685,"journal":{"name":"2019 9th International Conference on Computer and Knowledge Engineering (ICCKE)","volume":"94 1","pages":"225-230"},"PeriodicalIF":0.0,"publicationDate":"2019-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91348687","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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