Pub Date : 2013-12-01DOI: 10.1109/FPT.2013.6718319
K. Wakabayashi
This presentation discusses how FPGA or coarse grained reconfigurable processor is superior to CPU/GPGPU from the view point of C compiler. Initially, we introduce the architectural characteristic of CPU, GPGPU and fine grained and coarse grained reconfigurable process with FSM+Datapath model. Then, we explain what kind of applications can be accelerated with "FPGA and C-based High Level Synthesis Tool" better than GPGPU according to the compiler techniques (freedom of compiler parallelization).
{"title":"Reconfigurable chip advantage compared with GPGPU from the compiler perspective","authors":"K. Wakabayashi","doi":"10.1109/FPT.2013.6718319","DOIUrl":"https://doi.org/10.1109/FPT.2013.6718319","url":null,"abstract":"This presentation discusses how FPGA or coarse grained reconfigurable processor is superior to CPU/GPGPU from the view point of C compiler. Initially, we introduce the architectural characteristic of CPU, GPGPU and fine grained and coarse grained reconfigurable process with FSM+Datapath model. Then, we explain what kind of applications can be accelerated with \"FPGA and C-based High Level Synthesis Tool\" better than GPGPU according to the compiler techniques (freedom of compiler parallelization).","PeriodicalId":6877,"journal":{"name":"2014 International Conference on Field-Programmable Technology (FPT)","volume":"6 1","pages":"2"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72792185","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-12-01DOI: 10.1109/FPT.2013.6718318
Arif Rahman
Summary form only given. Die stacking technology with high-bandwidth interconnect is enabling new product architectures and capabilities. Although 3D integration, where TSVs are incorporated in active device layers, is the Holy-Grail of die stacking, the early phase of technology adoption is driven by passive silicon interposer (2.5D) based integration scheme or some variants of it. This presentation will provide an overview of recent advances in die stacking and FPGA application trends which are driving the need for stacking technologies. I will present some of the industry challenges in technology integration and design infrastructure and how they are being addressed to enable broader technology adoption.
{"title":"Recent advances in die stacking and 3D FPGA","authors":"Arif Rahman","doi":"10.1109/FPT.2013.6718318","DOIUrl":"https://doi.org/10.1109/FPT.2013.6718318","url":null,"abstract":"Summary form only given. Die stacking technology with high-bandwidth interconnect is enabling new product architectures and capabilities. Although 3D integration, where TSVs are incorporated in active device layers, is the Holy-Grail of die stacking, the early phase of technology adoption is driven by passive silicon interposer (2.5D) based integration scheme or some variants of it. This presentation will provide an overview of recent advances in die stacking and FPGA application trends which are driving the need for stacking technologies. I will present some of the industry challenges in technology integration and design infrastructure and how they are being addressed to enable broader technology adoption.","PeriodicalId":6877,"journal":{"name":"2014 International Conference on Field-Programmable Technology (FPT)","volume":"5 1","pages":"1"},"PeriodicalIF":0.0,"publicationDate":"2013-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"89787459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-12-01DOI: 10.1109/FPT.2008.4762356
P. Lysaght
Summary form only given.FPGAs are the most successful example to date of programmable concurrent architectures. The 1980s saw the introduction of several kinds of concurrent processing arrays, ranging from fine-grained FPGAs to systolic arrays, to arrays of microprocessors. Of these, only FPGAs have enjoyed continuous commercial success. Now, however, with the end of the four-decade-old trend towards faster microprocessors, we are witnessing the revival of processor arrays. Due largely to concerns about power consumption multi-core, and indeed many-core architectures, are back at the forefront of system design. It is clear that we have the silicon resources and the circuit design skills to deliver semiconductor devices with highly concurrent programmable architectures and that the aggregate compute power of these arrays is impressive. What is not so straightforward is whether we now have the methodologies and automated tools to efficiently design systems of the complexity demanded by current and future markets. For example, we might enquire whether almost forty years of experience with microprocessors has made us any better prepared for the revival of many-core architectures. Paradoxically, the success of the uni-processor programming model may be the most significant impediment to our future success with highly concurrent, programmable architectures. Or taking an alternative perspective, we might ask whether we can benefit from over 25 years of experience of successfully deploying the programmable concurrency of FPGAs. In this talk, we will re-visit the challenges posed by programmable concurrent architectures and explore some of the assumptions underlying them in an effort to assess the potential of emergent solutions.
{"title":"Re-visiting the challenges of programmable concurrent architectures","authors":"P. Lysaght","doi":"10.1109/FPT.2008.4762356","DOIUrl":"https://doi.org/10.1109/FPT.2008.4762356","url":null,"abstract":"Summary form only given.FPGAs are the most successful example to date of programmable concurrent architectures. The 1980s saw the introduction of several kinds of concurrent processing arrays, ranging from fine-grained FPGAs to systolic arrays, to arrays of microprocessors. Of these, only FPGAs have enjoyed continuous commercial success. Now, however, with the end of the four-decade-old trend towards faster microprocessors, we are witnessing the revival of processor arrays. Due largely to concerns about power consumption multi-core, and indeed many-core architectures, are back at the forefront of system design. It is clear that we have the silicon resources and the circuit design skills to deliver semiconductor devices with highly concurrent programmable architectures and that the aggregate compute power of these arrays is impressive. What is not so straightforward is whether we now have the methodologies and automated tools to efficiently design systems of the complexity demanded by current and future markets. For example, we might enquire whether almost forty years of experience with microprocessors has made us any better prepared for the revival of many-core architectures. Paradoxically, the success of the uni-processor programming model may be the most significant impediment to our future success with highly concurrent, programmable architectures. Or taking an alternative perspective, we might ask whether we can benefit from over 25 years of experience of successfully deploying the programmable concurrency of FPGAs. In this talk, we will re-visit the challenges posed by programmable concurrent architectures and explore some of the assumptions underlying them in an effort to assess the potential of emergent solutions.","PeriodicalId":6877,"journal":{"name":"2014 International Conference on Field-Programmable Technology (FPT)","volume":"1967 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2008-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91397027","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-12-11DOI: 10.1109/FPT.2005.1568517
M. Juliato, G. Araújo, J. C. López-Hernández, R. Dahab
The invention is an improved hardener for use with phenolresorcinol-formaldehyde wood bonding adhesives. The hardener is conveniently made and shipped as a stable dry powdered material. It is then slurried in water at the point of use for convenience with continuously mixed and dispensed liquid-liquid, two part adhesive systems. The hardener comprises paraformaldehyde or alphapolyoxymethylene, fillers, viscosity and/or rheology control agents, and a solid acidic material. The latter ingredient is a critical component used to adjust the pH of an aqueous slurry to the range of 4.0 to 5.5. Oxalic acid is preferred. In this pH range, the formaldehyde polymers are stable and the slurried hardener does not give off significant formaldehyde odor for periods up to several days. Bonding performance is improved because the characteristics of the hardener and resulting adhesive have very little variation over time.
{"title":"A custom instruction approach for hardware and software implementations of finite field arithmetic over F263 using Gaussian normal bases","authors":"M. Juliato, G. Araújo, J. C. López-Hernández, R. Dahab","doi":"10.1109/FPT.2005.1568517","DOIUrl":"https://doi.org/10.1109/FPT.2005.1568517","url":null,"abstract":"The invention is an improved hardener for use with phenolresorcinol-formaldehyde wood bonding adhesives. The hardener is conveniently made and shipped as a stable dry powdered material. It is then slurried in water at the point of use for convenience with continuously mixed and dispensed liquid-liquid, two part adhesive systems. The hardener comprises paraformaldehyde or alphapolyoxymethylene, fillers, viscosity and/or rheology control agents, and a solid acidic material. The latter ingredient is a critical component used to adjust the pH of an aqueous slurry to the range of 4.0 to 5.5. Oxalic acid is preferred. In this pH range, the formaldehyde polymers are stable and the slurried hardener does not give off significant formaldehyde odor for periods up to several days. Bonding performance is improved because the characteristics of the hardener and resulting adhesive have very little variation over time.","PeriodicalId":6877,"journal":{"name":"2014 International Conference on Field-Programmable Technology (FPT)","volume":"27 1","pages":"5-12"},"PeriodicalIF":0.0,"publicationDate":"2005-12-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84417182","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2004-01-01DOI: 10.1109/FPT.2004.1393323
Esmail Chitalwala, T. El-Ghazawi, K. Gaj, N. Alexandridis, D. Poznanovic
{"title":"Effective system and performance benchmarking for reconfigurable computers","authors":"Esmail Chitalwala, T. El-Ghazawi, K. Gaj, N. Alexandridis, D. Poznanovic","doi":"10.1109/FPT.2004.1393323","DOIUrl":"https://doi.org/10.1109/FPT.2004.1393323","url":null,"abstract":"","PeriodicalId":6877,"journal":{"name":"2014 International Conference on Field-Programmable Technology (FPT)","volume":"16 1","pages":"453-456"},"PeriodicalIF":0.0,"publicationDate":"2004-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74666518","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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