Pub Date : 2016-06-01Epub Date: 2016-09-22DOI: 10.1109/VLSIC.2016.7573490
Xiao Wu, Yao Shi, Supreet Jeloka, Kaiyuan Yang, Inhee Lee, Dennis Sylvester, David Blaauw
We present a discontinuous harvesting approach for switch capacitor DC-DC converters that enables ultra-low power energy harvesting. By slowly accumulating charge on an input capacitor and then transferring it to a battery in burst-mode, switching and leakage losses in the DC-DC converter can be optimally traded-off with the loss due to non-ideal MPPT operation. The harvester uses a 15pW mode controller, an automatic conversion ratio modulator, and a moving sum charge pump for low startup energy upon a mode switch. In 180nm CMOS, the harvester achieves >40% end-to-end efficiency from 113pW to 1.5μW with 66pW minimum input power, marking a >10× improvement over prior ultra-low power harvesters.
{"title":"A 66pW Discontinuous Switch-Capacitor Energy Harvester for Self-Sustaining Sensor Applications.","authors":"Xiao Wu, Yao Shi, Supreet Jeloka, Kaiyuan Yang, Inhee Lee, Dennis Sylvester, David Blaauw","doi":"10.1109/VLSIC.2016.7573490","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573490","url":null,"abstract":"<p><p>We present a discontinuous harvesting approach for switch capacitor DC-DC converters that enables ultra-low power energy harvesting. By slowly accumulating charge on an input capacitor and then transferring it to a battery in burst-mode, switching and leakage losses in the DC-DC converter can be optimally traded-off with the loss due to non-ideal MPPT operation. The harvester uses a 15pW mode controller, an automatic conversion ratio modulator, and a moving sum charge pump for low startup energy upon a mode switch. In 180nm CMOS, the harvester achieves >40% end-to-end efficiency from 113pW to 1.5μW with 66pW minimum input power, marking a >10× improvement over prior ultra-low power harvesters.</p>","PeriodicalId":74899,"journal":{"name":"Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits","volume":"2016 ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2016-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/VLSIC.2016.7573490","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"34898873","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-06-01Epub Date: 2016-09-22DOI: 10.1109/VLSIC.2016.7573481
Wootaek Lim, Taekwang Jang, Inhee Lee, Hun-Seok Kim, Dennis Sylvester, David Blaauw
We present a sub-nW optical wake-up receiver for wireless sensor nodes. The wake-up receiver supports dual mode operation for both ultra-low standby power and high data rates, while canceling ambient in-band noise. In 0.18µm CMOS the receiver consumes 380pW in always-on wake-up mode and 28.1µW in fast RX mode at 250kbps.
{"title":"A 380pW Dual Mode Optical Wake-up Receiver with Ambient Noise Cancellation.","authors":"Wootaek Lim, Taekwang Jang, Inhee Lee, Hun-Seok Kim, Dennis Sylvester, David Blaauw","doi":"10.1109/VLSIC.2016.7573481","DOIUrl":"https://doi.org/10.1109/VLSIC.2016.7573481","url":null,"abstract":"<p><p>We present a sub-nW optical wake-up receiver for wireless sensor nodes. The wake-up receiver supports dual mode operation for both ultra-low standby power and high data rates, while canceling ambient in-band noise. In 0.18µm CMOS the receiver consumes 380pW in always-on wake-up mode and 28.1µW in fast RX mode at 250kbps.</p>","PeriodicalId":74899,"journal":{"name":"Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits","volume":"2016 ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2016-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/VLSIC.2016.7573481","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"34898874","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-16DOI: 10.1109/VLSIC.2015.7231361
Jolan De Boeck
Starting from the application perspective, this paper addresses on the needs for sensor node architecture, wireless communication, security and infrastructure for IoT.
本文从应用角度出发，论述了物联网对传感器节点架构、无线通信、安全和基础设施的需求。
{"title":"IoT: The Impact of Things","authors":"Jolan De Boeck","doi":"10.1109/VLSIC.2015.7231361","DOIUrl":"https://doi.org/10.1109/VLSIC.2015.7231361","url":null,"abstract":"Starting from the application perspective, this paper addresses on the needs for sensor node architecture, wireless communication, security and infrastructure for IoT.","PeriodicalId":74899,"journal":{"name":"Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits","volume":"20 1","pages":"82-"},"PeriodicalIF":0.0,"publicationDate":"2015-06-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75690327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-06-01DOI: 10.1109/VLSIC.2015.7231327
Seokhyeon Jeong, Wanyeong Jung, Dongsuk Jeon, Omer Berenfeld, Hakan Oral, Grant Kruger, David Blaauw, Dennis Sylvester
We present an 8-bit sub-ranging SAR ADC designed for bursty signals having long time periods with small code spread. A modified capacitive-DAC (CDAC) saves previous sample's MSB voltage and reuses it throughout subsequent conversions. This prevents unnecessary switching of large MSB capacitors as well as conversion cycles, reducing energy consumed in the comparator and digital logic and yielding total energy savings of 2.6×. In 0.18μm CMOS, the ADC consumes 120nW at 0.6V and 100kS/s with 46.9dB SNDR.
{"title":"A 120nW 8b Sub-ranging SAR ADC with Signal-Dependent Charge Recycling for Biomedical Applications.","authors":"Seokhyeon Jeong, Wanyeong Jung, Dongsuk Jeon, Omer Berenfeld, Hakan Oral, Grant Kruger, David Blaauw, Dennis Sylvester","doi":"10.1109/VLSIC.2015.7231327","DOIUrl":"https://doi.org/10.1109/VLSIC.2015.7231327","url":null,"abstract":"<p><p>We present an 8-bit sub-ranging SAR ADC designed for bursty signals having long time periods with small code spread. A modified capacitive-DAC (CDAC) saves previous sample's MSB voltage and reuses it throughout subsequent conversions. This prevents unnecessary switching of large MSB capacitors as well as conversion cycles, reducing energy consumed in the comparator and digital logic and yielding total energy savings of 2.6×. In 0.18μm CMOS, the ADC consumes 120nW at 0.6V and 100kS/s with 46.9dB SNDR.</p>","PeriodicalId":74899,"journal":{"name":"Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits","volume":"2015 ","pages":"C60-C61"},"PeriodicalIF":0.0,"publicationDate":"2015-06-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/VLSIC.2015.7231327","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"10525974","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2015-01-01DOI: 10.1109/VLSIC.2015.7231320
Saurabh Saxena, Guanghua Shu, R. Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, S. Kim, Woo-Seok Choi, P. Hanumolu
{"title":"A 2.8mW/Gb/s 14Gb/s serial link transceiver in 65nm CMOS","authors":"Saurabh Saxena, Guanghua Shu, R. Nandwana, Mrunmay Talegaonkar, Ahmed Elkholy, Tejasvi Anand, S. Kim, Woo-Seok Choi, P. Hanumolu","doi":"10.1109/VLSIC.2015.7231320","DOIUrl":"https://doi.org/10.1109/VLSIC.2015.7231320","url":null,"abstract":"","PeriodicalId":74899,"journal":{"name":"Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits","volume":"22 1","pages":"352-"},"PeriodicalIF":0.0,"publicationDate":"2015-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85466371","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2014-06-10DOI: 10.1109/VLSIC.2014.6858430
D. Yeager, W. Biederman, Nathan Narevsky, Jaclyn Leverett, R. Neely, J. Carmena, E. Alon, J. Rabaey
A 65nm CMOS 4.78mm 2 integrated neuromodulation SoC consumes 417μW from a 1.2V supply while operating 64 acquisition channels with epoch compression at an average firing rate of 50Hz and engaging two stimulators with a pulse width of 250μs/phase, differential current of 150μA, and a pulse frequency of 100Hz. Compared to the state of the art, this represents the lowest area and power for the highest integration complexity achieved to date.
{"title":"A 4.78mm2 fully-integrated neuromodulation SoC combining 64 acquisition channels with digital compression and simultaneous dual stimulation","authors":"D. Yeager, W. Biederman, Nathan Narevsky, Jaclyn Leverett, R. Neely, J. Carmena, E. Alon, J. Rabaey","doi":"10.1109/VLSIC.2014.6858430","DOIUrl":"https://doi.org/10.1109/VLSIC.2014.6858430","url":null,"abstract":"A 65nm CMOS 4.78mm\u0000 2 \u0000integrated neuromodulation SoC consumes 417μW from a 1.2V supply while operating 64 acquisition channels with epoch compression at an average firing rate of 50Hz and engaging two stimulators with a pulse width of 250μs/phase, differential current of 150μA, and a pulse frequency of 100Hz. Compared to the state of the art, this represents the lowest area and power for the highest integration complexity achieved to date.","PeriodicalId":74899,"journal":{"name":"Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits","volume":"54 1","pages":"1-2"},"PeriodicalIF":0.0,"publicationDate":"2014-06-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85327905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we performed the comparative analysis of stand-by leakage (when the circuit is idle), delay and dynamic power (when the circuit switches) of the three different parallel digital multiplier circuits implemented with two adder modules and Self Adjustable Voltage level circuit (SVL). The adder modules chosen were 28 transistor-conventional CMOS adder and 10 transistorStatic Energy Recovery CMOS adder (SERF) circuits. The multiplier modules chosen were 4Bits Array, 4bits Carry Save and 4Bits Baugh Wooley multipliers. At first, the circuits were simulated with adder modules without applying the SVL circuit. And secondly, SVL circuit was incorporated in the adder modules for simulation. In all the multiplier architectures chosen, less standby leakage power was observed being consumed by the SERF adder based multipliers applied with SVL circuit. The stand-by leakage power dissipation is 1.16μwatts in Bits array multiplier with SERF Adder applied with SVL vs. 1.39μwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit. It is 1.16μwatts in Carry Save multiplier with SERF Adder applied with SVL vs. 1.4μwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit. It is 1.67μwatts in Baugh Wooley multiplier with SERF Adder applied with SVl circuit vs. 2.74μwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit.
{"title":"Stand by Leakage Power Reduction in Nanoscale Static CMOS VLSI Multiplier Circuits Using Self Adjustable Voltage Level Circuit","authors":"Deeprose Subedi","doi":"10.5121/VLSIC.2012.3501","DOIUrl":"https://doi.org/10.5121/VLSIC.2012.3501","url":null,"abstract":"In this paper, we performed the comparative analysis of stand-by leakage (when the circuit is idle), delay and dynamic power (when the circuit switches) of the three different parallel digital multiplier circuits implemented with two adder modules and Self Adjustable Voltage level circuit (SVL). The adder modules chosen were 28 transistor-conventional CMOS adder and 10 transistorStatic Energy Recovery CMOS adder (SERF) circuits. The multiplier modules chosen were 4Bits Array, 4bits Carry Save and 4Bits Baugh Wooley multipliers. At first, the circuits were simulated with adder modules without applying the SVL circuit. And secondly, SVL circuit was incorporated in the adder modules for simulation. In all the multiplier architectures chosen, less standby leakage power was observed being consumed by the SERF adder based multipliers applied with SVL circuit. The stand-by leakage power dissipation is 1.16μwatts in Bits array multiplier with SERF Adder applied with SVL vs. 1.39μwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit. It is 1.16μwatts in Carry Save multiplier with SERF Adder applied with SVL vs. 1.4μwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit. It is 1.67μwatts in Baugh Wooley multiplier with SERF Adder applied with SVl circuit vs. 2.74μwatts in the same multiplier with CMOS 28T Adder applied with SVL circuit.","PeriodicalId":74899,"journal":{"name":"Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits","volume":"48 1","pages":"1-12"},"PeriodicalIF":0.0,"publicationDate":"2012-10-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91396268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Leakage Power Reduction and Analysis of CMOS Sequential Circuits","authors":"M. Rani","doi":"10.5121/VLSIC.2012.3102","DOIUrl":"https://doi.org/10.5121/VLSIC.2012.3102","url":null,"abstract":"","PeriodicalId":74899,"journal":{"name":"Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits","volume":"15 1","pages":"13-23"},"PeriodicalIF":0.0,"publicationDate":"2012-02-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91397283","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Area Efficient 3.3GHZ Phase Locked Loop with Four Multiple Output Using 45NM VLSI Technology","authors":"U. Belorkar, S. Ladhake","doi":"10.5121/VLSIC.2011.2110","DOIUrl":"https://doi.org/10.5121/VLSIC.2011.2110","url":null,"abstract":"","PeriodicalId":74899,"journal":{"name":"Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits","volume":"39 1","pages":"116-126"},"PeriodicalIF":0.0,"publicationDate":"2011-03-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"91396263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-01-01DOI: 10.1109/vlsic.2006.1705300
A. Maxim, R. Poorfard, Richard A. Johnson, P. Crawley, J. Kao, Z. Dong, M. Chennam, T. Nutt, D. Trager, M. Reid
This paper presents the first low-IF fully integrated receiver for DBS satellite TV applications realized in 0.13 μm CMOS. A wideband ring oscillator based frequency synthesizer having a large frequency step was used to downconvert a cluster of channels to a coarsely defined low-IF frequency, while the second downconversion to baseband was performed in the digital domain. Eliminating the oscillator inductors reduced the parasitic magnetic coupling from the digital core, allowing a single-chip integration of the sensitive tuner and the noisy digital demodulator. A significant die area reduction was achieved by using a single oscillator to cover the entire satellite TV spectrum, while a noise attenuator was cascaded with the PLL loop filter to reduce the equivalent tuning gain. The low-IF architecture allowed a discrete-step AGC that improves both tuner noise and linearity performance. Tuner gain and IF corner frequency were calibrated using replica ring oscillators that are tuned up to the onset of oscillations. The tuner specifications include: 90 dB gain range, 9 dB noise figure at max gain, +25 dBm IIP3 at min gain, 1.3°rms integrated phase noise, <50 dBc spurs, 0.7 W power consumption from dual 1.8/3.3-V supplies, and 1.8 x 1.2 mm 2 die area.
本文提出了首个采用0.13 μm CMOS实现的低中频全集成DBS卫星电视接收机。采用一种基于大频率步进的宽带环形振荡器频率合成器将一组信道下变频到粗略定义的低中频频率，同时在数字域进行第二次下变频到基带。消除振荡器电感减少了来自数字核心的寄生磁耦合，使敏感调谐器和噪声数字解调器的单芯片集成成为可能。通过使用单个振荡器覆盖整个卫星电视频谱，实现了显着的芯片面积减少，而噪声衰减器与锁相环滤波器级联以降低等效调谐增益。低中频架构允许离散步进AGC，提高调谐器噪声和线性性能。调谐器增益和中频角频率使用被调谐到振荡开始的复制环振荡器进行校准。调谐器规格包括:90db增益范围，最大增益时9db噪声系数，最小增益时+ 25dbm IIP3, 1.3°rms集成相位噪声，<50 dBc杂散，双1.8/3.3 v电源功耗0.7 W, 1.8 x 1.2 mm 2芯片面积。
{"title":"A fully integrated 0.13 μm CMOS low-IF DBS satellite tuner using automatic signal-path gain and bandwidth calibration","authors":"A. Maxim, R. Poorfard, Richard A. Johnson, P. Crawley, J. Kao, Z. Dong, M. Chennam, T. Nutt, D. Trager, M. Reid","doi":"10.1109/vlsic.2006.1705300","DOIUrl":"https://doi.org/10.1109/vlsic.2006.1705300","url":null,"abstract":"This paper presents the first low-IF fully integrated receiver for DBS satellite TV applications realized in 0.13 μm CMOS. A wideband ring oscillator based frequency synthesizer having a large frequency step was used to downconvert a cluster of channels to a coarsely defined low-IF frequency, while the second downconversion to baseband was performed in the digital domain. Eliminating the oscillator inductors reduced the parasitic magnetic coupling from the digital core, allowing a single-chip integration of the sensitive tuner and the noisy digital demodulator. A significant die area reduction was achieved by using a single oscillator to cover the entire satellite TV spectrum, while a noise attenuator was cascaded with the PLL loop filter to reduce the equivalent tuning gain. The low-IF architecture allowed a discrete-step AGC that improves both tuner noise and linearity performance. Tuner gain and IF corner frequency were calibrated using replica ring oscillators that are tuned up to the onset of oscillations. The tuner specifications include: 90 dB gain range, 9 dB noise figure at max gain, +25 dBm IIP3 at min gain, 1.3°rms integrated phase noise, <50 dBc spurs, 0.7 W power consumption from dual 1.8/3.3-V supplies, and 1.8 x 1.2 mm 2 die area.","PeriodicalId":74899,"journal":{"name":"Symposium on VLSI Circuits : [proceedings]. Symposium on VLSI Circuits","volume":"85 1 1","pages":"897-921"},"PeriodicalIF":0.0,"publicationDate":"2007-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87668541","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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