International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications最新文献
Pub Date : 2008-01-01DOI: 10.1109/FPL.2008.4630005
Sih Zaidi, A. Nabina, C. N. Canagarajah, J. Núñez-Yáñez
{"title":"International Conference on Field Programmable Logic and Applications, 2008 (FPL 2008), Heidelberg","authors":"Sih Zaidi, A. Nabina, C. N. Canagarajah, J. Núñez-Yáñez","doi":"10.1109/FPL.2008.4630005","DOIUrl":"https://doi.org/10.1109/FPL.2008.4630005","url":null,"abstract":"","PeriodicalId":93570,"journal":{"name":"International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications","volume":"3694 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2008-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86683536","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-12DOI: 10.1109/FPL.2007.4380615
J. Wawrzynek
The computer industry is at a cross-roads. The problems associated with scaling uniprocessor performance has forced all major computer manufactures to turn to multi-and many-core architectures. This sea change in processor design has created many opportunities for field programmable logic. In the RAMP project, we are developing an affordable and versatile multiprocessor emulation platform being built as a large collaborative effort. RAMP hardware, from processors to caches to networks, is implemented in FPGAs for flexibility, accuracy, visibility, cost and performance. It is designed to be composable, where different components can be quickly written, assembled and run. By using hardware rather than simulation, RAMP will be fast enough to run real codes and be useful to software. By using conventional instruction set architectures and providing peripheral support required by operating systems, RAMP will run full, unmodified software stacks. RAMP's intended audience includes anyone designing and using multiprocessor systems, including architecture researchers, software developers, and end users. In this talk, I will describe the background and current state of the RAMP development and related projects using our FPGA platform, the Berkeley emulation engine (BEE).
{"title":"Adventures with a Reconfigurable Research Platform","authors":"J. Wawrzynek","doi":"10.1109/FPL.2007.4380615","DOIUrl":"https://doi.org/10.1109/FPL.2007.4380615","url":null,"abstract":"The computer industry is at a cross-roads. The problems associated with scaling uniprocessor performance has forced all major computer manufactures to turn to multi-and many-core architectures. This sea change in processor design has created many opportunities for field programmable logic. In the RAMP project, we are developing an affordable and versatile multiprocessor emulation platform being built as a large collaborative effort. RAMP hardware, from processors to caches to networks, is implemented in FPGAs for flexibility, accuracy, visibility, cost and performance. It is designed to be composable, where different components can be quickly written, assembled and run. By using hardware rather than simulation, RAMP will be fast enough to run real codes and be useful to software. By using conventional instruction set architectures and providing peripheral support required by operating systems, RAMP will run full, unmodified software stacks. RAMP's intended audience includes anyone designing and using multiprocessor systems, including architecture researchers, software developers, and end users. In this talk, I will describe the background and current state of the RAMP development and related projects using our FPGA platform, the Berkeley emulation engine (BEE).","PeriodicalId":93570,"journal":{"name":"International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications","volume":"282 1","pages":"3"},"PeriodicalIF":0.0,"publicationDate":"2007-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80168426","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-12DOI: 10.1109/FPL.2007.4380614
M. Dickinson
Summary form only given. Today's FPGA applications are made up of many different functional elements; hardware blocks, software modules, I/O functions and on-chip interconnect fabrics are four major categories of these elements. I will explore some of the characteristics of these categories in order to provide insight into how the creation, or synthesis, of these functional elements can be automated as much as possible. In particular I will focus on unique benefits and challenges FPGAs present when considering such system design tools. The ideas will be illustrated by examples taken from applications in the networking and the image processing areas. These examples will illustrate progress to date as well as highlighting important areas of focus for future developments.
{"title":"System-Level Design for FPGAs","authors":"M. Dickinson","doi":"10.1109/FPL.2007.4380614","DOIUrl":"https://doi.org/10.1109/FPL.2007.4380614","url":null,"abstract":"Summary form only given. Today's FPGA applications are made up of many different functional elements; hardware blocks, software modules, I/O functions and on-chip interconnect fabrics are four major categories of these elements. I will explore some of the characteristics of these categories in order to provide insight into how the creation, or synthesis, of these functional elements can be automated as much as possible. In particular I will focus on unique benefits and challenges FPGAs present when considering such system design tools. The ideas will be illustrated by examples taken from applications in the networking and the image processing areas. These examples will illustrate progress to date as well as highlighting important areas of focus for future developments.","PeriodicalId":93570,"journal":{"name":"International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications","volume":"8 1","pages":"2"},"PeriodicalIF":0.0,"publicationDate":"2007-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87416810","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-12DOI: 10.1109/FPL.2007.4380616
S. Trimberger
Summary form only given. Over the past twenty years, FPGAs evolved from simple glue-logic chips to complex systems-on-a-chip. This change can be viewed having distinct phases, each with different architecture, tools and methodology requirements. Are we now facing another phase change? Will FPGAs continue to evolve incrementally or are we about to see a radical change in field programmable logic? This talk traces the evolution of programmable logic based on the technological opportunities and pressures. Those pressures are changing, and the change will affect not only device architecture, but also design tools, methodology and even our business models. This talk discusses today's technological opportunities and pressures, and how those pressures will define tomorrow's FPGAs.
{"title":"Redefining the FPGA for the Next Generation","authors":"S. Trimberger","doi":"10.1109/FPL.2007.4380616","DOIUrl":"https://doi.org/10.1109/FPL.2007.4380616","url":null,"abstract":"Summary form only given. Over the past twenty years, FPGAs evolved from simple glue-logic chips to complex systems-on-a-chip. This change can be viewed having distinct phases, each with different architecture, tools and methodology requirements. Are we now facing another phase change? Will FPGAs continue to evolve incrementally or are we about to see a radical change in field programmable logic? This talk traces the evolution of programmable logic based on the technological opportunities and pressures. Those pressures are changing, and the change will affect not only device architecture, but also design tools, methodology and even our business models. This talk discusses today's technological opportunities and pressures, and how those pressures will define tomorrow's FPGAs.","PeriodicalId":93570,"journal":{"name":"International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications","volume":"36 1","pages":"4"},"PeriodicalIF":0.0,"publicationDate":"2007-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74940652","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-11-12DOI: 10.1109/FPL.2007.4380613
Ajay V. Bhatt
Summary form only given. Moore's law has enabled the current trend toward multi-core computing that is dramatically increasing performance and power efficiency. I/O interconnects are on a similar growth path of increasing performance and efficiency. As computing requirements become more complex, new strategies evolve to provide the performance necessary for data-and calculation-intensive applications. A growing such strategy is the use of specialized accelerators to enhance the performance of specific tasks or functions. Broadly speaking, an accelerator is a device that attaches to a computing system, providing optimal performance at reduced cost and/or power for a specialized task. Examples of emerging applications for which accelerators may be suitable are photorealistic graphics, financial simulation, and climate modeling. The development of specialized application accelerators is happening today. However, they do not share a common attach point, and have no common architecture or programming model. An industry framework that economically and efficiently enables specialized acceleration is highly desirable. This talk will focus on a new architectural framework for the attached application accelerators called Geneseo. The talk will provide an overview of the Geneseo interconnect and software architecture and provide insight in to proposed improvements in available bandwidth, latency, efficiency and software interface.
{"title":"The Intel Geneseo Project","authors":"Ajay V. Bhatt","doi":"10.1109/FPL.2007.4380613","DOIUrl":"https://doi.org/10.1109/FPL.2007.4380613","url":null,"abstract":"Summary form only given. Moore's law has enabled the current trend toward multi-core computing that is dramatically increasing performance and power efficiency. I/O interconnects are on a similar growth path of increasing performance and efficiency. As computing requirements become more complex, new strategies evolve to provide the performance necessary for data-and calculation-intensive applications. A growing such strategy is the use of specialized accelerators to enhance the performance of specific tasks or functions. Broadly speaking, an accelerator is a device that attaches to a computing system, providing optimal performance at reduced cost and/or power for a specialized task. Examples of emerging applications for which accelerators may be suitable are photorealistic graphics, financial simulation, and climate modeling. The development of specialized application accelerators is happening today. However, they do not share a common attach point, and have no common architecture or programming model. An industry framework that economically and efficiently enables specialized acceleration is highly desirable. This talk will focus on a new architectural framework for the attached application accelerators called Geneseo. The talk will provide an overview of the Geneseo interconnect and software architecture and provide insight in to proposed improvements in available bandwidth, latency, efficiency and software interface.","PeriodicalId":93570,"journal":{"name":"International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications","volume":"22 1","pages":"1"},"PeriodicalIF":0.0,"publicationDate":"2007-11-12","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"82817715","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2007-01-01DOI: 10.1109/FPL.2007.4380742
Tamer Güdü
{"title":"A New Scalable Hardware Architecture for RSA Algorithm","authors":"Tamer Güdü","doi":"10.1109/FPL.2007.4380742","DOIUrl":"https://doi.org/10.1109/FPL.2007.4380742","url":null,"abstract":"","PeriodicalId":93570,"journal":{"name":"International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications","volume":"12 1","pages":"670-674"},"PeriodicalIF":0.0,"publicationDate":"2007-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87543900","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
I will relate the story of a disruptive technology in hardware compilation and reconfigurable computing. Conceived in academia, it led first to a ?spin-out? and then to a public company. After a career spanning computing and electronics in both industrial and academic environments I started a new research group at Oxford University in 1990. The ?big idea? was to develop a method of automatically implementing computer programs directly in parallel hardware - or ?hardware compilation?. I called the result ?Computing Without Computers? as once the compilation has been done, there is no sequential computer around to slow the computation down. However, there is a big disconnect between the worlds of academia and commerce. Despite welcome changes over the last ten years to make it easier for academics to create spinout companies, it is still a hard trick to pull off. Some of the things that can, and did, go wrong will be highlighted. I will try to abstract some of the hard lessons learned along the way. For example, I have come to believe that attempting to copy the entrepreneurial success of others is much less likely to be useful than avoiding their failures. The talk will cover the creation of the technology and the company, raising finance for it and the (unfinished) story of how to encourage the adoption of a disruptive product in the market-place. The spinout experience changed my life in completely unexpected ways.
{"title":"Academia to IPO - A Modern Odyssey","authors":"I. Page","doi":"10.1109/FPL.2006.311186","DOIUrl":"https://doi.org/10.1109/FPL.2006.311186","url":null,"abstract":"I will relate the story of a disruptive technology in hardware compilation and reconfigurable computing. Conceived in academia, it led first to a ?spin-out? and then to a public company. After a career spanning computing and electronics in both industrial and academic environments I started a new research group at Oxford University in 1990. The ?big idea? was to develop a method of automatically implementing computer programs directly in parallel hardware - or ?hardware compilation?. I called the result ?Computing Without Computers? as once the compilation has been done, there is no sequential computer around to slow the computation down. However, there is a big disconnect between the worlds of academia and commerce. Despite welcome changes over the last ten years to make it easier for academics to create spinout companies, it is still a hard trick to pull off. Some of the things that can, and did, go wrong will be highlighted. I will try to abstract some of the hard lessons learned along the way. For example, I have come to believe that attempting to copy the entrepreneurial success of others is much less likely to be useful than avoiding their failures. The talk will cover the creation of the technology and the company, raising finance for it and the (unfinished) story of how to encourage the adoption of a disruptive product in the market-place. The spinout experience changed my life in completely unexpected ways.","PeriodicalId":93570,"journal":{"name":"International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications","volume":"12 Suppl 1 1","pages":"1"},"PeriodicalIF":0.0,"publicationDate":"2006-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76563241","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Summary form only given. FPGAs fabrics have become much more complex, including a range of hard IP for memory, DSP and I/O functions. FPGAs have also become much larger, supporting much larger designs and a need to raise the design abstraction level. DSM effects are threatening the FPGA abstraction in which these effects are hidden from the designer by clever circuit design and guard banding. For example, at 400 MHz in a 45 nm FPGA, on chip variation (OCV) will become such a large portion of cycle time that simply guard banding will leave too much performance on the table. FPGAs are also expanding into new markets where cost and power consumption are more important than performance. These changes present many design tool challenges and create numerous opportunities for innovation.
{"title":"FPGAs at 65NM and Beyond - Powerful New FPGAs Bring New Challenges","authors":"K. McElvain","doi":"10.1109/FPL.2006.311184","DOIUrl":"https://doi.org/10.1109/FPL.2006.311184","url":null,"abstract":"Summary form only given. FPGAs fabrics have become much more complex, including a range of hard IP for memory, DSP and I/O functions. FPGAs have also become much larger, supporting much larger designs and a need to raise the design abstraction level. DSM effects are threatening the FPGA abstraction in which these effects are hidden from the designer by clever circuit design and guard banding. For example, at 400 MHz in a 45 nm FPGA, on chip variation (OCV) will become such a large portion of cycle time that simply guard banding will leave too much performance on the table. FPGAs are also expanding into new markets where cost and power consumption are more important than performance. These changes present many design tool challenges and create numerous opportunities for innovation.","PeriodicalId":93570,"journal":{"name":"International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications","volume":"13 1","pages":"1"},"PeriodicalIF":0.0,"publicationDate":"2006-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80343684","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-10DOI: 10.1109/FPL.2005.1515787
Klaus Danne, M. Platzner
This paper deals with scheduling periodic real-time tasks on reconfigurable hardware devices, such as FPGAs. Reconfigurable hardware devices are increasingly used in embedded systems. To utilize these devices also for systems with real-time constraints, predictable task scheduling is required. We formalize the periodic task scheduling problem and propose two preemptive scheduling algorithms. The first is an adaption of the well-known earliest deadline first (EDF) technique to the FPGA execution model. Although the algorithm reveals good scheduling performance, it lacks an efficient schedulability test and requires a high number of FPGA configurations. The second algorithm uses the concept of servers that reserve area and execution time for other tasks. Tasks are successively merged into servers, which are then scheduled sequentially. While this method is inferior to the EDF-based technique regarding schedulability, it comes with a fast schedulability test and greatly reduces the number of required FPGA configurations.
{"title":"A Heuristic Approach to Schedule Periodic Real-Time Tasks on Reconfigurable Hardware","authors":"Klaus Danne, M. Platzner","doi":"10.1109/FPL.2005.1515787","DOIUrl":"https://doi.org/10.1109/FPL.2005.1515787","url":null,"abstract":"This paper deals with scheduling periodic real-time tasks on reconfigurable hardware devices, such as FPGAs. Reconfigurable hardware devices are increasingly used in embedded systems. To utilize these devices also for systems with real-time constraints, predictable task scheduling is required. We formalize the periodic task scheduling problem and propose two preemptive scheduling algorithms. The first is an adaption of the well-known earliest deadline first (EDF) technique to the FPGA execution model. Although the algorithm reveals good scheduling performance, it lacks an efficient schedulability test and requires a high number of FPGA configurations. The second algorithm uses the concept of servers that reserve area and execution time for other tasks. Tasks are successively merged into servers, which are then scheduled sequentially. While this method is inferior to the EDF-based technique regarding schedulability, it comes with a fast schedulability test and greatly reduces the number of required FPGA configurations.","PeriodicalId":93570,"journal":{"name":"International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications","volume":"29 1","pages":"568-573"},"PeriodicalIF":0.0,"publicationDate":"2005-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78155645","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2005-10-10DOI: 10.1109/FPL.2005.1515782
J. Martínez, F. J. Toledo-Moreo, F. J. Garrigós, J. M. Ferrández
In this paper we propose an area-time efficient architecture for the realization of self-clocked MAC filters on FPGA. First, the self-timed 4-phase oscillator/counter is analyzed and characterized, showing experimental results in comparison with simulation foreseen. Next, the proposed filter architecture, based on circular memories, is described and efficiently implemented as an IP module using device primitives and relative location constraints. Finally, an example using the proposed architecture is implemented on an FPGA and compared with a standard IP filter of similar characteristics, pointing out the advantages of our approach.
{"title":"FPGA Implementation of an Area-Time Efficient FIR Filter Core Using a Self-Clocked Approach","authors":"J. Martínez, F. J. Toledo-Moreo, F. J. Garrigós, J. M. Ferrández","doi":"10.1109/FPL.2005.1515782","DOIUrl":"https://doi.org/10.1109/FPL.2005.1515782","url":null,"abstract":"In this paper we propose an area-time efficient architecture for the realization of self-clocked MAC filters on FPGA. First, the self-timed 4-phase oscillator/counter is analyzed and characterized, showing experimental results in comparison with simulation foreseen. Next, the proposed filter architecture, based on circular memories, is described and efficiently implemented as an IP module using device primitives and relative location constraints. Finally, an example using the proposed architecture is implemented on an FPGA and compared with a standard IP filter of similar characteristics, pointing out the advantages of our approach.","PeriodicalId":93570,"journal":{"name":"International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications","volume":"10 1","pages":"547-550"},"PeriodicalIF":0.0,"publicationDate":"2005-10-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"86495224","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications
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