International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications最新文献
Nina Engelhardt, C.-H. Dominic Hung, Hayden Kwok-Hay So
In this paper, we present a multi-FPGA graph processing framework and an accompanying performance model. Our framework emphasizes programmability, requiring minimal user input beyond providing the application kernel and the dataset. The framework predicts the performance of the system based on the algorithm characteristics and problem size and automatically selects the optimal FPGA configuration. We implement our system on an experimental 4-FPGA platform and compare the results to the predicted performance.
{"title":"Performance-Driven System Generation for Distributed Vertex-Centric Graph Processing on Multi-FPGA Systems","authors":"Nina Engelhardt, C.-H. Dominic Hung, Hayden Kwok-Hay So","doi":"10.1109/FPL.2018.00043","DOIUrl":"https://doi.org/10.1109/FPL.2018.00043","url":null,"abstract":"In this paper, we present a multi-FPGA graph processing framework and an accompanying performance model. Our framework emphasizes programmability, requiring minimal user input beyond providing the application kernel and the dataset. The framework predicts the performance of the system based on the algorithm characteristics and problem size and automatically selects the optimal FPGA configuration. We implement our system on an experimental 4-FPGA platform and compare the results to the predicted performance.","PeriodicalId":93570,"journal":{"name":"International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications","volume":"15 1","pages":"215-218"},"PeriodicalIF":0.0,"publicationDate":"2018-08-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73241795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-09-01DOI: 10.23919/FPL.2017.8056755
I. Bolsens
Smart Systems create new challenges for semiconductor components that need to provide, at one hand, the ease of software programmability and, on the other hand, the capability of hardware efficiency. This dichotomy is driven by, on the one hand, the need for a software stack that supports flexibility, scalability, fast development cycles and, on the other hand, the need for hardware optimization to support performance, efficiency and cost. In this talk, we will discuss the technical trends in major market segments such as datacenters, 5G wireless infrastructure and software defined networking and the resulting requirements for semiconductor platforms, both from hardware and software perspective. To provide an answer to these challenges, it will be demonstrated on how FPGA technology is evolving from a programmable hardware solution catering to ASIC refugees towards an All Programmable architecture empowering system and software engineers.
{"title":"\"All programmable FPGA, providing hardware efficiency to software programmers\"","authors":"I. Bolsens","doi":"10.23919/FPL.2017.8056755","DOIUrl":"https://doi.org/10.23919/FPL.2017.8056755","url":null,"abstract":"Smart Systems create new challenges for semiconductor components that need to provide, at one hand, the ease of software programmability and, on the other hand, the capability of hardware efficiency. This dichotomy is driven by, on the one hand, the need for a software stack that supports flexibility, scalability, fast development cycles and, on the other hand, the need for hardware optimization to support performance, efficiency and cost. In this talk, we will discuss the technical trends in major market segments such as datacenters, 5G wireless infrastructure and software defined networking and the resulting requirements for semiconductor platforms, both from hardware and software perspective. To provide an answer to these challenges, it will be demonstrated on how FPGA technology is evolving from a programmable hardware solution catering to ASIC refugees towards an All Programmable architecture empowering system and software engineers.","PeriodicalId":93570,"journal":{"name":"International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications","volume":"70 1","pages":"1-3"},"PeriodicalIF":0.0,"publicationDate":"2017-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79728404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-29DOI: 10.1109/FPL.2009.5272564
P. Alfke
Recently, Xilinx introduced two new FPGA families, Virtex-6 and Spartan-6, closely related in architecture, but each optimized for different markets and applications: Virtex-6 for high performance, features and capacity; Spartan-6 for low cost and low power consumption. Both families take advantage of 40/45 nm technology, and both are derived from the successful Virtex-5 architecture. I will give an overview of the salient features and capabilities of both families. Then I will give a peek into the future, explaining the impact of rapidly rising development costs for all future technology nodes. That limits ASICs and ASSPs to serve only high-volume opportunities, and offers unique advantages for FPGAs. But we must overcome certain technical difficulties, and streamline the user's design process.
{"title":"Virtex-6 and Spartan-6, plus a look into the future","authors":"P. Alfke","doi":"10.1109/FPL.2009.5272564","DOIUrl":"https://doi.org/10.1109/FPL.2009.5272564","url":null,"abstract":"Recently, Xilinx introduced two new FPGA families, Virtex-6 and Spartan-6, closely related in architecture, but each optimized for different markets and applications: Virtex-6 for high performance, features and capacity; Spartan-6 for low cost and low power consumption. Both families take advantage of 40/45 nm technology, and both are derived from the successful Virtex-5 architecture. I will give an overview of the salient features and capabilities of both families. Then I will give a peek into the future, explaining the impact of rapidly rising development costs for all future technology nodes. That limits ASICs and ASSPs to serve only high-volume opportunities, and offers unique advantages for FPGAs. But we must overcome certain technical difficulties, and streamline the user's design process.","PeriodicalId":93570,"journal":{"name":"International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications","volume":"153 1","pages":"5"},"PeriodicalIF":0.0,"publicationDate":"2009-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75438409","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-29DOI: 10.1109/FPL.2009.5272567
Vaughn Betz
FPGA companies are amongst the earliest adopters of next-generation process technology. This involves many challenges, including power management, device modeling, increasing I/O performance to match the computational capacity, and enabling very large designs to be completed quickly.
{"title":"FPGA challenges and opportunities at 40nm and beyond","authors":"Vaughn Betz","doi":"10.1109/FPL.2009.5272567","DOIUrl":"https://doi.org/10.1109/FPL.2009.5272567","url":null,"abstract":"FPGA companies are amongst the earliest adopters of next-generation process technology. This involves many challenges, including power management, device modeling, increasing I/O performance to match the computational capacity, and enabling very large designs to be completed quickly.","PeriodicalId":93570,"journal":{"name":"International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications","volume":"49 1","pages":"4"},"PeriodicalIF":0.0,"publicationDate":"2009-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83795170","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-29DOI: 10.1109/FPL.2009.5272571
P. Athanas
In an engineering perspective, agility is one property that a designer must consider when creating a product that is expected to undergo change throughout its lifetime. For embedded computing systems, traditionally the system hardware is fixed, and the system software provides the means of achieving agility. Altering software functionality is relatively easy to do, and software compile times are fast. There are situations, however, where for performance reasons, agility beyond software is needed. In theory, FPGAs offer a degree of agility to system hardware through the mechanism of altering functionality under software control. In practice, however, FPGAs are not very agile at all, requiring long design times and complicated compilation processes. In this talk, the use-model of contemporary FPGAs is reexamined, and alternative ways of hardware/software interaction are presented with the objective of achieving a higher degree of hardware agility.
{"title":"In search of agile hardware","authors":"P. Athanas","doi":"10.1109/FPL.2009.5272571","DOIUrl":"https://doi.org/10.1109/FPL.2009.5272571","url":null,"abstract":"In an engineering perspective, agility is one property that a designer must consider when creating a product that is expected to undergo change throughout its lifetime. For embedded computing systems, traditionally the system hardware is fixed, and the system software provides the means of achieving agility. Altering software functionality is relatively easy to do, and software compile times are fast. There are situations, however, where for performance reasons, agility beyond software is needed. In theory, FPGAs offer a degree of agility to system hardware through the mechanism of altering functionality under software control. In practice, however, FPGAs are not very agile at all, requiring long design times and complicated compilation processes. In this talk, the use-model of contemporary FPGAs is reexamined, and alternative ways of hardware/software interaction are presented with the objective of achieving a higher degree of hardware agility.","PeriodicalId":93570,"journal":{"name":"International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications","volume":"84 1","pages":"2"},"PeriodicalIF":0.0,"publicationDate":"2009-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"76185572","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2009-09-29DOI: 10.1109/FPL.2009.5272566
Jonathan Rose
As integrated circuit fabrication processes continue to provide exponential increases in density of transistors with each generation, the question of what to do with those transistors becomes ever more interesting. The most fundamental part of that question is the global organization of the structures created from the transistors, most commonly referred to as the *architecture* of the device.
{"title":"The evolution of architecture exploration of programmable devices","authors":"Jonathan Rose","doi":"10.1109/FPL.2009.5272566","DOIUrl":"https://doi.org/10.1109/FPL.2009.5272566","url":null,"abstract":"As integrated circuit fabrication processes continue to provide exponential increases in density of transistors with each generation, the question of what to do with those transistors becomes ever more interesting. The most fundamental part of that question is the global organization of the structures created from the transistors, most commonly referred to as the *architecture* of the device.","PeriodicalId":93570,"journal":{"name":"International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications","volume":"21 1","pages":"3"},"PeriodicalIF":0.0,"publicationDate":"2009-09-29","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73569202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-23DOI: 10.1109/FPL.2008.4629895
I. Bolsens
As FPGApsilas become the heart of embedded systems, the use of these programmable platforms becomes more pervasive in markets such as automotive, consumer electronics, industrial and medical. We will discuss the opportunities for FPGAs as they evolve to solve the challenges for transforming, transporting and computing data. We will describe a vision of future use models of FPGApsilas and the implications on system architectures and software environments.
{"title":"FPGA: The future platform for transforming, transporting and computing data","authors":"I. Bolsens","doi":"10.1109/FPL.2008.4629895","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629895","url":null,"abstract":"As FPGApsilas become the heart of embedded systems, the use of these programmable platforms becomes more pervasive in markets such as automotive, consumer electronics, industrial and medical. We will discuss the opportunities for FPGAs as they evolve to solve the challenges for transforming, transporting and computing data. We will describe a vision of future use models of FPGApsilas and the implications on system architectures and software environments.","PeriodicalId":93570,"journal":{"name":"International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications","volume":"235 1","pages":"1"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75741685","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-23DOI: 10.1109/FPL.2008.4629897
D. Werthimer
Summary form only given. Next generation radio telescopes, such as the Allen telescope array and the square kilometer array are composed of hundreds to thousands of smaller telescopes; these large arrays require peta-ops per second of real time processing to combine telescope signals, generate images, and search for radio signals from extraterrestrial civilizations. I will describe these telescopes, their instrumentation, and the motivation for peta-op/sec FPGA systems.
{"title":"Searching for ET with FPGA'S","authors":"D. Werthimer","doi":"10.1109/FPL.2008.4629897","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629897","url":null,"abstract":"Summary form only given. Next generation radio telescopes, such as the Allen telescope array and the square kilometer array are composed of hundreds to thousands of smaller telescopes; these large arrays require peta-ops per second of real time processing to combine telescope signals, generate images, and search for radio signals from extraterrestrial civilizations. I will describe these telescopes, their instrumentation, and the motivation for peta-op/sec FPGA systems.","PeriodicalId":93570,"journal":{"name":"International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications","volume":"30 1","pages":"3"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83370803","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-23DOI: 10.1109/FPL.2008.4629896
L. Musa
CERN, the European Organization for Nuclear Research, is the worldpsilas largest particle physics centre. It provides state-of-the-art scientific facilities to use in exploring what matter is made of, and what forces hold it together. Observing phenomena at the subatomic level requires extraordinary instruments, particle accelerators and particle detectors. In a particle accelerator, beams of subatomic particles are boosted to nearly the speed of light and then brought into collision with either a stationary target or another beam of accelerated particles coming head-on. Each of these collisions is called an event. Each event is very complex since lots of particles are produced. In order to look for these various particles and decay products, multi-component detectors that study different aspects of an event are built around the collision point. Each component of a modern detector is used for measuring particle energies and momentum, and/or distinguishing different particle types. Most modern particle detectors produce tiny electrical signals that can be treated and recorded as computer data. Detectors in high-energy physics characteristically produce great quantities of data, whose acquisition, reduction and interpretation have made up a significant component of the experimental effort both technically and financially. For the past 60 years, the historic advances in elementary particle physics are linked to the progress in accelerator and detector technologies, as well as in the associated readout electronics technologies. Owing to the continuous evolution in the semiconductor industry, the front-end and readout electronics for High Energy Physics have been evolving to satisfy decade after decade the increasing demands of the experiments. Very deep submicron CMOS FPGAs not only offer speed, density, computational power and flexibility, but also intrinsic radiation tolerance. ASICs and FPGAs are largely used in many different areas in High Energy Physics: controls, monitoring, signal processing, data compression, high-speed data links, online reconstruction and selection of the collision events. This contribution aims at reviewing the important role that FPGAs play in modern High Energy Physics Experiments by presenting some of the most advanced and peculiar applications of FPGAs at CERN.
{"title":"FPGAS in high energy physics experiments at CERN","authors":"L. Musa","doi":"10.1109/FPL.2008.4629896","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629896","url":null,"abstract":"CERN, the European Organization for Nuclear Research, is the worldpsilas largest particle physics centre. It provides state-of-the-art scientific facilities to use in exploring what matter is made of, and what forces hold it together. Observing phenomena at the subatomic level requires extraordinary instruments, particle accelerators and particle detectors. In a particle accelerator, beams of subatomic particles are boosted to nearly the speed of light and then brought into collision with either a stationary target or another beam of accelerated particles coming head-on. Each of these collisions is called an event. Each event is very complex since lots of particles are produced. In order to look for these various particles and decay products, multi-component detectors that study different aspects of an event are built around the collision point. Each component of a modern detector is used for measuring particle energies and momentum, and/or distinguishing different particle types. Most modern particle detectors produce tiny electrical signals that can be treated and recorded as computer data. Detectors in high-energy physics characteristically produce great quantities of data, whose acquisition, reduction and interpretation have made up a significant component of the experimental effort both technically and financially. For the past 60 years, the historic advances in elementary particle physics are linked to the progress in accelerator and detector technologies, as well as in the associated readout electronics technologies. Owing to the continuous evolution in the semiconductor industry, the front-end and readout electronics for High Energy Physics have been evolving to satisfy decade after decade the increasing demands of the experiments. Very deep submicron CMOS FPGAs not only offer speed, density, computational power and flexibility, but also intrinsic radiation tolerance. ASICs and FPGAs are largely used in many different areas in High Energy Physics: controls, monitoring, signal processing, data compression, high-speed data links, online reconstruction and selection of the collision events. This contribution aims at reviewing the important role that FPGAs play in modern High Energy Physics Experiments by presenting some of the most advanced and peculiar applications of FPGAs at CERN.","PeriodicalId":93570,"journal":{"name":"International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications","volume":"115 1","pages":"2"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77749398","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2008-09-23DOI: 10.1109/FPL.2008.4629898
O. Wohlmuth
Driven by the increasing demand of high performance computing (HPC) systems in scientific and commercial computing on one hand and the limitation of todays processor technology (memory wall, frequency wall, power wall) on the other hand there is a growing interest in highly scalable and high-performance computer architectures based on application-optimized processors and computation technology. Examples of specialized high-performance processors are graphic processing units (GPUs) and game processors, e.g. the Cell/B.E. processor, which are capable of performing more than the specific computations for which they were designed. A big challenge especially in HPC is to integrate those specialized processors into a system architecture which is able to provide the I/O and sustained system performance in a massively parallel computation system. An example is the worldpsilas fastest supercomputer with a peak performance of 1.7 petaflops which is a hybrid design based on standard dual-core and specialized game processors which are connected by a specific I/O expansion board. Another highly innovative and scalable computer design based on game processors is the so-called ldquoQCD parallel computer based on cell technologyrdquo (QPACE) which consists of an application-optimized network chip implemented on FPGA overcoming the I/O limitations of existing network chips. This talk will provide an overview and insight into the QPACE architecture concept with focus on the application-optimized network implemented on FPGAs and will discuss scalable computer design concepts in HPC based on specialized high performance processors.
{"title":"Keynote: High performance computing based on FPGAS","authors":"O. Wohlmuth","doi":"10.1109/FPL.2008.4629898","DOIUrl":"https://doi.org/10.1109/FPL.2008.4629898","url":null,"abstract":"Driven by the increasing demand of high performance computing (HPC) systems in scientific and commercial computing on one hand and the limitation of todays processor technology (memory wall, frequency wall, power wall) on the other hand there is a growing interest in highly scalable and high-performance computer architectures based on application-optimized processors and computation technology. Examples of specialized high-performance processors are graphic processing units (GPUs) and game processors, e.g. the Cell/B.E. processor, which are capable of performing more than the specific computations for which they were designed. A big challenge especially in HPC is to integrate those specialized processors into a system architecture which is able to provide the I/O and sustained system performance in a massively parallel computation system. An example is the worldpsilas fastest supercomputer with a peak performance of 1.7 petaflops which is a hybrid design based on standard dual-core and specialized game processors which are connected by a specific I/O expansion board. Another highly innovative and scalable computer design based on game processors is the so-called ldquoQCD parallel computer based on cell technologyrdquo (QPACE) which consists of an application-optimized network chip implemented on FPGA overcoming the I/O limitations of existing network chips. This talk will provide an overview and insight into the QPACE architecture concept with focus on the application-optimized network implemented on FPGAs and will discuss scalable computer design concepts in HPC based on specialized high performance processors.","PeriodicalId":93570,"journal":{"name":"International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications","volume":"24 1","pages":"4"},"PeriodicalIF":0.0,"publicationDate":"2008-09-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"87087920","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
International Conference on Field-programmable Logic and Applications : [proceedings]. International Conference on Field-Programmable Logic and Applications
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