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Bit-sliced realization of a CMOVE architecture microcomputer CMOVE结构微机的位切片实现
Euromicro Newsletter
Pub Date : 1980-11-01 DOI: 10.1016/0303-1268(80)90082-6
Helnye Azaria, Daniel Tabak

A bit-sliced hardware realization of a CMOVE Architecture microcomputer is proposed. AMD 2900 euqipment is used in most parts of the system, currently under construction. A comparative study of performance of arithmetic operations, between the CMOVE processor and existing microprocessors (Intel 8085, 8086, Motorola 68000 and Zilog 8000) has been conducted for both single and multiple precision addition and multiplication. CMOVE turned out to be faster, particularly for multiplications at any precision level. In single-byte addition its performance is comparable to Intel 8085, which is even slightly faster than the CMOVE for this case. An extension of the system into a distributed processor with a capability of connection to a large number of peripherals has been proposed.

提出了一种CMOVE结构微型计算机的位片硬件实现方法。AMD 2900设备用于系统的大部分部分，目前正在建设中。对CMOVE处理器和现有微处理器（Intel 8085、8086、Motorola 68000和Zilog 8000）在单精度和多精度加法和乘法方面的算术运算性能进行了比较研究。CMOVE被证明是更快的，特别是对于任何精度级别的乘法。在单字节加法中，它的性能与Intel 8085相当，在这种情况下甚至比CMOVE稍快。已经提出将该系统扩展为具有连接到大量外围设备的能力的分布式处理器。
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引用次数: 5
A general-purpose multi-micro-system with high fault-tolerance and unlimited system-capacity 具有高容错性和无限系统容量的通用多微系统
Euromicro Newsletter
Pub Date : 1980-11-01 DOI: 10.1016/0303-1268(80)90084-X
R Männer, W Schneider , B De Luigi , K Posner

The Heidelberg Multi-Processor-System is described. It will be used for online-data reduction, trigger processing, image processing, etc. The system consists of typically up to 300 processor-modules and several global memory modules. They are interconnected by a multi-common-bus for data transfer and a multiple synchronization bus for processor/task-scheduling. Hardware and software have been designed to be free of bottle-necks: the number of modules and the bus capacity are not limited. An increased system size does not lead to increased memory or bus interferences. The system has also been designed to be fault-tolerant: hardware and software are organized totally decentralized; most temporary and permanent memory and bus transfer faults are corrected by hardware. Defective modules or busses are disabled by software; the system continues its operation with almost the same speed.

介绍了海德堡多处理器系统。它将用于在线数据缩减、触发处理、图像处理等。该系统通常由多达300个处理器模块和几个全局内存模块组成。它们通过用于数据传输的多公共总线和用于处理器/任务调度的多同步总线互连。硬件和软件的设计没有瓶颈：模块的数量和总线容量不受限制。系统大小的增加不会导致内存或总线干扰的增加。该系统也被设计为容错：硬件和软件完全分散组织；大多数临时和永久存储器和总线传输故障都是通过硬件来纠正的。有缺陷的模块或总线被软件禁用；系统以几乎相同的速度继续其操作。
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引用次数: 3
Function-microcomputers for computer graphics 计算机制图用微型计算机功能
Euromicro Newsletter
Pub Date : 1980-11-01 DOI: 10.1016/0303-1268(80)90090-5
G. Szanto, J. Bos
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引用次数: 0
Standard specification for proposed microcomputer system backplanes P896/D2 拟建微机系统背板P896/D2的标准规范
Euromicro Newsletter
Pub Date : 1980-11-01 DOI: 10.1016/0303-1268(80)90080-2
A. Allison
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引用次数: 0
Introduction to the special section: Papers presented as ‘short notes’ at the EUROMICRO 80 symposium 特别部分介绍:在EUROMICRO 80研讨会上作为“简短笔记”提出的论文
Euromicro Newsletter
Pub Date : 1980-11-01 DOI: 10.1016/0303-1268(80)90077-2
Lorenzo Mezzalira
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引用次数: 0
Realization of a simple serial process data highway (PDV-bus) station 实现一个简单的串行处理数据高速公路(pdv总线)站
Euromicro Newsletter
Pub Date : 1980-11-01 DOI: 10.1016/0303-1268(80)90081-4
P Levi

An implementation of a minimal subset of the PDV-communication protocol is introduced. This subset allows connections which are protected against double transmission errors and offers data flow control on the link level.

介绍了PDV通信协议的极小子集的实现。该子集允许防止双重传输错误的连接，并在链路级别提供数据流控制。
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引用次数: 2
Introduction to the special section: Papers presented as ‘short notes’ at the EUROMICRO 80 symposium 特别部分介绍:在EUROMICRO 80研讨会上作为“简短笔记”提出的论文
Euromicro Newsletter
Pub Date : 1980-11-01 DOI: 10.1016/0303-1268(80)90077-2
L. Mezzalira
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引用次数: 0
Realization of a simple serial process data highway (PDV-bus) station 实现一个简单的串行处理数据高速公路(pdv总线)站
Euromicro Newsletter
Pub Date : 1980-11-01 DOI: 10.1016/0303-1268(80)90081-4
P. Levi
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引用次数: 2
GD80—A multi-microprocessor architecture for computer graphics 用于计算机图形学的多微处理器体系结构
Euromicro Newsletter
Pub Date : 1980-11-01 DOI: 10.1016/0303-1268(80)90089-9
P. Verebély
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引用次数: 0
Function-microcomputers for computer graphics 计算机制图用微型计算机功能
Euromicro Newsletter
Pub Date : 1980-11-01 DOI: 10.1016/0303-1268(80)90090-5
G Szanto, J van den Bos

A wide range of microprocessor, memory and interface circuits with ever improving specifications and decreasing prices permits us to build efficient and inexpensive microcomputers. These devices are therefore particularly suited as special-purpose modules in many areas of data processing. This report offers a design for a net of closely coupled special-purpose microcomputers in computer graphics. This system performs utility functions for device-independent and terminal dependent graphics. It also serves to emulate certain higher-level functions for output and input handling. Because speed requirements differ greatly, both MOS and bit-slice microprocessors can be applied. Applying dynamically microprogrammable processors will permit run-time changes in the function repertoire. This facility is used for emulation and high-level graphics instructions at the microcode level.

微处理器、存储器和接口电路种类繁多，规格不断提高，价格不断下降，这使我们能够制造出高效、廉价的微型计算机。因此，这些设备特别适合作为数据处理的许多领域中的专用模块。本报告提供了计算机图形学中紧密耦合的专用微型计算机网络的设计。该系统执行与设备无关和与终端相关的图形的实用功能。它还用于模拟某些更高级别的输出和输入处理功能。由于速度要求差别很大，MOS和位片微处理器都可以应用。应用动态可微程序处理器将允许在运行时更改功能库。此功能用于微码级别的模拟和高级图形指令。
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引用次数: 0
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