Pub Date : 2025-02-03DOI: 10.1109/TMAT.2025.3535909
{"title":"Call for Nominations for Editor-in-Chief: IEEE Transactions on Semiconductor Manufacturing","authors":"","doi":"10.1109/TMAT.2025.3535909","DOIUrl":"https://doi.org/10.1109/TMAT.2025.3535909","url":null,"abstract":"","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"2 ","pages":"C3-C3"},"PeriodicalIF":0.0,"publicationDate":"2025-02-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10869512","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"143105656","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-17DOI: 10.1109/TMAT.2025.3529277
{"title":"Wide Band Gap Semiconductors for Automotive Applications Call for Papers","authors":"","doi":"10.1109/TMAT.2025.3529277","DOIUrl":"https://doi.org/10.1109/TMAT.2025.3529277","url":null,"abstract":"","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"2 ","pages":"C3-C3"},"PeriodicalIF":0.0,"publicationDate":"2025-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10844544","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142993022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-17DOI: 10.1109/TMAT.2025.3529352
{"title":"Call for Papers: Special Issue on Exploration of the Exciting World of Multifunctional Oxide-Based Electronic Devices: From Material to System-Level Applications","authors":"","doi":"10.1109/TMAT.2025.3529352","DOIUrl":"https://doi.org/10.1109/TMAT.2025.3529352","url":null,"abstract":"","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"2 ","pages":"C3-C3"},"PeriodicalIF":0.0,"publicationDate":"2025-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10844545","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142993021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-17DOI: 10.1109/TMAT.2025.3529353
{"title":"Announcing an IEEE/Optica Publishing Group Journal of Lightwave Technology Special Issue on:","authors":"","doi":"10.1109/TMAT.2025.3529353","DOIUrl":"https://doi.org/10.1109/TMAT.2025.3529353","url":null,"abstract":"","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"2 ","pages":"C3-C3"},"PeriodicalIF":0.0,"publicationDate":"2025-01-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10844543","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142993023","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-01-14DOI: 10.1109/TMAT.2025.3529194
{"title":"2024 Index IEEE Transactions on Materials for Electron Devices Vol. 1","authors":"","doi":"10.1109/TMAT.2025.3529194","DOIUrl":"https://doi.org/10.1109/TMAT.2025.3529194","url":null,"abstract":"","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"1 ","pages":"222-229"},"PeriodicalIF":0.0,"publicationDate":"2025-01-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10841915","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142976040","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The choice and engineering of the gate-dielectric (GD) is of paramount importance to the performance and energy-efficiency of two-dimensional (2D) field-effect-transistors (FETs) that are considered to be primary candidates for sub-10 nm gate length (L g ) metal-oxide-semiconductor FETs (MOSFETs). Despite remarkable progress achieved in recent years by the semiconductor-industry towards realization of high-performance 2D FETs based on transition-metal dichalcogenides (TMDs), achieving fast switching speeds and low device leakage currents remain an open challenge. More specifically, the effect of traps at the dielectric-2D interface and bulk defects in the dielectric on device performance have not been thoroughly investigated. In this paper, taking a common 2D-TMD material molybdenum disulfide (MoS 2 ) as an example, we explore various GDs and dielectric-stacks – their interfaces, traps and defects, by using rigorous ab-initio density-functional-theory (DFT) and non-equilibrium-Green's-function (NEGF) transport. Our framework and analysis provide valuable insights into the design of n-type 2D MoS 2 FETs, including their gate leakage (I GL ), subthreshold swing (SS), and ON-current (I ON ), and they can be extended to optimize the design and performance of other 2D FETs. More specifically, we demonstrate that monolayer (1L-) and bilayer (2L-) LaOCl/HfO 2 are promising GD stacks to achieve IRDS required values for I GL , SS, and I ON in n-type 2D FETs. Finally, we develop a framework to derive the design-window in terms of material/interface properties valid for both n-type and p-type 2D FETs and identify potential GD materials as a passivation/seeding layer across different L g for n-type 2D FETs. The results highlight LaOCl as a promising candidate for L g = 7 nm while several materials, including LaOCl and h BN, are viable for L g = 10 nm.
{"title":"A Framework for Exploring Gate-Dielectric Materials for High-Performance Two-Dimensional Field-Effect-Transistors","authors":"Ankit Kumar;Lin Xu;Albert Ho;Arnab Pal;Kunjesh Agashiwala;Kamyar Parto;Wei Cao;Kaustav Banerjee","doi":"10.1109/TMAT.2024.3513236","DOIUrl":"https://doi.org/10.1109/TMAT.2024.3513236","url":null,"abstract":"The choice and engineering of the gate-dielectric (GD) is of paramount importance to the performance and energy-efficiency of two-dimensional (2D) field-effect-transistors (FETs) that are considered to be primary candidates for sub-10 nm gate length (L\u0000<sub>g</sub>\u0000) metal-oxide-semiconductor FETs (MOSFETs). Despite remarkable progress achieved in recent years by the semiconductor-industry towards realization of high-performance 2D FETs based on transition-metal dichalcogenides (TMDs), achieving fast switching speeds and low device leakage currents remain an open challenge. More specifically, the effect of traps at the dielectric-2D interface and bulk defects in the dielectric on device performance have not been thoroughly investigated. In this paper, taking a common 2D-TMD material molybdenum disulfide (MoS\u0000<sub>2</sub>\u0000) as an example, we explore various GDs and dielectric-stacks – their interfaces, traps and defects, by using rigorous ab-initio density-functional-theory (DFT) and non-equilibrium-Green's-function (NEGF) transport. Our framework and analysis provide valuable insights into the design of n-type 2D MoS\u0000<sub>2</sub>\u0000 FETs, including their gate leakage (I\u0000<sub>GL</sub>\u0000), subthreshold swing (SS), and ON-current (I\u0000<sub>ON</sub>\u0000), and they can be extended to optimize the design and performance of other 2D FETs. More specifically, we demonstrate that monolayer (1L-) and bilayer (2L-) LaOCl/HfO\u0000<sub>2</sub>\u0000 are promising GD stacks to achieve IRDS required values for I\u0000<sub>GL</sub>\u0000, SS, and I\u0000<sub>ON</sub>\u0000 in n-type 2D FETs. Finally, we develop a framework to derive the design-window in terms of material/interface properties valid for both n-type and p-type 2D FETs and identify potential GD materials as a passivation/seeding layer across different L\u0000<sub>g</sub>\u0000 for n-type 2D FETs. The results highlight LaOCl as a promising candidate for L\u0000<sub>g</sub>\u0000 = 7 nm while several materials, including LaOCl and \u0000<italic>h</i>\u0000BN, are viable for L\u0000<sub>g</sub>\u0000 = 10 nm.","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"1 ","pages":"211-220"},"PeriodicalIF":0.0,"publicationDate":"2024-12-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142912585","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-03DOI: 10.1109/TMAT.2024.3469608
{"title":"IEEE Electron Devices Society Information","authors":"","doi":"10.1109/TMAT.2024.3469608","DOIUrl":"https://doi.org/10.1109/TMAT.2024.3469608","url":null,"abstract":"","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"1 ","pages":"C2-C2"},"PeriodicalIF":0.0,"publicationDate":"2024-12-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10772478","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142761429","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-25DOI: 10.1109/TMAT.2024.3486974
FRANCESCA IACOPI
{"title":"Editorial An Era of Surfaces","authors":"FRANCESCA IACOPI","doi":"10.1109/TMAT.2024.3486974","DOIUrl":"https://doi.org/10.1109/TMAT.2024.3486974","url":null,"abstract":"","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"1 ","pages":"iii-iv"},"PeriodicalIF":0.0,"publicationDate":"2024-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10766942","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142713868","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-18DOI: 10.1109/TMAT.2024.3501212
Akrajas Ali Umar;P. Susthita Menon
This paper discusses a specific case regarding how the behavior of the perovskite lattice and the crystallinity properties of the electron transport layer (ETL) impact the photoelectrical dynamics in perovskite solar cells (PSCs). While many factors influence this photovoltaic process, including the properties of the perovskite layer, ETL, hole transport layer (HTL), and the interfacial properties between these components, the fundamental phenomena occurring within each layer are quite similar. By examining the properties of the perovskite layer and ETL, we can gain valuable insights into how they collectively influence the transport of photogenerated carriers in PSCs. This brief review aims to shed light on these key aspects, thus catalyzing efforts to enhance the performance of perovskite solar cells. Understanding the underlying dynamics at play will enable researchers to devise more targeted strategies to optimize PSCs, ultimately realizing their full potential in renewable energy applications.
{"title":"Optoelectrical Dynamic of Perovskite Solar Cells Under Perovskite and Electron Transport Layer Crystallinity Effect","authors":"Akrajas Ali Umar;P. Susthita Menon","doi":"10.1109/TMAT.2024.3501212","DOIUrl":"https://doi.org/10.1109/TMAT.2024.3501212","url":null,"abstract":"This paper discusses a specific case regarding how the behavior of the perovskite lattice and the crystallinity properties of the electron transport layer (ETL) impact the photoelectrical dynamics in perovskite solar cells (PSCs). While many factors influence this photovoltaic process, including the properties of the perovskite layer, ETL, hole transport layer (HTL), and the interfacial properties between these components, the fundamental phenomena occurring within each layer are quite similar. By examining the properties of the perovskite layer and ETL, we can gain valuable insights into how they collectively influence the transport of photogenerated carriers in PSCs. This brief review aims to shed light on these key aspects, thus catalyzing efforts to enhance the performance of perovskite solar cells. Understanding the underlying dynamics at play will enable researchers to devise more targeted strategies to optimize PSCs, ultimately realizing their full potential in renewable energy applications.","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"1 ","pages":"194-210"},"PeriodicalIF":0.0,"publicationDate":"2024-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142810265","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-13DOI: 10.1109/TMAT.2024.3497835
Luigi Colombo;Salim El Kazzi;Mihaela Popovici;Gilles Delie;Dae Seon Kwon;Sean RC McMitchell;Christoph Adelmann
The integration of novel materials has been pivotal in advancing Si-based devices ever since Si became the preferred material for transistors, and later, integrated circuits. New materials have rapidly been adopted in recent decades to enhance the performance of Si integrated circuits. The imperative to uphold Moore's Law for both More Moore and More than Moore devices has driven the industry to study, and later introduce a plethora of materials and innovative processes into the Si fabrication process, spanning from the front-end-of-line (FEOL) to the back-end-of-line (BEOL). This concerted effort aims to bolster computing power and functionality while curbing costs. Scaling Si-channel transistors down to the nanometer level has presented formidable challenges. The emergence of new materials, such as two-dimensional materials like transition metal dichalcogenides, carbon nanotubes, and metal oxides holds promise for further scaling endeavors. With transistors and interconnects nearing their physical limits, these materials offer potential solutions by enabling the fabrication of high-performance devices without relying solely on Si, while integrated at lower thermal budgets. Moreover, these technologies can be repurposed in the BEOL to add extra functionality while reducing the overall device footprint. Recent breakthroughs, notably the successful demonstration of high-performance devices utilizing ALD metal oxides like In 2 O 3 , have sparked considerable excitement. Addressing the scaling challenges of interconnects is equally daunting. The quest for materials with lower resistivities than copper interconnects with reduced electromigration at scaled dimensions and efforts to eliminate or minimize barrier layers hold promise in mitigating RC time delay. Non-volatile memories, particularly ferroelectric-based memories, stand to be gained from advancements in materials science. Innovations in such materials as hafnates and enhanced integration techniques for perovskites through electrode stack engineering could facilitate the scaling of current ferroelectric memories. The ongoing introduction of new materials is poised to sustain scaling efforts and unlock novel functionalities in electronic devices for many years.
自从硅成为晶体管和后来的集成电路的首选材料以来，新材料的集成一直是推进硅基器件的关键。近几十年来，新材料被迅速采用，以提高硅集成电路的性能。对于More Moore和More than Moore器件来说，维护摩尔定律的必要性推动了该行业的研究，并随后在Si制造过程中引入了大量的材料和创新工艺，从前端线（FEOL）到后端线（BEOL）。这种协同的努力旨在增强计算能力和功能，同时控制成本。将硅沟道晶体管缩小到纳米级是一个艰巨的挑战。新材料的出现，如过渡金属二硫族化合物、碳纳米管和金属氧化物等二维材料，为进一步扩大规模带来了希望。随着晶体管和互连接近其物理极限，这些材料提供了潜在的解决方案，使制造高性能器件无需完全依赖于Si，同时集成在更低的热预算。此外，这些技术可以在BEOL中重新利用，以增加额外的功能，同时减少整体设备占用空间。最近的突破，特别是利用ALD金属氧化物（如In2O3）的高性能器件的成功演示，引发了相当大的兴奋。解决互连的规模挑战同样令人生畏。寻求比铜互连具有更低电阻率的材料，在缩放尺寸上减少电迁移，并努力消除或最小化屏障层，有望减轻RC时间延迟。非易失性存储器，特别是基于铁电的存储器，将从材料科学的进步中获得。诸如铪酸盐等材料的创新和通过电极堆叠工程增强的钙钛矿集成技术可以促进当前铁电存储器的缩放。正在进行的新材料的引入准备维持规模的努力，并解锁多年的电子设备的新功能。
{"title":"Future Materials for Beyond Si Integrated Circuits: A Perspective","authors":"Luigi Colombo;Salim El Kazzi;Mihaela Popovici;Gilles Delie;Dae Seon Kwon;Sean RC McMitchell;Christoph Adelmann","doi":"10.1109/TMAT.2024.3497835","DOIUrl":"https://doi.org/10.1109/TMAT.2024.3497835","url":null,"abstract":"The integration of novel materials has been pivotal in advancing Si-based devices ever since Si became the preferred material for transistors, and later, integrated circuits. New materials have rapidly been adopted in recent decades to enhance the performance of Si integrated circuits. The imperative to uphold Moore's Law for both More Moore and More than Moore devices has driven the industry to study, and later introduce a plethora of materials and innovative processes into the Si fabrication process, spanning from the front-end-of-line (FEOL) to the back-end-of-line (BEOL). This concerted effort aims to bolster computing power and functionality while curbing costs. Scaling Si-channel transistors down to the nanometer level has presented formidable challenges. The emergence of new materials, such as two-dimensional materials like transition metal dichalcogenides, carbon nanotubes, and metal oxides holds promise for further scaling endeavors. With transistors and interconnects nearing their physical limits, these materials offer potential solutions by enabling the fabrication of high-performance devices without relying solely on Si, while integrated at lower thermal budgets. Moreover, these technologies can be repurposed in the BEOL to add extra functionality while reducing the overall device footprint. Recent breakthroughs, notably the successful demonstration of high-performance devices utilizing ALD metal oxides like In\u0000<sub>2</sub>\u0000O\u0000<sub>3</sub>\u0000, have sparked considerable excitement. Addressing the scaling challenges of interconnects is equally daunting. The quest for materials with lower resistivities than copper interconnects with reduced electromigration at scaled dimensions and efforts to eliminate or minimize barrier layers hold promise in mitigating RC time delay. Non-volatile memories, particularly ferroelectric-based memories, stand to be gained from advancements in materials science. Innovations in such materials as hafnates and enhanced integration techniques for perovskites through electrode stack engineering could facilitate the scaling of current ferroelectric memories. The ongoing introduction of new materials is poised to sustain scaling efforts and unlock novel functionalities in electronic devices for many years.","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"1 ","pages":"178-193"},"PeriodicalIF":0.0,"publicationDate":"2024-11-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142810264","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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