Pub Date : 2026-01-20DOI: 10.1109/TMAT.2026.3654827
{"title":"2025 Index IEEE Transactions on Materials for Electron Devices","authors":"","doi":"10.1109/TMAT.2026.3654827","DOIUrl":"https://doi.org/10.1109/TMAT.2026.3654827","url":null,"abstract":"","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"2 ","pages":"166-173"},"PeriodicalIF":0.0,"publicationDate":"2026-01-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=11359568","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"146026394","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Black phosphorus (BP), with its tunable thickness-dependent bandgap (0.3–2.0 eV) and high carrier mobility (up to 10,000 cm2 V−1 s−1), has emerged as a transformative two-dimensional (2D) material for next-generation electronics and optoelectronics. This study investigates BP’s rediscovery, unique properties, synthesis advancements, and integration into cutting-edge applications. Recent advances in synthesis methods, including liquid-phase exfoliation, chemical vapor transport, and bismuth-flux techniques, have enabled the scalable production of high-quality BP with precisely controlled structural features. Its anisotropic electrical and optical properties have opened the door to the realization of a high-performance device, for example, field-effect transistors (FETs) with outstanding ON/OFF ratios and mobility, flexible super capacitors with enhanced energy densities, and complex diodes engineered for optoelectronic applications. Despite its transformative potential, challenges related to scalability, oxidation stability, and manufacturing consistency remain critical areas of research, with ongoing efforts focused on encapsulation techniques, hybrid material systems, and advanced doping methods to enhance BP’s performance and feasibility in real-world applications. The novelty of this review article stems from its integrated and application-focused approach, which sets it apart from existing literature that typically treats application of phosphorene separately. Whereas most reviews available in the literature concentrate on general material properties of black phosphorus or examine its role within a single device category; this work unifies the progress, discussion, challenges and future road map of BP in FETs, flexible super capacitors, and diodes within a single comprehensive framework.
{"title":"Progress of Black Phosphorus in Field Effect Transistors, Flexible Super Capacitors and Diodes: Open Issues and Future Directions","authors":"Girish Chandra Ghivela;Shreeved Tadas;Shatakshi Ranjan;Pranav Chaure","doi":"10.1109/TMAT.2025.3640977","DOIUrl":"https://doi.org/10.1109/TMAT.2025.3640977","url":null,"abstract":"Black phosphorus (BP), with its tunable thickness-dependent bandgap (0.3–2.0 eV) and high carrier mobility (up to 10,000 cm<sup>2</sup> V<sup>−1</sup> s<sup>−1</sup>), has emerged as a transformative two-dimensional (2D) material for next-generation electronics and optoelectronics. This study investigates BP’s rediscovery, unique properties, synthesis advancements, and integration into cutting-edge applications. Recent advances in synthesis methods, including liquid-phase exfoliation, chemical vapor transport, and bismuth-flux techniques, have enabled the scalable production of high-quality BP with precisely controlled structural features. Its anisotropic electrical and optical properties have opened the door to the realization of a high-performance device, for example, field-effect transistors (FETs) with outstanding ON/OFF ratios and mobility, flexible super capacitors with enhanced energy densities, and complex diodes engineered for optoelectronic applications. Despite its transformative potential, challenges related to scalability, oxidation stability, and manufacturing consistency remain critical areas of research, with ongoing efforts focused on encapsulation techniques, hybrid material systems, and advanced doping methods to enhance BP’s performance and feasibility in real-world applications. The novelty of this review article stems from its integrated and application-focused approach, which sets it apart from existing literature that typically treats application of phosphorene separately. Whereas most reviews available in the literature concentrate on general material properties of black phosphorus or examine its role within a single device category; this work unifies the progress, discussion, challenges and future road map of BP in FETs, flexible super capacitors, and diodes within a single comprehensive framework.","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"3 ","pages":"23-38"},"PeriodicalIF":0.0,"publicationDate":"2025-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145830846","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Carbon nanotubes (CNTs) have been extensively investigated as channel materials for flexible electronics, owing to their inherent flexibility, high carrier mobility, ultrathin body, and solution-based, low-temperature processibility. However, achieving robust operation of CNT thin-film transistors (TFTs) under repeated bias cycling in air, a crucial requirement for complex and large-scale circuits, remains a challenge. In this work, we present a low-temperature hexamethyldisilazane (HMDS) post-treatment (150 °c) to enhance the robustness of flexible, bottom-gated CNT TFTs. This treatment significantly reduces device hysteresis and improves threshold voltage (Vth) stability under repeated bias cycling, decreasing the relative standard deviation (Sr) of Vth from 136% to 34.1% and from 77.3% to 4.23% under different measurement modes. The mechanisms underlying this Vth stability enhancement are primarily attributed to a significant reduction in device surface traps: (1) prolonged 150 °C post-treatment in a vacuum oven promotes the desorption of oxygen and water molecules from the active layer and dielectric surface; (2) HMDS reacts with polar hydroxyl groups on the device surface, generating hydrophobic, non-polar methyl groups, thereby reducing surface charge accumulation; and (3) the hydrophobic nature of the HMDS layer on the device surface contributes to insulating the device from ambient oxygen and water molecules.
{"title":"Enhanced Operational Stability of Flexible Carbon Nanotube Thin Film Transistors Using Low-Temperature Post-Treatment","authors":"Haitao Zhang;Xiongfeng Zou;Jian Hu;Hui Wang;Li Xiang","doi":"10.1109/TMAT.2025.3638976","DOIUrl":"https://doi.org/10.1109/TMAT.2025.3638976","url":null,"abstract":"Carbon nanotubes (CNTs) have been extensively investigated as channel materials for flexible electronics, owing to their inherent flexibility, high carrier mobility, ultrathin body, and solution-based, low-temperature processibility. However, achieving robust operation of CNT thin-film transistors (TFTs) under repeated bias cycling in air, a crucial requirement for complex and large-scale circuits, remains a challenge. In this work, we present a low-temperature hexamethyldisilazane (HMDS) post-treatment (150 °c) to enhance the robustness of flexible, bottom-gated CNT TFTs. This treatment significantly reduces device hysteresis and improves threshold voltage (V<sub>th</sub>) stability under repeated bias cycling, decreasing the relative standard deviation (S<sub>r</sub>) of V<sub>th</sub> from 136% to 34.1% and from 77.3% to 4.23% under different measurement modes. The mechanisms underlying this V<sub>th</sub> stability enhancement are primarily attributed to a significant reduction in device surface traps: (1) prolonged 150 °C post-treatment in a vacuum oven promotes the desorption of oxygen and water molecules from the active layer and dielectric surface; (2) HMDS reacts with polar hydroxyl groups on the device surface, generating hydrophobic, non-polar methyl groups, thereby reducing surface charge accumulation; and (3) the hydrophobic nature of the HMDS layer on the device surface contributes to insulating the device from ambient oxygen and water molecules.","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"2 ","pages":"151-155"},"PeriodicalIF":0.0,"publicationDate":"2025-12-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145778329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
This work presents the filamentary resistive switching (RS) of transition metal oxide thin film planner memristors, specifically focusing on α-MoO3, a distinguished n-type wide bandgap semiconductor. The study uncovers the metal electrode-dependent negative differential resistance (NDR) effect and memristive behavior of α-MoO3 thin films for next-generation non-volatile memory and neuromorphic computing applications. The silver (Ag) electrode exhibits superior bipolar RS than the titanium (Ti) electrode because of Ag ion diffusions, the nature of the Ag/MoO3 junction, and interfacial effects. Likewise, significant NDR is observed for the Ag electrode compared to the Ti, owing to thermally activated transport, residual ionic motion, and redox processes at the Ag electrode. Transient measurements reveal stronger spike-like current responses for the Ag electrode, emphasizing its potential for neuromorphic devices. Besides, the optical absorption and photoluminescence analysis show that oxygen vacancies create Mo+5 defect states and split the Mo d-level owing to the crystal field effect, which affects the electronic structure and visible light emission of α-MoO3 thin film. These findings demonstrate the essential role of metal electrodes and defect engineering in controlling filamentary RS and NDR effect, advancing α-MoO3 thin films for future neuromorphic computing and optoelectronic devices.
{"title":"Coexistence of Electrode-Dependent Resistive Switching and Negative Differential Resistance Effect in α-MoO3-x Memristor","authors":"Ravindra Kumar Nitharwal;Ravindra Kumar;Subhajit Chatterjee;Arige Sumanth;Renu Yadav;Abhishek Misra;M. S. Ramachandra Rao;Tejendra Dixit;Sivarama Krishnan","doi":"10.1109/TMAT.2025.3637805","DOIUrl":"https://doi.org/10.1109/TMAT.2025.3637805","url":null,"abstract":"This work presents the filamentary resistive switching (RS) of transition metal oxide thin film planner memristors, specifically focusing on <italic>α</i>-MoO<sub>3</sub>, a distinguished <italic>n</i>-type wide bandgap semiconductor. The study uncovers the metal electrode-dependent negative differential resistance (NDR) effect and memristive behavior of <italic>α</i>-MoO<sub>3</sub> thin films for next-generation non-volatile memory and neuromorphic computing applications. The silver (Ag) electrode exhibits superior bipolar RS than the titanium (Ti) electrode because of Ag ion diffusions, the nature of the Ag/MoO<sub>3</sub> junction, and interfacial effects. Likewise, significant NDR is observed for the Ag electrode compared to the Ti, owing to thermally activated transport, residual ionic motion, and redox processes at the Ag electrode. Transient measurements reveal stronger spike-like current responses for the Ag electrode, emphasizing its potential for neuromorphic devices. Besides, the optical absorption and photoluminescence analysis show that oxygen vacancies create Mo<sup>+5</sup> defect states and split the Mo d-level owing to the crystal field effect, which affects the electronic structure and visible light emission of <italic>α</i>-MoO<sub>3</sub> thin film. These findings demonstrate the essential role of metal electrodes and defect engineering in controlling filamentary RS and NDR effect, advancing <italic>α</i>-MoO<sub>3</sub> thin films for future neuromorphic computing and optoelectronic devices.","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"3 ","pages":"15-22"},"PeriodicalIF":0.0,"publicationDate":"2025-11-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145778282","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Al-doped HfO2 (HAO) has demonstrated improved ferroelectric stability; however, its relatively low remnant polarization (2Pr) at reduced annealing temperatures significantly limits practical application. This limitation primarily stems from a low ferroelectric phase fraction and insufficient crystallinity. To address this challenge, we systematically investigated the interplay among processing parameters, ferroelectric phase content, and film crystallinity. Guided by these insights, we optimized HAO films processed at low annealing temperatures by tuning key parameters, including Al doping concentration, oxidant, film thickness, and electrode material. Within an annealing temperature range of 500 °C to 700 °C, the optimized capacitors exhibited markedly enhanced 2Pr values. Notably, a record-high 2Pr of 37.5 μC/cm2 was achieved at 500 °C, representing an 80.3% increase over the previously reported benchmark of 20.8 μC/cm2. These findings underscore the pivotal role of processing-driven control over phase composition and crystallinity in enhancing the ferroelectric performance of HAO films, offering a promising pathway for their integration into next-generation electronic devices.
{"title":"Toward High 2Pr in Al:HfO2 Capacitors at Low Thermal Budgets: The Interplay of Crystallinity, Phase, and Ferroelectricity","authors":"Zhuohua Tang;Xujin Song;Wanwang Yang;Shangze Li;Dijiang Sun;Ruiqi Chen;Yulin Feng;Jinfeng Kang;Peng Huang","doi":"10.1109/TMAT.2025.3637185","DOIUrl":"https://doi.org/10.1109/TMAT.2025.3637185","url":null,"abstract":"Al-doped HfO<sub>2</sub> (HAO) has demonstrated improved ferroelectric stability; however, its relatively low remnant polarization (2P<sub>r</sub>) at reduced annealing temperatures significantly limits practical application. This limitation primarily stems from a low ferroelectric phase fraction and insufficient crystallinity. To address this challenge, we systematically investigated the interplay among processing parameters, ferroelectric phase content, and film crystallinity. Guided by these insights, we optimized HAO films processed at low annealing temperatures by tuning key parameters, including Al doping concentration, oxidant, film thickness, and electrode material. Within an annealing temperature range of 500 °C to 700 °C, the optimized capacitors exhibited markedly enhanced 2P<sub>r</sub> values. Notably, a record-high 2P<sub>r</sub> of 37.5 μC/cm<sup>2</sup> was achieved at 500 °C, representing an 80.3% increase over the previously reported benchmark of 20.8 μC/cm<sup>2</sup>. These findings underscore the pivotal role of processing-driven control over phase composition and crystallinity in enhancing the ferroelectric performance of HAO films, offering a promising pathway for their integration into next-generation electronic devices.","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"3 ","pages":"8-14"},"PeriodicalIF":0.0,"publicationDate":"2025-11-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145778158","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-11-20DOI: 10.1109/TMAT.2025.3635149
Dong Jun Kim;Sun Woo Lee;Hojin Lee;Taek-Soo Kim
As vias become narrower and deeper, to improve semiconductor performance, the demand for tungsten (W) with excellent step coverage is increasing. However, residual stress remains an important issue in the W thin film deposition process. This study investigated the residual stress of chemical vapor deposition (CVD) W thin films using two different reducing gases: diborane (B2H6) and silane (SiH4). Residual stress was quantitatively evaluated using the Stoney equation based-on wafer curvature measurements. As a result, the SiH4-W thin film exhibited higher residual stress than the B2H6-W film as the thin film thickness increased. It was found that the difference in residual stress depending on the reducing gas was mainly attributed to microstructural effects rather than impurity incorporation. In both cases, the intrinsic stress was dominant in the residual stress. The SiH4-W thin film exhibited smaller grains compared to B2H6-W, resulting in higher tensile stress. In addition, fracture surface analysis using fracture mechanics tests revealed that the fracture surface crack patterns varied with the level of residual stress. The results of this study are expected to provide insights into optimizing W thin-film deposition and improving mechanical reliability for advanced semiconductor applications.
{"title":"Effect of Nucleation-Stage Reducing Agents on Residual Stress in CVD Tungsten Thin Films","authors":"Dong Jun Kim;Sun Woo Lee;Hojin Lee;Taek-Soo Kim","doi":"10.1109/TMAT.2025.3635149","DOIUrl":"https://doi.org/10.1109/TMAT.2025.3635149","url":null,"abstract":"As vias become narrower and deeper, to improve semiconductor performance, the demand for tungsten (W) with excellent step coverage is increasing. However, residual stress remains an important issue in the W thin film deposition process. This study investigated the residual stress of chemical vapor deposition (CVD) W thin films using two different reducing gases: diborane (B<sub>2</sub>H<sub>6</sub>) and silane (SiH<sub>4</sub>). Residual stress was quantitatively evaluated using the Stoney equation based-on wafer curvature measurements. As a result, the SiH<sub>4</sub>-W thin film exhibited higher residual stress than the B<sub>2</sub>H<sub>6</sub>-W film as the thin film thickness increased. It was found that the difference in residual stress depending on the reducing gas was mainly attributed to microstructural effects rather than impurity incorporation. In both cases, the intrinsic stress was dominant in the residual stress. The SiH<sub>4</sub>-W thin film exhibited smaller grains compared to B<sub>2</sub>H<sub>6</sub>-W, resulting in higher tensile stress. In addition, fracture surface analysis using fracture mechanics tests revealed that the fracture surface crack patterns varied with the level of residual stress. The results of this study are expected to provide insights into optimizing W thin-film deposition and improving mechanical reliability for advanced semiconductor applications.","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"3 ","pages":"1-7"},"PeriodicalIF":0.0,"publicationDate":"2025-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145778462","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-09-04DOI: 10.1109/TMAT.2025.3606438
Ziyi He;Dinusha Herath Mudiyanselage;Dawei Wang;Bingcheng Da;Junzhe Xie;Michel Khoury;Yuji Zhao;Houqiang Fu
In this paper, we developed a simple gate recess etching technique for the fabrication of GaN E-mode HEMT. A systematic comparison between the high-power etching and high-low-power etching gate recessed E-mode GaN HEMT has been carried out. The device with high-low power etching showed increased on-current, reduced gate leakage current and threshold voltage dispersion, and reduced hysteresis. The device with high-low power etching showed an improved interface between dielectric and recessed gate with an interface trap density of 1.2 × 1012 cm−2⋅eV−1 to 2.2 × 1012 cm−2⋅eV−1, which is about half of the value in the high power etching device. Gate step-stress testing and positive gate-bias stress testing showed an improved gate robustness, and reduced threshold voltage shift resulting from reduced SiNx/GaN interface traps for high-low-power etching MISHEMT. Time-dependent dielectric breakdown (TDDB) testing showed its increased gate voltage of 5 V for maintaining a 10-year lifetime compared to 4.5 V for the high-power etching device. This work demonstrated and analyzed an easy-to-implement approach for realizing high-performance low interface trap E-mode GaN MISHEMT.
{"title":"Electrical and Reliability Study of GaN E-Mode MISHEMTs With Two-Step Etching Gate Recess","authors":"Ziyi He;Dinusha Herath Mudiyanselage;Dawei Wang;Bingcheng Da;Junzhe Xie;Michel Khoury;Yuji Zhao;Houqiang Fu","doi":"10.1109/TMAT.2025.3606438","DOIUrl":"https://doi.org/10.1109/TMAT.2025.3606438","url":null,"abstract":"In this paper, we developed a simple gate recess etching technique for the fabrication of GaN E-mode HEMT. A systematic comparison between the high-power etching and high-low-power etching gate recessed E-mode GaN HEMT has been carried out. The device with high-low power etching showed increased on-current, reduced gate leakage current and threshold voltage dispersion, and reduced hysteresis. The device with high-low power etching showed an improved interface between dielectric and recessed gate with an interface trap density of 1.2 × 10<sup>12</sup> cm<sup>−2</sup>⋅eV<sup>−1</sup> to 2.2 × 10<sup>12</sup> cm<sup>−2</sup>⋅eV<sup>−1</sup>, which is about half of the value in the high power etching device. Gate step-stress testing and positive gate-bias stress testing showed an improved gate robustness, and reduced threshold voltage shift resulting from reduced SiN<sub>x</sub>/GaN interface traps for high-low-power etching MISHEMT. Time-dependent dielectric breakdown (TDDB) testing showed its increased gate voltage of 5 V for maintaining a 10-year lifetime compared to 4.5 V for the high-power etching device. This work demonstrated and analyzed an easy-to-implement approach for realizing high-performance low interface trap E-mode GaN MISHEMT.","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"2 ","pages":"108-112"},"PeriodicalIF":0.0,"publicationDate":"2025-09-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"145141609","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2025-08-20DOI: 10.1109/TMAT.2025.3601062
Bingcheng Da;Dinusha Herath Mudiyanselage;Dawei Wang;Ziyi He;Junzhe Xie;Houqiang Fu
This work reports the demonstration of AlN trench metal-oxide-semiconductor transistors (MOSFETs) on single-crystal AlN substrates, where the impacts of gate trench depth were investigated. It was found that the device with a deeper gate trench showed enhanced output characteristics with increased on/off ratio of >600 by ∼20 times, improved maximum transconductance of 3.1 μS/mm by ∼2 times, and higher maximum drain current of 47 μA/mm by ∼1.5 times, compared with the device with a shallow gate trench. Compared with the reported AlN MOSFETs on sapphire substrates, the AlN-on-AlN device exhibited ∼10 times higher drain current, ∼15 times larger transconductance, and ∼2 times larger average breakdown electric field of >1MV/cm. These results will benefit the future development of high-performance AlN power electronics.
{"title":"Ultrawide Bandgap AlN Trench Metal-Oxide-Semiconductor Transistors (MOSFETs) on Single-Crystal AlN Substrates","authors":"Bingcheng Da;Dinusha Herath Mudiyanselage;Dawei Wang;Ziyi He;Junzhe Xie;Houqiang Fu","doi":"10.1109/TMAT.2025.3601062","DOIUrl":"https://doi.org/10.1109/TMAT.2025.3601062","url":null,"abstract":"This work reports the demonstration of AlN trench metal-oxide-semiconductor transistors (MOSFETs) on single-crystal AlN substrates, where the impacts of gate trench depth were investigated. It was found that the device with a deeper gate trench showed enhanced output characteristics with increased on/off ratio of >600 by ∼20 times, improved maximum transconductance of 3.1 μS/mm by ∼2 times, and higher maximum drain current of 47 μA/mm by ∼1.5 times, compared with the device with a shallow gate trench. Compared with the reported AlN MOSFETs on sapphire substrates, the AlN-on-AlN device exhibited ∼10 times higher drain current, ∼15 times larger transconductance, and ∼2 times larger average breakdown electric field of >1MV/cm. These results will benefit the future development of high-performance AlN power electronics.","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"2 ","pages":"103-107"},"PeriodicalIF":0.0,"publicationDate":"2025-08-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144934455","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Low temperature co-fired ceramics (LTCC) have garnered significant attention due to their exceptional electrical and thermal properties. While the traditional tape casting method for preparing LTCC substrates yields high density, it is constrained by limited geometric freedom and a complex process, making it less suitable for contemporary demands. In this study, we employ vat photopolymerization 3D printing technology to fabricate alumina/borosilicate glass composite LTCC systems and introduce a microporous structure design on the substrate. This innovation simplifies the traditional punching step, enhancing both productivity and reliability. We formulated LTCC slurry suitable for vat photopolymerization and examined the thermal conductivity and dielectric properties of the sintered parts. The findings reveal that samples held at 750 °C for 30 minutes achieved the highest densities, exhibiting a thermal conductivity of 3.63 W·m−1·K−1, a relative dielectric constant of 13.09, and the lowest dielectric loss (7.9 × 10−3). We successfully realized microporous printing on LTCC substrates, achieving microporous structures with an actual diameter of 132 μm. Additionally, we verified the compatibility of substrates with silver co-firing, observing a robust bond between the silver layer and the LTCC layer. This study underscores the potential of vat photopolymerization for LTCC applications.
{"title":"Vat Photopolymerization of Al2O3/Borosilicate Glass Low Temperature Co-Fired Ceramic Substrates With Integrated Micropore Patterning Device","authors":"Yizhen Chu;Yujuan Zhou;Mingyong Jia;Qianshun Cui;Haiyuan Shi;Zhifeng Huang;Fei Chen","doi":"10.1109/TMAT.2025.3598753","DOIUrl":"https://doi.org/10.1109/TMAT.2025.3598753","url":null,"abstract":"Low temperature co-fired ceramics (LTCC) have garnered significant attention due to their exceptional electrical and thermal properties. While the traditional tape casting method for preparing LTCC substrates yields high density, it is constrained by limited geometric freedom and a complex process, making it less suitable for contemporary demands. In this study, we employ vat photopolymerization 3D printing technology to fabricate alumina/borosilicate glass composite LTCC systems and introduce a microporous structure design on the substrate. This innovation simplifies the traditional punching step, enhancing both productivity and reliability. We formulated LTCC slurry suitable for vat photopolymerization and examined the thermal conductivity and dielectric properties of the sintered parts. The findings reveal that samples held at 750 °C for 30 minutes achieved the highest densities, exhibiting a thermal conductivity of 3.63 W·m<sup>−1</sup>·K<sup>−1</sup>, a relative dielectric constant of 13.09, and the lowest dielectric loss (7.9 × 10<sup>−3</sup>). We successfully realized microporous printing on LTCC substrates, achieving microporous structures with an actual diameter of 132 μm. Additionally, we verified the compatibility of substrates with silver co-firing, observing a robust bond between the silver layer and the LTCC layer. This study underscores the potential of vat photopolymerization for LTCC applications.","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"2 ","pages":"95-102"},"PeriodicalIF":0.0,"publicationDate":"2025-08-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144916326","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this letter, we have successfully fabricated a metal-ferroelectricity-metal (MFM) capacitor of an ultrathin 5.6 nm HZO and ultrathin In2O3 back gate devices in a back-end-of-line (BEOL) compatible process. By proposing a novel atomic layer deposition (ALD) scheme and an alternative bottom electrode treatment, the MoN-HZO sample shows an average 2Pr value of 64 μC/cm2 (with a standard deviation of 0.52) and high endurance (△2Pr/2Prpristine ≈2% from pristine to 1010 cycles). The MoN–HZO stack integrated with an ultrathin In2O3 back gate exhibits a memory window (MW) greater than 2.5 V and excellent endurance and data retention characteristics. With a maximum process temperature of 400°C, our approach meets the stringent requirements for Back-End-of-Line (BEOL) integration.
{"title":"BEOL-Compatible 5.6 nm Ultrathin HZO With Molybdenum Nitride Electrode and IN2O3 Channel Devices for Enhanced Ferroelectricity and Reliability","authors":"Li-Cheng Teng;Yu-Che Huang;Shin-Yuan Wang;Yu-Hsien Lin;Chao-Hsin Chien","doi":"10.1109/TMAT.2025.3586809","DOIUrl":"https://doi.org/10.1109/TMAT.2025.3586809","url":null,"abstract":"In this letter, we have successfully fabricated a metal-ferroelectricity-metal (MFM) capacitor of an ultrathin 5.6 nm HZO and ultrathin In<sub>2</sub>O<sub>3</sub> back gate devices in a back-end-of-line (BEOL) compatible process. By proposing a novel atomic layer deposition (ALD) scheme and an alternative bottom electrode treatment, the MoN-HZO sample shows an average 2Pr value of 64 μC/cm<sup>2</sup> (with a standard deviation of 0.52) and high endurance (△2Pr/2Pr<sub>pristine</sub> ≈2% from pristine to 10<sup>10</sup> cycles). The MoN–HZO stack integrated with an ultrathin In<sub>2</sub>O<sub>3</sub> back gate exhibits a memory window (MW) greater than 2.5 V and excellent endurance and data retention characteristics. With a maximum process temperature of 400°C, our approach meets the stringent requirements for Back-End-of-Line (BEOL) integration.","PeriodicalId":100642,"journal":{"name":"IEEE Transactions on Materials for Electron Devices","volume":"2 ","pages":"90-94"},"PeriodicalIF":0.0,"publicationDate":"2025-07-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"144704968","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：