Pub Date : 2017-03-31DOI: 10.1109/TMSCS.2017.2710194
Hongxu Yin;Niraj K. Jha
Even with an annual expenditure of more than $3 trillion, the U.S. healthcare system is far from optimal. For example, the third leading cause of death in the U.S. is preventable medical error, immediately after heart disease and cancer. Computer-based clinical decision support systems (CDSSs) have been proposed to address such deficiencies and have significantly improved clinical practice over the past decade. However, they remain limited to clinics and hospitals, and do not take advantage of patient data that are obtained on a daily basis using wearable medical sensors (WMSs) that have the ability to bridge this information gap. WMSs can collect physiological signals from anyone anywhere anytime. Thus, they have the potential to usher in an era of pervasive healthcare. However, most prior work on WMSs only focuses on hardware and protocol design, and not on an information system that can fully utilize the collected signals for efficient disease diagnosis. In this paper, for the first time, we introduce a hierarchical health decision support system for disease diagnosis that integrates health data from WMSs into CDSSs. The proposed system has a multi-tier structure, starting with a WMS tier, backed by robust machine learning, that enables diseases to be tracked individually by a disease diagnosis module. We demonstrate the feasibility of such a system through six disease diagnosis modules aimed at four ICD-10-CM disease categories. We show that the system is scalable using five more disease categories. Just the WMS tier offers impressive diagnostic accuracies for various diseases: arrhythmia (86 percent), type-2 diabetes (78 percent), urinary bladder disorder (99 percent), renal pelvis nephritis (94 percent), and hypothyroid (95 percent). We estimate that the disease diagnosis modules of all known 69,000 human diseases would require just 62 GB of storage space in the WMS tier. This is practical even in today's cloud or base station oriented WMS systems.
{"title":"A Health Decision Support System for Disease Diagnosis Based on Wearable Medical Sensors and Machine Learning Ensembles","authors":"Hongxu Yin;Niraj K. Jha","doi":"10.1109/TMSCS.2017.2710194","DOIUrl":"https://doi.org/10.1109/TMSCS.2017.2710194","url":null,"abstract":"Even with an annual expenditure of more than $3 trillion, the U.S. healthcare system is far from optimal. For example, the third leading cause of death in the U.S. is preventable medical error, immediately after heart disease and cancer. Computer-based clinical decision support systems (CDSSs) have been proposed to address such deficiencies and have significantly improved clinical practice over the past decade. However, they remain limited to clinics and hospitals, and do not take advantage of patient data that are obtained on a daily basis using wearable medical sensors (WMSs) that have the ability to bridge this information gap. WMSs can collect physiological signals from anyone anywhere anytime. Thus, they have the potential to usher in an era of pervasive healthcare. However, most prior work on WMSs only focuses on hardware and protocol design, and not on an information system that can fully utilize the collected signals for efficient disease diagnosis. In this paper, for the first time, we introduce a hierarchical health decision support system for disease diagnosis that integrates health data from WMSs into CDSSs. The proposed system has a multi-tier structure, starting with a WMS tier, backed by robust machine learning, that enables diseases to be tracked individually by a disease diagnosis module. We demonstrate the feasibility of such a system through six disease diagnosis modules aimed at four ICD-10-CM disease categories. We show that the system is scalable using five more disease categories. Just the WMS tier offers impressive diagnostic accuracies for various diseases: arrhythmia (86 percent), type-2 diabetes (78 percent), urinary bladder disorder (99 percent), renal pelvis nephritis (94 percent), and hypothyroid (95 percent). We estimate that the disease diagnosis modules of all known 69,000 human diseases would require just 62 GB of storage space in the WMS tier. This is practical even in today's cloud or base station oriented WMS systems.","PeriodicalId":100643,"journal":{"name":"IEEE Transactions on Multi-Scale Computing Systems","volume":"3 4","pages":"228-241"},"PeriodicalIF":0.0,"publicationDate":"2017-03-31","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TMSCS.2017.2710194","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68021199","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In emerging 3D NoC-based chip multiprocessors (CMPs), aging in circuits due to bias temperature instability (BTI) stress is expected to cause gate-delay degradation that, if left unchecked, can lead to untimely failure. Simultaneously, the effects of electromigration (EM) induced aging in the on-chip wires, especially those in the 3D power delivery network (PDN), are expected to notably reduce chip lifetime. A commonly proposed solution to mitigate circuit-slowdown due to aging is to hike the supply voltage; however, this increases current-densities in the PDN due to the increased power consumption on the die, which in turn expedites PDN-aging. We thus note that mechanisms to enhance lifetime reliability in 3D NoC-based CMPs must consider circuit-aging together with PDN-aging. In this paper, we propose a novel runtime framework (ARTEMIS) for intelligent dynamic application-mapping and voltage-scaling to simultaneously manage aging in circuits and the PDN, and enhance the performance and lifetime of 3D NoC-based CMPs. We also propose an aging-enabled routing algorithm that balances the degree of aging between NoC routers and cores, thereby increasing the combined lifetime of both. Our framework also considers dark-silicon power constraints that are becoming a major design challenge in scaled technologies, particularly for 3D stacked CMPs. Our experimental results indicate that ARTEMIS enables the execution of 25 percent more applications over the chip lifetime compared to state-of-the-art prior work.
{"title":"ARTEMIS: An Aging-Aware Runtime Application Mapping Framework for 3D NoC-Based Chip Multiprocessors","authors":"Venkata Yaswanth Raparti;Nishit Kapadia;Sudeep Pasricha","doi":"10.1109/TMSCS.2017.2686856","DOIUrl":"https://doi.org/10.1109/TMSCS.2017.2686856","url":null,"abstract":"In emerging 3D NoC-based chip multiprocessors (CMPs), aging in circuits due to bias temperature instability (BTI) stress is expected to cause gate-delay degradation that, if left unchecked, can lead to untimely failure. Simultaneously, the effects of electromigration (EM) induced aging in the on-chip wires, especially those in the 3D power delivery network (PDN), are expected to notably reduce chip lifetime. A commonly proposed solution to mitigate circuit-slowdown due to aging is to hike the supply voltage; however, this increases current-densities in the PDN due to the increased power consumption on the die, which in turn expedites PDN-aging. We thus note that mechanisms to enhance lifetime reliability in 3D NoC-based CMPs must consider circuit-aging together with PDN-aging. In this paper, we propose a novel runtime framework (ARTEMIS) for intelligent dynamic application-mapping and voltage-scaling to simultaneously manage aging in circuits and the PDN, and enhance the performance and lifetime of 3D NoC-based CMPs. We also propose an aging-enabled routing algorithm that balances the degree of aging between NoC routers and cores, thereby increasing the combined lifetime of both. Our framework also considers dark-silicon power constraints that are becoming a major design challenge in scaled technologies, particularly for 3D stacked CMPs. Our experimental results indicate that ARTEMIS enables the execution of 25 percent more applications over the chip lifetime compared to state-of-the-art prior work.","PeriodicalId":100643,"journal":{"name":"IEEE Transactions on Multi-Scale Computing Systems","volume":"3 2","pages":"72-85"},"PeriodicalIF":0.0,"publicationDate":"2017-03-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TMSCS.2017.2686856","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68019438","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-18DOI: 10.1109/TMSCS.2017.2705683
Byungseok Kang;Daecheon Kim;Hyunseung Choo
Gateways are emerging as a key element of bringing legacy and next generation devices to the Internet of Things (IoT). They integrate protocols for networking, help manage storage and edge analytics on the data, and facilitate data flow securely between edge devices and the cloud. Current IoT gateways solve the communication gap between field control/sensor nodes and customer cloud, enabling field data to be harnessed for manufacturing process optimization, remote management, and preventive maintenance. However, these gateways do not support fully-automatic configuration of newly added IoT devices. In this paper, we proposed a self-configurable gateway featuring real time detection and configuration of smart things over the wireless networks. This novel gateway's main features are: dynamic discovery of home IoT device(s), automatic updates of hardware changes, connection management of smart things connected over AllJoyn. We use the `option' field for automatic configuration of IoT devices rather than modify standard format of CoAP protocol. Proposed gateway functionality has been validated over the large-scale IoT testbed.
{"title":"Internet of Everything: A Large-Scale Autonomic IoT Gateway","authors":"Byungseok Kang;Daecheon Kim;Hyunseung Choo","doi":"10.1109/TMSCS.2017.2705683","DOIUrl":"https://doi.org/10.1109/TMSCS.2017.2705683","url":null,"abstract":"Gateways are emerging as a key element of bringing legacy and next generation devices to the Internet of Things (IoT). They integrate protocols for networking, help manage storage and edge analytics on the data, and facilitate data flow securely between edge devices and the cloud. Current IoT gateways solve the communication gap between field control/sensor nodes and customer cloud, enabling field data to be harnessed for manufacturing process optimization, remote management, and preventive maintenance. However, these gateways do not support fully-automatic configuration of newly added IoT devices. In this paper, we proposed a self-configurable gateway featuring real time detection and configuration of smart things over the wireless networks. This novel gateway's main features are: dynamic discovery of home IoT device(s), automatic updates of hardware changes, connection management of smart things connected over AllJoyn. We use the `option' field for automatic configuration of IoT devices rather than modify standard format of CoAP protocol. Proposed gateway functionality has been validated over the large-scale IoT testbed.","PeriodicalId":100643,"journal":{"name":"IEEE Transactions on Multi-Scale Computing Systems","volume":"3 3","pages":"206-214"},"PeriodicalIF":0.0,"publicationDate":"2017-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TMSCS.2017.2705683","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68070519","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-17DOI: 10.1109/TMSCS.2017.2705139
Yue Hu;David M. Koppelman;Steven Robert Brandt
Stencil computations form the basis for computer simulations across almost every field of science, such as computational fluid dynamics, data mining, and image processing. Their mostly regular data access patterns potentially enable them to take advantage of the high computation and data bandwidth of GPUs, but only if data buffering and other issues are handled properly. Finding a good code generation strategy presents a number of challenges, one of which is the best way to make use of memory. GPUs have several types of on-chip storage including registers, shared memory, and a read-only cache. The choice of type of storage and how it’s used, a buffering strategy , for each stencil array ( grid function , [GF]) not only requires a good understanding of its stencil pattern, but also the efficiency of each type of storage for the GF, to avoid squandering storage that would be more beneficial to another GF. For a stencil computation with $N$ GFs, the total number of possible assignments is $beta ^{N}$ where $beta$ is the number of buffering strategies. Our code-generation framework supports five buffering strategies ( $beta =5$ ). Large, complex stencil kernels may consist of dozens of GFs, resulting in significant search overhead. In this work, we present an analytic performance model for stencil computations on GPUs and study the behavior of read-only cache and L2 cache. Next, we propose an efficiency-based assignment algorithm which operates by scoring a change in buffering strategy for a GF using a combination of (a) the predicted execution time and (b) on-chip storage usage. By using this scoring, an assignment for $N$ GFs can be determined in $(beta -1)N(N+1)/2$ steps. Results show that the performance model has good accuracy and that the assignment strategy is highly efficient.
{"title":"Thoroughly Exploring GPU Buffering Options for Stencil Code by Using an Efficiency Measure and a Performance Model","authors":"Yue Hu;David M. Koppelman;Steven Robert Brandt","doi":"10.1109/TMSCS.2017.2705139","DOIUrl":"https://doi.org/10.1109/TMSCS.2017.2705139","url":null,"abstract":"Stencil computations form the basis for computer simulations across almost every field of science, such as computational fluid dynamics, data mining, and image processing. Their mostly regular data access patterns potentially enable them to take advantage of the high computation and data bandwidth of GPUs, but only if data buffering and other issues are handled properly. Finding a good code generation strategy presents a number of challenges, one of which is the best way to make use of memory. GPUs have several types of on-chip storage including registers, shared memory, and a read-only cache. The choice of type of storage and how it’s used, a \u0000<i>buffering strategy</i>\u0000, for each stencil array (\u0000<i>grid function</i>\u0000, [GF]) not only requires a good understanding of its stencil pattern, but also the efficiency of each type of storage for the GF, to avoid squandering storage that would be more beneficial to another GF. For a stencil computation with \u0000<inline-formula><tex-math>$N$</tex-math> </inline-formula>\u0000 GFs, the total number of possible assignments is \u0000<inline-formula><tex-math>$beta ^{N}$</tex-math></inline-formula>\u0000 where \u0000<inline-formula> <tex-math>$beta$</tex-math></inline-formula>\u0000 is the number of buffering strategies. Our code-generation framework supports five buffering strategies (\u0000<inline-formula><tex-math>$beta =5$</tex-math></inline-formula>\u0000). Large, complex stencil kernels may consist of dozens of GFs, resulting in significant search overhead. In this work, we present an analytic performance model for stencil computations on GPUs and study the behavior of read-only cache and L2 cache. Next, we propose an efficiency-based assignment algorithm which operates by scoring a change in buffering strategy for a GF using a combination of (a) the predicted execution time and (b) on-chip storage usage. By using this scoring, an assignment for \u0000<inline-formula><tex-math>$N$</tex-math></inline-formula>\u0000 GFs can be determined in \u0000<inline-formula><tex-math>$(beta -1)N(N+1)/2$</tex-math></inline-formula>\u0000 steps. Results show that the performance model has good accuracy and that the assignment strategy is highly efficient.","PeriodicalId":100643,"journal":{"name":"IEEE Transactions on Multi-Scale Computing Systems","volume":"4 3","pages":"477-490"},"PeriodicalIF":0.0,"publicationDate":"2017-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TMSCS.2017.2705139","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68024923","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-17DOI: 10.1109/TMSCS.2017.2664638
Presents a listing of reviewers who contributed to this publication in 2016.
提供2016年为本出版物做出贡献的评审人员名单。
{"title":"2016 Reviewers List","authors":"","doi":"10.1109/TMSCS.2017.2664638","DOIUrl":"https://doi.org/10.1109/TMSCS.2017.2664638","url":null,"abstract":"Presents a listing of reviewers who contributed to this publication in 2016.","PeriodicalId":100643,"journal":{"name":"IEEE Transactions on Multi-Scale Computing Systems","volume":"3 1","pages":"62-63"},"PeriodicalIF":0.0,"publicationDate":"2017-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TMSCS.2017.2664638","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68072480","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-17DOI: 10.1109/TMSCS.2016.2647518
Presents the 2016 author/subject index for this publication.
提供本出版物2016年的作者/主题索引。
{"title":"2016 Index IEEE Transactions on Multi-Scale Computing Systems Vol. 2","authors":"","doi":"10.1109/TMSCS.2016.2647518","DOIUrl":"https://doi.org/10.1109/TMSCS.2016.2647518","url":null,"abstract":"Presents the 2016 author/subject index for this publication.","PeriodicalId":100643,"journal":{"name":"IEEE Transactions on Multi-Scale Computing Systems","volume":"3 1","pages":"64-69"},"PeriodicalIF":0.0,"publicationDate":"2017-03-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TMSCS.2016.2647518","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68072483","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-16DOI: 10.1109/TMSCS.2017.2683487
Ujjwal Gupta;Raid Ayoub;Michael Kishinevsky;David Kadjo;Niranjan Soundararajan;Ugurkan Tursun;Umit Y. Ogras
Competitive graphics performance is crucial for the success of state-of-the-art mobile processors. High graphics performance comes at the cost of higher power consumption, which elevates the temperature due to limited cooling solutions. To avoid thermal violations, the system needs to operate within a power budget. Since the power budget is a shared resource, there is a strong demand for effective dynamic power budgeting techniques. This paper presents a novel technique to efficiently distribute the power budget among the CPU and GPU cores, while maximizing performance. The proposed technique is evaluated using a state-of-the-art mobile platform using industrial benchmarks, and an in-house simulator. The experiments on the mobile platform show up to 15% increase in average frame rate compared to default power allocation algorithms.
{"title":"Dynamic Power Budgeting for Mobile Systems Running Graphics Workloads","authors":"Ujjwal Gupta;Raid Ayoub;Michael Kishinevsky;David Kadjo;Niranjan Soundararajan;Ugurkan Tursun;Umit Y. Ogras","doi":"10.1109/TMSCS.2017.2683487","DOIUrl":"https://doi.org/10.1109/TMSCS.2017.2683487","url":null,"abstract":"Competitive graphics performance is crucial for the success of state-of-the-art mobile processors. High graphics performance comes at the cost of higher power consumption, which elevates the temperature due to limited cooling solutions. To avoid thermal violations, the system needs to operate within a power budget. Since the power budget is a shared resource, there is a strong demand for effective dynamic power budgeting techniques. This paper presents a novel technique to efficiently distribute the power budget among the CPU and GPU cores, while maximizing performance. The proposed technique is evaluated using a state-of-the-art mobile platform using industrial benchmarks, and an in-house simulator. The experiments on the mobile platform show up to 15% increase in average frame rate compared to default power allocation algorithms.","PeriodicalId":100643,"journal":{"name":"IEEE Transactions on Multi-Scale Computing Systems","volume":"4 1","pages":"30-40"},"PeriodicalIF":0.0,"publicationDate":"2017-03-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TMSCS.2017.2683487","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68003396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-15DOI: 10.1109/TMSCS.2017.2704101
Debajit Bhattacharya;Niraj K. Jha
With the increasing number of components in multiprocessor systems-on-chip, standard bus based communication architectures face a formidable scalability challenge. Network-on-chip (NoC), a type of communication architecture, addresses this scalability problem by distributing the communication resources among the communicating components. A huge bottleneck to modern NoC design is its extremely slow simulation/prototyping phase. Traditionally, analytical performance models have been used to speed up this phase. However, the currently available analytical models are not applicable to state-of-the-art NoCs. This forces NoC designers to rely on simulation/prototyping. In this work, we propose an analytical NoC performance analysis methodology for modeling the state-of-the-art single-cycle multi-hop asynchronous repeated traversal (SMART) NoC that enables packets to partially or completely bypass routers from source to destination. To the best of our knowledge, this is the first work on analytical modeling of NoCs that enable bypassing of routers. Our method registers a prediction error in network latency that is as low as 1 percent, and on an average below 2.5 and 8.4 percent, respectively, compared with the cycle-accurate GARNET network simulator and the gem5 full-system simulator running the PARSEC benchmark suite. The method also leads to two orders of magnitude speedup in computation time. It can account for variations in NoC design parameters, such as the maximum number of hops per cycle, number of virtual channels, flit size, buffer depth per virtual channel, etc. Even when these NoC design parameters are varied, our method's results remain within 5 percent of GARNET's results.
{"title":"Analytical Modeling of the SMART NoC","authors":"Debajit Bhattacharya;Niraj K. Jha","doi":"10.1109/TMSCS.2017.2704101","DOIUrl":"https://doi.org/10.1109/TMSCS.2017.2704101","url":null,"abstract":"With the increasing number of components in multiprocessor systems-on-chip, standard bus based communication architectures face a formidable scalability challenge. Network-on-chip (NoC), a type of communication architecture, addresses this scalability problem by distributing the communication resources among the communicating components. A huge bottleneck to modern NoC design is its extremely slow simulation/prototyping phase. Traditionally, analytical performance models have been used to speed up this phase. However, the currently available analytical models are not applicable to state-of-the-art NoCs. This forces NoC designers to rely on simulation/prototyping. In this work, we propose an analytical NoC performance analysis methodology for modeling the state-of-the-art single-cycle multi-hop asynchronous repeated traversal (SMART) NoC that enables packets to partially or completely bypass routers from source to destination. To the best of our knowledge, this is the first work on analytical modeling of NoCs that enable bypassing of routers. Our method registers a prediction error in network latency that is as low as 1 percent, and on an average below 2.5 and 8.4 percent, respectively, compared with the cycle-accurate GARNET network simulator and the gem5 full-system simulator running the PARSEC benchmark suite. The method also leads to two orders of magnitude speedup in computation time. It can account for variations in NoC design parameters, such as the maximum number of hops per cycle, number of virtual channels, flit size, buffer depth per virtual channel, etc. Even when these NoC design parameters are varied, our method's results remain within 5 percent of GARNET's results.","PeriodicalId":100643,"journal":{"name":"IEEE Transactions on Multi-Scale Computing Systems","volume":"3 4","pages":"242-254"},"PeriodicalIF":0.0,"publicationDate":"2017-03-15","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TMSCS.2017.2704101","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68022239","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-11DOI: 10.1109/TMSCS.2017.2703613
Ayten Ozge Akmandor;Niraj K. Jha
Long-term exposure to stress may lead to serious health problems such as those related to the immune, cardiovascular, and endocrine systems. Once having arisen, these problems require a considerable investment of time and money to recover from. With early detection and treatment, however, these health problems may be nipped in the bud, thus improving quality of life. We present an automatic stress detection and alleviation system, called SoDA, to address this issue. SoDA takes advantage of emerging wearable medical sensors (WMSs), specifically, electrocardiogram (ECG), galvanic skin response (GSR), respiration rate, blood pressure, and blood oximeter, to continuously monitor human stress levels and mitigate stress as it arises. It performs stress detection and alleviation in a user-transparent manner, i.e., without the need for user intervention. When it detects stress, SoDA employs a stress alleviation technique in an adaptive manner based on the stress response of the user. We establish the effectiveness of the proposed system through a detailed analysis of data collected from 32 participants. A total of four stressors and three stress reduction techniques are employed. In the stress detection stage, SoDA achieves 95.8 percent accuracy with a distinct combination of supervised feature selection and unsupervised dimensionality reduction. In the stress alleviation stage, we compare SoDA with the `no alleviation' baseline and validate its efficacy in responding to and alleviating stress.
{"title":"Keep the Stress Away with SoDA: Stress Detection and Alleviation System","authors":"Ayten Ozge Akmandor;Niraj K. Jha","doi":"10.1109/TMSCS.2017.2703613","DOIUrl":"https://doi.org/10.1109/TMSCS.2017.2703613","url":null,"abstract":"Long-term exposure to stress may lead to serious health problems such as those related to the immune, cardiovascular, and endocrine systems. Once having arisen, these problems require a considerable investment of time and money to recover from. With early detection and treatment, however, these health problems may be nipped in the bud, thus improving quality of life. We present an automatic stress detection and alleviation system, called SoDA, to address this issue. SoDA takes advantage of emerging wearable medical sensors (WMSs), specifically, electrocardiogram (ECG), galvanic skin response (GSR), respiration rate, blood pressure, and blood oximeter, to continuously monitor human stress levels and mitigate stress as it arises. It performs stress detection and alleviation in a user-transparent manner, i.e., without the need for user intervention. When it detects stress, SoDA employs a stress alleviation technique in an adaptive manner based on the stress response of the user. We establish the effectiveness of the proposed system through a detailed analysis of data collected from 32 participants. A total of four stressors and three stress reduction techniques are employed. In the stress detection stage, SoDA achieves 95.8 percent accuracy with a distinct combination of supervised feature selection and unsupervised dimensionality reduction. In the stress alleviation stage, we compare SoDA with the `no alleviation' baseline and validate its efficacy in responding to and alleviating stress.","PeriodicalId":100643,"journal":{"name":"IEEE Transactions on Multi-Scale Computing Systems","volume":"3 4","pages":"269-282"},"PeriodicalIF":0.0,"publicationDate":"2017-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TMSCS.2017.2703613","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68022240","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-03-05DOI: 10.1109/TMSCS.2017.2701795
Hang Lu;Guihai Yan;Yinhe Han;Xiaowei Li
Existing power management approaches for modern many-core processors resort to “centralized” design concept, aiming to optimize chip performance under fixed power budget. Unfortunately, the centralized power management approach, which usually relies on a dedicated on-chip power manager, faces various limitations such as poor scalability and high implementation overhead, and hence cannot be deployed in future large-scale manycores. This article proposes PowerTrader, an autonomous power management scheme. PowerTrader endows each core with self autonomy to issue the power control at any time to harvest the desirable power quota through negotiating with vicinity cores. It does not incur the overheads introduced by power allocation and statistics collection that are inevitable in centralized approaches, meanwhile chip power consumption could be well kept beneath the preset power budget. This article also elaborates on the key design tradeoff in autonomous power management (i.e., Mean-Time-to-Stable versus application power efficiency), and provides thorough design space exploration to justify the efficacy of the proposed approach. Experimental results show that PowerTrader achieves substantial improvements in both performance and power, and exhibits superior scalability compared with the state-of-the-arts.
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