Pub Date : 2017-03-03DOI: 10.1109/TMSCS.2017.2675888
Arsalan Mosenia;Susmita Sur-Kolay;Anand Raghunathan;Niraj K. Jha
Wearable medical sensors (WMSs) are garnering ever-increasing attention from both the scientific community and the industry. Driven by technological advances in sensing, wireless communication, and machine learning, WMS-based systems have begun transforming our daily lives. Although WMSswere initially developed to enable low-cost solutions for continuous health monitoring, the applications of WMS-based systems now range far beyond health care. Several research efforts have proposed the use of such systems in diverse application domains, e.g., education, human-computer interaction, and security. Even though the number of such research studies has grown drastically in the last few years, the potential challenges associated with their design, development, and implementation are neither well-studied nor well-recognized. This article discusses various services, applications, and systems that have been developed based on WMSs and sheds light on their design goals and challenges. We first provide a brief history of WMSs and discuss how their market is growing. We then discuss the scope of applications of WMS-based systems. Next, we describe the architecture of a typical WMS-based system and the components that constitute such a system, and their limitations. Thereafter, we suggest a list of desirable design goals that WMS-based systems should satisfy. Finally, we discuss various research directions related to WMSs and how previous research studies have attempted to address the limitations of the components used in WMS-based systems and satisfy the desirable design goals.
{"title":"Wearable Medical Sensor-Based System Design: A Survey","authors":"Arsalan Mosenia;Susmita Sur-Kolay;Anand Raghunathan;Niraj K. Jha","doi":"10.1109/TMSCS.2017.2675888","DOIUrl":"https://doi.org/10.1109/TMSCS.2017.2675888","url":null,"abstract":"Wearable medical sensors (WMSs) are garnering ever-increasing attention from both the scientific community and the industry. Driven by technological advances in sensing, wireless communication, and machine learning, WMS-based systems have begun transforming our daily lives. Although WMSswere initially developed to enable low-cost solutions for continuous health monitoring, the applications of WMS-based systems now range far beyond health care. Several research efforts have proposed the use of such systems in diverse application domains, e.g., education, human-computer interaction, and security. Even though the number of such research studies has grown drastically in the last few years, the potential challenges associated with their design, development, and implementation are neither well-studied nor well-recognized. This article discusses various services, applications, and systems that have been developed based on WMSs and sheds light on their design goals and challenges. We first provide a brief history of WMSs and discuss how their market is growing. We then discuss the scope of applications of WMS-based systems. Next, we describe the architecture of a typical WMS-based system and the components that constitute such a system, and their limitations. Thereafter, we suggest a list of desirable design goals that WMS-based systems should satisfy. Finally, we discuss various research directions related to WMSs and how previous research studies have attempted to address the limitations of the components used in WMS-based systems and satisfy the desirable design goals.","PeriodicalId":100643,"journal":{"name":"IEEE Transactions on Multi-Scale Computing Systems","volume":"3 2","pages":"124-138"},"PeriodicalIF":0.0,"publicationDate":"2017-03-03","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TMSCS.2017.2675888","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68021533","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-22DOI: 10.1109/TMSCS.2017.2672553
Punyasha Chatterjee;Sasthi C. Ghosh;Nabanita Das
In this paper, to gather streams of data in static wireless sensor networks, a novel graded node deployment strategy is proposed that generates minimum traffic, just sufficient for coverage. Based on this node distribution, a distributed, nearly load-balanced data gathering algorithm is developed to deliver packets to the sink node via minimum-hop paths that also in turn helps to limit the network traffic. An average case probabilistic analysis is done based on perfect matching of random bipartite graphs to establish a theoretical lower bound on the number of nodes to be deployed. Analysis and simulation studies show that the proposed model results huge enhancement in network lifetime that significantly overrides the cost due to over deployment. Hence, this technique offers an excellent cost-effective and energy-efficient solution for node deployment and routing in large wireless sensor networks to operate with prolonged lifetime.
{"title":"Load Balanced Coverage with Graded Node Deployment in Wireless Sensor Networks","authors":"Punyasha Chatterjee;Sasthi C. Ghosh;Nabanita Das","doi":"10.1109/TMSCS.2017.2672553","DOIUrl":"https://doi.org/10.1109/TMSCS.2017.2672553","url":null,"abstract":"In this paper, to gather streams of data in static wireless sensor networks, a novel graded node deployment strategy is proposed that generates minimum traffic, just sufficient for coverage. Based on this node distribution, a distributed, nearly load-balanced data gathering algorithm is developed to deliver packets to the sink node via minimum-hop paths that also in turn helps to limit the network traffic. An average case probabilistic analysis is done based on perfect matching of random bipartite graphs to establish a theoretical lower bound on the number of nodes to be deployed. Analysis and simulation studies show that the proposed model results huge enhancement in network lifetime that significantly overrides the cost due to over deployment. Hence, this technique offers an excellent cost-effective and energy-efficient solution for node deployment and routing in large wireless sensor networks to operate with prolonged lifetime.","PeriodicalId":100643,"journal":{"name":"IEEE Transactions on Multi-Scale Computing Systems","volume":"3 2","pages":"100-112"},"PeriodicalIF":0.0,"publicationDate":"2017-02-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TMSCS.2017.2672553","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68019439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-02-13DOI: 10.1109/TMSCS.2017.2667661
Haeseung Lee;Mohammad Abdullah Al Faruque
The demand for low-power and high-performance computing has been driving the semiconductor industry for decades. The semiconductor technology has been scaled down to satisfy these demands. At the same time, the semiconductor technology has faced severe reliability challenges like soft-error. Research has been conducted to improve the soft-error reliability of the GPU, which has been improved by using various methodologies such as redundancy methodologies. However, the GPU compiler has yet to be considered for improving the soft-error reliability of the GPU. In this paper, in order to improve the soft-error reliability of the GPU, we propose a novel GPU architecture aware compilation methodology. The proposed methodology jointly considers the parallel behavior of the GPU hardware and the applications, and minimizes the vulnerability of the GPU applications during instruction scheduling. In addition, the proposed methodology is able to complement any hardware based soft-error reliability improvement techniques. We compared our compilation methodology with the state-of-the-art soft-error reliability aware techniques and the performance aware instruction scheduling. We have injected the soft-errors during the experiments and have compared the number of correct executions that have no erroneous output. Our methodology requires less performance and power overhead than the state-of-the-art soft-error reliability methodologies in most cases. Compilation time overhead of our methodology is 8.13 seconds on average. The experimental results show that our methodology improves the soft-error reliability by 23 percent and 12 percent (up to 64 percent and 52 percent) compared to the state-of-the-art soft-error reliability and performance aware compilation techniques, respectively. Moreover, we have shown that the soft-error reliability of a GPU is not related to the performance, but to the fine-grained timing behavior of an application.
{"title":"GPU Architecture Aware Instruction Scheduling for Improving Soft-Error Reliability","authors":"Haeseung Lee;Mohammad Abdullah Al Faruque","doi":"10.1109/TMSCS.2017.2667661","DOIUrl":"https://doi.org/10.1109/TMSCS.2017.2667661","url":null,"abstract":"The demand for low-power and high-performance computing has been driving the semiconductor industry for decades. The semiconductor technology has been scaled down to satisfy these demands. At the same time, the semiconductor technology has faced severe reliability challenges like soft-error. Research has been conducted to improve the soft-error reliability of the GPU, which has been improved by using various methodologies such as redundancy methodologies. However, the GPU compiler has yet to be considered for improving the soft-error reliability of the GPU. In this paper, in order to improve the soft-error reliability of the GPU, we propose a novel GPU architecture aware compilation methodology. The proposed methodology jointly considers the parallel behavior of the GPU hardware and the applications, and minimizes the vulnerability of the GPU applications during instruction scheduling. In addition, the proposed methodology is able to complement any hardware based soft-error reliability improvement techniques. We compared our compilation methodology with the state-of-the-art soft-error reliability aware techniques and the performance aware instruction scheduling. We have injected the soft-errors during the experiments and have compared the number of correct executions that have no erroneous output. Our methodology requires less performance and power overhead than the state-of-the-art soft-error reliability methodologies in most cases. Compilation time overhead of our methodology is 8.13 seconds on average. The experimental results show that our methodology improves the soft-error reliability by 23 percent and 12 percent (up to 64 percent and 52 percent) compared to the state-of-the-art soft-error reliability and performance aware compilation techniques, respectively. Moreover, we have shown that the soft-error reliability of a GPU is not related to the performance, but to the fine-grained timing behavior of an application.","PeriodicalId":100643,"journal":{"name":"IEEE Transactions on Multi-Scale Computing Systems","volume":"3 2","pages":"86-99"},"PeriodicalIF":0.0,"publicationDate":"2017-02-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TMSCS.2017.2667661","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"67856116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
General-purpose graphics processing units (GPGPUs), as programmable accelerators, improve energy efficiency by integrating a large number of relatively small cores. In this paper, we focus on improving energy efficiency of such processing core by integrating an associative memory where function responses are prestored. Associative memories can search and recall function responses for a subset of input values therefore avoiding the actual function execution on the processing core that leads to energy saving. We propose a novel low-energy Resistive Multi-stage Associative Memory (ReMAM) architecture to significantly reduce energy of a search operation by employing selective row activation and in-advance precharging techniques. ReMAM splits the search operations in a ternary content addressable memory (TCAM) to a number of shorter searches in consecutive stages. Then, it selectively activates TCAM rows at each stage based on the hits of previous stages, thus enabling energy savings. The proposed inadvance precharging technique mitigates the delay of the sequential TCAM search and limits the number of precharges to two low-cost steps. ReMAM further implements approximation on the selective TCAM blocks to reduce the search energy that relaxes the function output in a fine-grained granularity with very low impact on accuracy of the results. Its multi-stage search operation makes ReMAM applicable to many applications such as search engines, sorting, image coding, pattern recognition, query processing, and machine learning. In this work, we show an application of proposed ReMAM on AMD Southern Island GPUs. Our experimental evaluation shows that ReMAM reduces on average GPGPU energy consumption by 35 percent in the exact mode, and 58 percent in approximate mode with average relative error lower than 10 percent. These energy savings are 1.8x and 1.5x higher than state-of-the-art associative memories used in GPGPUs in exact and approximate modes.
{"title":"Multi-Stage Tunable Approximate Search in Resistive Associative Memory","authors":"Mohsen Imani;Abbas Rahimi;Pietro Mercati;Tajana Simunic Rosing","doi":"10.1109/TMSCS.2017.2665462","DOIUrl":"https://doi.org/10.1109/TMSCS.2017.2665462","url":null,"abstract":"General-purpose graphics processing units (GPGPUs), as programmable accelerators, improve energy efficiency by integrating a large number of relatively small cores. In this paper, we focus on improving energy efficiency of such processing core by integrating an associative memory where function responses are prestored. Associative memories can search and recall function responses for a subset of input values therefore avoiding the actual function execution on the processing core that leads to energy saving. We propose a novel low-energy Resistive Multi-stage Associative Memory (ReMAM) architecture to significantly reduce energy of a search operation by employing selective row activation and in-advance precharging techniques. ReMAM splits the search operations in a ternary content addressable memory (TCAM) to a number of shorter searches in consecutive stages. Then, it selectively activates TCAM rows at each stage based on the hits of previous stages, thus enabling energy savings. The proposed inadvance precharging technique mitigates the delay of the sequential TCAM search and limits the number of precharges to two low-cost steps. ReMAM further implements approximation on the selective TCAM blocks to reduce the search energy that relaxes the function output in a fine-grained granularity with very low impact on accuracy of the results. Its multi-stage search operation makes ReMAM applicable to many applications such as search engines, sorting, image coding, pattern recognition, query processing, and machine learning. In this work, we show an application of proposed ReMAM on AMD Southern Island GPUs. Our experimental evaluation shows that ReMAM reduces on average GPGPU energy consumption by 35 percent in the exact mode, and 58 percent in approximate mode with average relative error lower than 10 percent. These energy savings are 1.8x and 1.5x higher than state-of-the-art associative memories used in GPGPUs in exact and approximate modes.","PeriodicalId":100643,"journal":{"name":"IEEE Transactions on Multi-Scale Computing Systems","volume":"4 1","pages":"17-29"},"PeriodicalIF":0.0,"publicationDate":"2017-02-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TMSCS.2017.2665462","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68003395","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2017-01-04DOI: 10.1109/TMSCS.2016.2643638
Qian Wang;An Wang;Gang Qu;Guoshuang Zhang
Fault Sensitivity Analysis (FSA) is a side-channel attack that utilizes the sensitive delay of circuits to retrieve the key in cryptographic systems. In this paper, we propose the concept of right or wrong collision (RWC) rate and use it to build templates on two S-boxes, one is the target of the attack and the other is used as a reference. Compared to the traditional Hamming weight model which has eight different values, our template model is two-dimensional with 256 different values and has the potential to significantly reduce the number of plaintext required to reveal the key. Attack experiments show that our template attack can successfully break the masked AES algorithm with only one clock frequency. Furthermore, we propose two improved template attack methods that can reduce the complexity for building templates to 1/256 and 9/256 of the original method, respectively. The improved method with different frequencies also improves the efficiency of template matching by 86.3 percent. Finally and most importantly, our methods can be used to break masked AES where the S-boxes do not have to be implemented by parallel AND gates, a major limitation of the current Hamming weight models.
{"title":"New Methods of Template Attack Based on Fault Sensitivity Analysis","authors":"Qian Wang;An Wang;Gang Qu;Guoshuang Zhang","doi":"10.1109/TMSCS.2016.2643638","DOIUrl":"https://doi.org/10.1109/TMSCS.2016.2643638","url":null,"abstract":"Fault Sensitivity Analysis (FSA) is a side-channel attack that utilizes the sensitive delay of circuits to retrieve the key in cryptographic systems. In this paper, we propose the concept of right or wrong collision (RWC) rate and use it to build templates on two S-boxes, one is the target of the attack and the other is used as a reference. Compared to the traditional Hamming weight model which has eight different values, our template model is two-dimensional with 256 different values and has the potential to significantly reduce the number of plaintext required to reveal the key. Attack experiments show that our template attack can successfully break the masked AES algorithm with only one clock frequency. Furthermore, we propose two improved template attack methods that can reduce the complexity for building templates to 1/256 and 9/256 of the original method, respectively. The improved method with different frequencies also improves the efficiency of template matching by 86.3 percent. Finally and most importantly, our methods can be used to break masked AES where the S-boxes do not have to be implemented by parallel AND gates, a major limitation of the current Hamming weight models.","PeriodicalId":100643,"journal":{"name":"IEEE Transactions on Multi-Scale Computing Systems","volume":"3 2","pages":"113-123"},"PeriodicalIF":0.0,"publicationDate":"2017-01-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TMSCS.2016.2643638","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68021532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-12-08DOI: 10.1109/TMSCS.2016.2637345
Ujjwal Gupta;Jaehyun Park;Hitesh Joshi;Umit Y. Ogras
Mechanically flexible, printed, and stretchable electronics are gaining momentum. While rapid advancement is well underway at the device and circuit levels, researchers have yet to envision the system design in a flexible form. This paper introduces the concept of System-on-Polymer (SoP) based on flexible hybrid electronics (FHE) to combine the advantages of flexible electronics and traditional silicon technology. First, we formally define flexibility as a new design metric in addition to existing power, performance, and area metrics. Then, we present a novel optimization approach to place rigid components onto a flexible substrate while minimizing the loss in flexibility. We show that the optimal placement leads to as much as 5.7 $times$ enhancement in flexibility compared to a naïve placement. We confirm the accuracy of our models and optimization framework using a finite element method (FEM) simulator. Finally, we demonstrate the SoP concept using a concrete hardware prototype, and discuss the major challenges in the architecture and design of SoPs.
{"title":"Flexibility-Aware System-on-Polymer (SoP): Concept to Prototype","authors":"Ujjwal Gupta;Jaehyun Park;Hitesh Joshi;Umit Y. Ogras","doi":"10.1109/TMSCS.2016.2637345","DOIUrl":"https://doi.org/10.1109/TMSCS.2016.2637345","url":null,"abstract":"Mechanically flexible, printed, and stretchable electronics are gaining momentum. While rapid advancement is well underway at the device and circuit levels, researchers have yet to envision the system design in a flexible form. This paper introduces the concept of \u0000<i>System-on-Polymer (SoP)</i>\u0000 based on flexible hybrid electronics (FHE) to combine the advantages of flexible electronics and traditional silicon technology. First, we formally define flexibility as a new design metric in addition to existing power, performance, and area metrics. Then, we present a novel optimization approach to place rigid components onto a flexible substrate while minimizing the loss in flexibility. We show that the optimal placement leads to as much as 5.7\u0000<inline-formula><tex-math> $times$</tex-math></inline-formula>\u0000 enhancement in flexibility compared to a naïve placement. We confirm the accuracy of our models and optimization framework using a finite element method (FEM) simulator. Finally, we demonstrate the SoP concept using a concrete hardware prototype, and discuss the major challenges in the architecture and design of SoPs.","PeriodicalId":100643,"journal":{"name":"IEEE Transactions on Multi-Scale Computing Systems","volume":"3 1","pages":"36-49"},"PeriodicalIF":0.0,"publicationDate":"2016-12-08","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TMSCS.2016.2637345","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68072481","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-22DOI: 10.1109/TMSCS.2016.2631534
Trey Reece;Supreeth Sathyanarayana;William H. Robinson;Raheem A. Beyah
In order to combat the growing threat of counterfeit components, this paper describes a technique to fingerprint and identify components based upon the way in which they send and process ICMP, UDP, and TCP network packets. These network fingerprints are then processed by an artificial neural network in order to categorize and classify individual processors. These tests found that ICMP and UDP packets provided an an effective, inexpensive, and fast tool for identifying counterfeit components in a network.
{"title":"On The Outside Looking In: Towards Detecting Counterfeit Devices Using Network Traffic Analysis","authors":"Trey Reece;Supreeth Sathyanarayana;William H. Robinson;Raheem A. Beyah","doi":"10.1109/TMSCS.2016.2631534","DOIUrl":"https://doi.org/10.1109/TMSCS.2016.2631534","url":null,"abstract":"In order to combat the growing threat of counterfeit components, this paper describes a technique to fingerprint and identify components based upon the way in which they send and process ICMP, UDP, and TCP network packets. These network fingerprints are then processed by an artificial neural network in order to categorize and classify individual processors. These tests found that ICMP and UDP packets provided an an effective, inexpensive, and fast tool for identifying counterfeit components in a network.","PeriodicalId":100643,"journal":{"name":"IEEE Transactions on Multi-Scale Computing Systems","volume":"3 1","pages":"50-61"},"PeriodicalIF":0.0,"publicationDate":"2016-11-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TMSCS.2016.2631534","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68072482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-10DOI: 10.1109/TMSCS.2016.2627543
Younghyun Kim;Vijay Raghunathan;Anand Raghunathan
Regulation services (RS) play an important role in maintaining the stability of electric grids by correcting for short-term mismatches between electricity generation and demand. RS providers dynamically supply electricity to the grid or consume electricity from it, in response to regulation signals, in return for economic compensation. This capability is commonly realized through large-scale electrical energy storage (EES) systems based on batteries. However, the highly transient nature of the regulation signals implies that the batteries used for RS are subject to frequent charge and discharge cycles, leading to shortened battery life and thereby impacting the profitability of RS. In this work, we explore the use of hybrid EES (HEES) systems, which combine batteries and supercapacitors, to improve the profitability of RS. HEES systems have the potential to reduce the cost of providing RS by utilizing supercapacitors to respond to the high-frequency components of the regulation signal, prolonging battery life. However, realizing this potential presents several challenges. First, the benefits of HEES systems have a profound dependence on the type of hybrid topology (i.e., active or passive), which results in a tradeoff between the implementation cost and the utilization of the supercapacitor capacity. Second, the allocation of energy storage capacity to batteries and supercapacitors should be carefully determined in the design phase because the reduction in battery replacement cost due to the use of supercapacitors must be balanced against the increased upfront cost for supercapacitors. Third, active HEES systems involve the problem of managing the power flows to batteries and supercapacitors so as to realize maximum cost benefits. To address these challenges, we present a framework for the design and management of a HEES system, so as to maximize the profit from the perspective of an RS provider. This framework consists of i) a design-time capacity optimization phase that determines the best allocation of capacity to batteries and supercapacitors and ii) a run-time management scheme that selects how the different storage devices are orchestrated considering their characteristics and the incoming regulation signal. Our experiments show that, with the proposed capacity optimization and management framework, the use of a passive or an active HEES system can improve the profit of RS providers by 1.16× or 5.44×, respectively.
{"title":"Design and Management of Battery-Supercapacitor Hybrid Electrical Energy Storage Systems for Regulation Services","authors":"Younghyun Kim;Vijay Raghunathan;Anand Raghunathan","doi":"10.1109/TMSCS.2016.2627543","DOIUrl":"https://doi.org/10.1109/TMSCS.2016.2627543","url":null,"abstract":"Regulation services (RS) play an important role in maintaining the stability of electric grids by correcting for short-term mismatches between electricity generation and demand. RS providers dynamically supply electricity to the grid or consume electricity from it, in response to regulation signals, in return for economic compensation. This capability is commonly realized through large-scale electrical energy storage (EES) systems based on batteries. However, the highly transient nature of the regulation signals implies that the batteries used for RS are subject to frequent charge and discharge cycles, leading to shortened battery life and thereby impacting the profitability of RS. In this work, we explore the use of hybrid EES (HEES) systems, which combine batteries and supercapacitors, to improve the profitability of RS. HEES systems have the potential to reduce the cost of providing RS by utilizing supercapacitors to respond to the high-frequency components of the regulation signal, prolonging battery life. However, realizing this potential presents several challenges. First, the benefits of HEES systems have a profound dependence on the type of hybrid topology (i.e., active or passive), which results in a tradeoff between the implementation cost and the utilization of the supercapacitor capacity. Second, the allocation of energy storage capacity to batteries and supercapacitors should be carefully determined in the design phase because the reduction in battery replacement cost due to the use of supercapacitors must be balanced against the increased upfront cost for supercapacitors. Third, active HEES systems involve the problem of managing the power flows to batteries and supercapacitors so as to realize maximum cost benefits. To address these challenges, we present a framework for the design and management of a HEES system, so as to maximize the profit from the perspective of an RS provider. This framework consists of i) a design-time capacity optimization phase that determines the best allocation of capacity to batteries and supercapacitors and ii) a run-time management scheme that selects how the different storage devices are orchestrated considering their characteristics and the incoming regulation signal. Our experiments show that, with the proposed capacity optimization and management framework, the use of a passive or an active HEES system can improve the profit of RS providers by 1.16× or 5.44×, respectively.","PeriodicalId":100643,"journal":{"name":"IEEE Transactions on Multi-Scale Computing Systems","volume":"3 1","pages":"12-24"},"PeriodicalIF":0.0,"publicationDate":"2016-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TMSCS.2016.2627543","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68072479","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2016-11-10DOI: 10.1109/TMSCS.2016.2627541
Tiago Rogerio Mück;Zana Ghaderi;Nikil D. Dutt;Eli Bozorgzadeh
The pervasiveness of heterogeneous multiprocessors (HMP) in the mobile domain enables more energy efficient systems. However, current approaches to exploit the energy efficiency of HMPs results in unbalanced usage of resources, which leads to higher aging rates and delay degradation when compared to homogeneous architectures. In this paper, we propose ADAMANT, an aging-aware task mapping algorithm for HMPs. ADAMANT exploits on-chip sensing of aging, performance, and power in orderto enable on-line workload characterization to select task-to-core mappings that yield both increased system lifetime and energy efficiency. Experimental evaluation using a typical mobile workload demonstrates an improvement in chip lifetime by up to 2x on a big.LITTLE architecture.
{"title":"Exploiting Heterogeneity for Aging-Aware Load Balancing in Mobile Platforms","authors":"Tiago Rogerio Mück;Zana Ghaderi;Nikil D. Dutt;Eli Bozorgzadeh","doi":"10.1109/TMSCS.2016.2627541","DOIUrl":"https://doi.org/10.1109/TMSCS.2016.2627541","url":null,"abstract":"The pervasiveness of heterogeneous multiprocessors (HMP) in the mobile domain enables more energy efficient systems. However, current approaches to exploit the energy efficiency of HMPs results in unbalanced usage of resources, which leads to higher aging rates and delay degradation when compared to homogeneous architectures. In this paper, we propose ADAMANT, an aging-aware task mapping algorithm for HMPs. ADAMANT exploits on-chip sensing of aging, performance, and power in orderto enable on-line workload characterization to select task-to-core mappings that yield both increased system lifetime and energy efficiency. Experimental evaluation using a typical mobile workload demonstrates an improvement in chip lifetime by up to 2x on a big.LITTLE architecture.","PeriodicalId":100643,"journal":{"name":"IEEE Transactions on Multi-Scale Computing Systems","volume":"3 1","pages":"25-35"},"PeriodicalIF":0.0,"publicationDate":"2016-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TMSCS.2016.2627541","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68072477","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
The increasing complexity of networked computing systems makes modern network systems vulnerable to various attacks against their resources, infrastructure, and operability. While the reasons for such attacks may be tied to complex sociological issues, the cause of the inadequate defense solutions lies in the single-layered approach used to address computer systems security. Current security approaches separate defense strategies into distinct realms, either hardware or software. Accordingly, cross-layer approaches for secure computing and circuit systems are entirely lacking. In addition, the wide usage of third-party IP cores and outsourcing fabrication/packaging services make it possible for malicious hardware modules to enter the design flow and complicate the problem of trusted system design and verification. Although hardware security has been under investigation for years, systematically understanding the security threats to hardware infrastructure from a cross-layer perspective is an emerging research topic. Therefore, this special issue intends to serve as a forum to present state-of-the-art security solutions crossing software and hardware layers towards trustworthy computing system development.
{"title":"Guest Editorial: Hardware/Software Cross-Layer Technologies for Trustworthy and Secure Computing","authors":"Shiyan Hu;Yier Jin;Kenneth Heffner;Mark Tehranipoor","doi":"10.1109/TMSCS.2016.2609298","DOIUrl":"https://doi.org/10.1109/TMSCS.2016.2609298","url":null,"abstract":"The increasing complexity of networked computing systems makes modern network systems vulnerable to various attacks against their resources, infrastructure, and operability. While the reasons for such attacks may be tied to complex sociological issues, the cause of the inadequate defense solutions lies in the single-layered approach used to address computer systems security. Current security approaches separate defense strategies into distinct realms, either hardware or software. Accordingly, cross-layer approaches for secure computing and circuit systems are entirely lacking. In addition, the wide usage of third-party IP cores and outsourcing fabrication/packaging services make it possible for malicious hardware modules to enter the design flow and complicate the problem of trusted system design and verification. Although hardware security has been under investigation for years, systematically understanding the security threats to hardware infrastructure from a cross-layer perspective is an emerging research topic. Therefore, this special issue intends to serve as a forum to present state-of-the-art security solutions crossing software and hardware layers towards trustworthy computing system development.","PeriodicalId":100643,"journal":{"name":"IEEE Transactions on Multi-Scale Computing Systems","volume":"2 3","pages":"144-145"},"PeriodicalIF":0.0,"publicationDate":"2016-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/TMSCS.2016.2609298","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"68035099","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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