Cryogenic quantum computers play a leading role in demonstrating quantum advantage. Given the severe constraints on the cooling capacity in cryogenic environments, thermal design is crucial for the scalability of these computers. The sources of heat dissipation include passive inflow via intertemperature wires and the power consumption of components located in the cryostat, such as wire amplifiers and quantum–classical interfaces. Thus, a critical challenge is to reduce the number of wires by reducing the required intertemperature bandwidth while maintaining minimal additional power consumption in the cryostat. One solution to address this challenge is near-data processing using ultralow-power computational logic within the cryostat. Based on the workload analysis and domain-specific system design focused on variational quantum algorithms (VQAs), we propose the cryogenic counter-based coprocessor for VQAs (C3-VQA) to enhance the design scalability of cryogenic quantum computers under the thermal constraint. The C3-VQA utilizes single-flux-quantum logic, which is an ultralow-power superconducting digital circuit that operates at the 4 K environment. The C3-VQA precomputes a part of the expectation value calculations for VQAs and buffers intermediate values using simple bit operation units and counters in the cryostat, thereby reducing the required intertemperature bandwidth with small additional power consumption. Consequently, the C3-VQA reduces the number of wires, leading to a reduction in the total heat dissipation in the cryostat. Our evaluation shows that the C3-VQA reduces the total heat dissipation at the 4 K stage by 30% and 81% under sequential-shot and parallel-shot execution scenarios, respectively. Furthermore, a case study in quantum chemistry shows that the C3-VQA reduces total heat dissipation by 87% with a 10 000-qubit system.
{"title":"C3-VQA: Cryogenic Counter-Based Coprocessor for Variational Quantum Algorithms","authors":"Yosuke Ueno;Satoshi Imamura;Yuna Tomida;Teruo Tanimoto;Masamitsu Tanaka;Yutaka Tabuchi;Koji Inoue;Hiroshi Nakamura","doi":"10.1109/TQE.2024.3521442","DOIUrl":"https://doi.org/10.1109/TQE.2024.3521442","url":null,"abstract":"Cryogenic quantum computers play a leading role in demonstrating quantum advantage. Given the severe constraints on the cooling capacity in cryogenic environments, thermal design is crucial for the scalability of these computers. The sources of heat dissipation include passive inflow via intertemperature wires and the power consumption of components located in the cryostat, such as wire amplifiers and quantum–classical interfaces. Thus, a critical challenge is to reduce the number of wires by reducing the required intertemperature bandwidth while maintaining minimal additional power consumption in the cryostat. One solution to address this challenge is near-data processing using ultralow-power computational logic within the cryostat. Based on the workload analysis and domain-specific system design focused on variational quantum algorithms (VQAs), we propose the cryogenic counter-based coprocessor for VQAs (C3-VQA) to enhance the design scalability of cryogenic quantum computers under the thermal constraint. The C3-VQA utilizes single-flux-quantum logic, which is an ultralow-power superconducting digital circuit that operates at the 4 K environment. The C3-VQA precomputes a part of the expectation value calculations for VQAs and buffers intermediate values using simple bit operation units and counters in the cryostat, thereby reducing the required intertemperature bandwidth with small additional power consumption. Consequently, the C3-VQA reduces the number of wires, leading to a reduction in the total heat dissipation in the cryostat. Our evaluation shows that the C3-VQA reduces the total heat dissipation at the 4 K stage by 30% and 81% under sequential-shot and parallel-shot execution scenarios, respectively. Furthermore, a case study in quantum chemistry shows that the C3-VQA reduces total heat dissipation by 87% with a 10 000-qubit system.","PeriodicalId":100644,"journal":{"name":"IEEE Transactions on Quantum Engineering","volume":"6 ","pages":"1-17"},"PeriodicalIF":0.0,"publicationDate":"2024-12-23","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10812867","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142993763","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-20DOI: 10.1109/TQE.2024.3520805
João Barbosa;Jack C. Brennan;Alessandro Casaburi;M. D. Hutchings;Alex Kirichenko;Oleg Mukhanov;Martin Weides
One of the most important and topical challenges of quantum circuits is their scalability. Rapid single flux quantum (RSFQ) technology is at the forefront of replacing current standard CMOS-based control architectures for a number of applications, including quantum computing and quantum sensor arrays. By condensing the control and readout to single-flux-quantum-based on-chip devices that are directly connected to the quantum systems, it is possible to minimize the total system overhead, improving scalability and integration. In this article, we present a novel RSFQ device that generates multitone digital signals, based on complex pulse train sequences using a circular shift register (CSR) and a comb filter stage. We show that the frequency spectrum of the pulse trains is dependent on a preloaded pattern on the CSR, as well as on the delay line of the comb filter stage. By carefully selecting both the pattern and delay, the desired tones can be isolated and amplified as required. Finally, we propose architectures where this device can be implemented to control and read out arrays of quantum devices, such as qubits and single-photon detectors.
{"title":"RSFQ All-Digital Programmable Multitone Generator for Quantum Applications","authors":"João Barbosa;Jack C. Brennan;Alessandro Casaburi;M. D. Hutchings;Alex Kirichenko;Oleg Mukhanov;Martin Weides","doi":"10.1109/TQE.2024.3520805","DOIUrl":"https://doi.org/10.1109/TQE.2024.3520805","url":null,"abstract":"One of the most important and topical challenges of quantum circuits is their scalability. Rapid single flux quantum (RSFQ) technology is at the forefront of replacing current standard CMOS-based control architectures for a number of applications, including quantum computing and quantum sensor arrays. By condensing the control and readout to single-flux-quantum-based on-chip devices that are directly connected to the quantum systems, it is possible to minimize the total system overhead, improving scalability and integration. In this article, we present a novel RSFQ device that generates multitone digital signals, based on complex pulse train sequences using a circular shift register (CSR) and a comb filter stage. We show that the frequency spectrum of the pulse trains is dependent on a preloaded pattern on the CSR, as well as on the delay line of the comb filter stage. By carefully selecting both the pattern and delay, the desired tones can be isolated and amplified as required. Finally, we propose architectures where this device can be implemented to control and read out arrays of quantum devices, such as qubits and single-photon detectors.","PeriodicalId":100644,"journal":{"name":"IEEE Transactions on Quantum Engineering","volume":"6 ","pages":"1-11"},"PeriodicalIF":0.0,"publicationDate":"2024-12-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10811769","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142975731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Complementary metal–oxide–semiconductor (CMOS)-based computing promises drastic improvement in performance at extremely low temperatures (e.g., 77 K, 10 K). The field of extremely low temperature CMOS-environment-based computing holds the promise of delivering remarkable enhancements in both performance and power consumption. Static random access memory (SRAM) plays a major role in determining the performance and efficiency of any processor due to its superior performance and density. This work aims to reveal how extremely low temperature operations profoundly impact the existing well-known tradeoffs in SRAM-based memory arrays. To accomplish this, first, we measure and model the 5 nm fin field-effect transistors characteristics over a wide temperature range from 300 K down to 10 K. Next, we develop a framework to perform simulations on the SRAM array by varying the number of rows and columns for examining the influence of leakage current ($I$leak) and parasitic effects of bit line (BL) and word line (WL) on the size and performance of the SRAM array under extremely low temperatures. For a comprehensive analysis, we further investigated the maximum attainable array size, extending our study down to 10 K, utilizing three distinct cell types. With the help of SRAM array simulations, we reveal that the maximum array size at extremely low temperatures is limited by WL parasitics instead of $I$leak, and the performance of the SRAM is governed by BL and WL parasitics. In addition, we elucidate the influence of transistor threshold voltage ($V$TH) engineering on the optimization of the SRAM array at extremely low temperature environments.
{"title":"Novel Trade-offs in 5 nm FinFET SRAM Arrays at Extremely Low Temperatures","authors":"Shivendra Singh Parihar;Girish Pahwa;Baker Mohammad;Yogesh Singh Chauhan;Hussam Amrouch","doi":"10.1109/TQE.2024.3512367","DOIUrl":"https://doi.org/10.1109/TQE.2024.3512367","url":null,"abstract":"Complementary metal–oxide–semiconductor (CMOS)-based computing promises drastic improvement in performance at extremely low temperatures (e.g., 77 K, 10 K). The field of extremely low temperature CMOS-environment-based computing holds the promise of delivering remarkable enhancements in both performance and power consumption. Static random access memory (SRAM) plays a major role in determining the performance and efficiency of any processor due to its superior performance and density. This work aims to reveal how extremely low temperature operations profoundly impact the existing well-known tradeoffs in SRAM-based memory arrays. To accomplish this, first, we measure and model the 5 nm fin field-effect transistors characteristics over a wide temperature range from 300 K down to 10 K. Next, we develop a framework to perform simulations on the SRAM array by varying the number of rows and columns for examining the influence of leakage current (<inline-formula><tex-math>$I$</tex-math></inline-formula><sub>leak</sub>) and parasitic effects of bit line (BL) and word line (WL) on the size and performance of the SRAM array under extremely low temperatures. For a comprehensive analysis, we further investigated the maximum attainable array size, extending our study down to 10 K, utilizing three distinct cell types. With the help of SRAM array simulations, we reveal that the maximum array size at extremely low temperatures is limited by WL parasitics instead of <inline-formula><tex-math>$I$</tex-math></inline-formula><sub>leak</sub>, and the performance of the SRAM is governed by BL and WL parasitics. In addition, we elucidate the influence of transistor threshold voltage (<inline-formula><tex-math>$V$</tex-math></inline-formula><sub>TH</sub>) engineering on the optimization of the SRAM array at extremely low temperature environments.","PeriodicalId":100644,"journal":{"name":"IEEE Transactions on Quantum Engineering","volume":"6 ","pages":"1-15"},"PeriodicalIF":0.0,"publicationDate":"2024-12-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10778409","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142975730","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-12-04DOI: 10.1109/TQE.2024.3511419
Yigal Ilin;Itai Arad
In recent years, variational quantum algorithms have gained significant attention due to their adaptability and efficiency on near-term quantum hardware. They have shown potential in a variety of tasks, including linear algebra, search problems, Gibbs, and ground state preparation. Nevertheless, the presence of noise in current day quantum hardware severely limits their performance. In this work, we introduce dissipative variational quantum algorithms (D-VQAs) by incorporating dissipative operations, such as qubit RESET and stochastic gates, as an intrinsic part of a variational quantum circuit. We argue that such dissipative variational algorithms possess some natural resilience to dissipative noise. We demonstrate how such algorithms can prepare Gibbs states over a wide range of quantum many-body Hamiltonians and temperatures, while significantly reducing errors due to both coherent and noncoherent noise. An additional advantage of our approach is that no ancilla qubits are need. Our results highlight the potential of D-VQAs to enhance the robustness and accuracy of variational quantum computations on noisy intermediate-scale quantum (NISQ) devices.
{"title":"Dissipative Variational Quantum Algorithms for Gibbs State Preparation","authors":"Yigal Ilin;Itai Arad","doi":"10.1109/TQE.2024.3511419","DOIUrl":"https://doi.org/10.1109/TQE.2024.3511419","url":null,"abstract":"In recent years, variational quantum algorithms have gained significant attention due to their adaptability and efficiency on near-term quantum hardware. They have shown potential in a variety of tasks, including linear algebra, search problems, Gibbs, and ground state preparation. Nevertheless, the presence of noise in current day quantum hardware severely limits their performance. In this work, we introduce dissipative variational quantum algorithms (D-VQAs) by incorporating dissipative operations, such as qubit RESET and stochastic gates, as an intrinsic part of a variational quantum circuit. We argue that such dissipative variational algorithms possess some natural resilience to dissipative noise. We demonstrate how such algorithms can prepare Gibbs states over a wide range of quantum many-body Hamiltonians and temperatures, while significantly reducing errors due to both coherent and noncoherent noise. An additional advantage of our approach is that no ancilla qubits are need. Our results highlight the potential of D-VQAs to enhance the robustness and accuracy of variational quantum computations on noisy intermediate-scale quantum (NISQ) devices.","PeriodicalId":100644,"journal":{"name":"IEEE Transactions on Quantum Engineering","volume":"6 ","pages":"1-12"},"PeriodicalIF":0.0,"publicationDate":"2024-12-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10777530","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142905740","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-28DOI: 10.1109/TQE.2024.3509019
Ilora Maity;Junaid ur Rehman;Symeon Chatzinotas
Quantum key distribution (QKD) provides a secure method to exchange encrypted information between two parties in a quantum communication infrastructure (QCI). The primary challenge in deploying a QCI is the cost of using optical fibers and trusted repeater nodes (TRNs). Practical systems combine quantum and classical channels on the same fiber to reduce the cost of fibers dedicated to QKD. In such a system with quantum-classical coexistence, the optimal distribution of QKD requests with minimal deployment cost and power usage on the multiplexed links is challenging due to the diverse key rate demands of the requests, number of classical and quantum channels, guard band spacing between classical and quantum channels, and secret key rate of the quantum channels that decreases with distance. To address these challenges, in this work, we propose a Steiner tree-based approach for constructing a QCI that connects all quantum nodes with minimum TRNs. In addition, we propose a genetic algorithm-based solution to optimally distribute the end-to-end QKD requests over the QCI. We also determine feasible optical bypass routes to reduce the overall energy consumption in the network further. The proposed approach reduces the QCI deployment cost by 19.42% compared to the benchmark MST-Baseline. Also, on average, TAQNet with optical bypass achieves 4.69 kbit per Joule more energy efficiency compared to the nonbypass approach.
{"title":"TAQNet: Traffic-Aware Minimum-Cost Quantum Communication Network Planning","authors":"Ilora Maity;Junaid ur Rehman;Symeon Chatzinotas","doi":"10.1109/TQE.2024.3509019","DOIUrl":"https://doi.org/10.1109/TQE.2024.3509019","url":null,"abstract":"Quantum key distribution (QKD) provides a secure method to exchange encrypted information between two parties in a quantum communication infrastructure (QCI). The primary challenge in deploying a QCI is the cost of using optical fibers and trusted repeater nodes (TRNs). Practical systems combine quantum and classical channels on the same fiber to reduce the cost of fibers dedicated to QKD. In such a system with quantum-classical coexistence, the optimal distribution of QKD requests with minimal deployment cost and power usage on the multiplexed links is challenging due to the diverse key rate demands of the requests, number of classical and quantum channels, guard band spacing between classical and quantum channels, and secret key rate of the quantum channels that decreases with distance. To address these challenges, in this work, we propose a Steiner tree-based approach for constructing a QCI that connects all quantum nodes with minimum TRNs. In addition, we propose a genetic algorithm-based solution to optimally distribute the end-to-end QKD requests over the QCI. We also determine feasible optical bypass routes to reduce the overall energy consumption in the network further. The proposed approach reduces the QCI deployment cost by 19.42% compared to the benchmark MST-Baseline. Also, on average, TAQNet with optical bypass achieves 4.69 kbit per Joule more energy efficiency compared to the nonbypass approach.","PeriodicalId":100644,"journal":{"name":"IEEE Transactions on Quantum Engineering","volume":"6 ","pages":"1-16"},"PeriodicalIF":0.0,"publicationDate":"2024-11-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10771724","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142859137","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-27DOI: 10.1109/TQE.2024.3507155
Nishanth Chandra;Pradeep Kumar Krishnamurthy
In this article, we propose and experimentally demonstrate a novel synchronization method for quantum key distribution (QKD) systems. The method consists of maximizing the visibility of frequency-domain interference of optical sidebands about an optical carrier at the receiver node. The sidebands are generated by phase modulation of the optical carrier by an radio-frequency (RF) signal whose phase can be dynamically varied. The phase-variable RF signal is generated by the field-programmable gate array (FPGA) at the transmitter and the receiver using GTX transceivers. In order to facilitate this, we use square waveforms for RF signal instead of the conventional sinusoidal signals. We derive mathematical expressions for sideband power as a function of the phase difference between RF signals at transmitter and receiver. The phase is adjusted using dynamic phase shifter module, implemented by the FPGA. We propose a complete workflow that allows transmitter and receiver synchronization to within 12.6 ps directly over the quantum channel of QKD systems. Once synchronized, the same system can be switched over to quantum transmission by user-defined time delay. The workflow was implemented on a Xilinx Kintex-7 KC705 FPGA board. We studied the robustness of our technique by evaluating the stability of the interferometer over an operation of 10 min with standard deviation of interference to be less than 9% of the mean detection amplitude.
{"title":"FPGA-Based Synchronization of Frequency-Domain Interferometer for QKD","authors":"Nishanth Chandra;Pradeep Kumar Krishnamurthy","doi":"10.1109/TQE.2024.3507155","DOIUrl":"https://doi.org/10.1109/TQE.2024.3507155","url":null,"abstract":"In this article, we propose and experimentally demonstrate a novel synchronization method for quantum key distribution (QKD) systems. The method consists of maximizing the visibility of frequency-domain interference of optical sidebands about an optical carrier at the receiver node. The sidebands are generated by phase modulation of the optical carrier by an radio-frequency (RF) signal whose phase can be dynamically varied. The phase-variable RF signal is generated by the field-programmable gate array (FPGA) at the transmitter and the receiver using GTX transceivers. In order to facilitate this, we use square waveforms for RF signal instead of the conventional sinusoidal signals. We derive mathematical expressions for sideband power as a function of the phase difference between RF signals at transmitter and receiver. The phase is adjusted using dynamic phase shifter module, implemented by the FPGA. We propose a complete workflow that allows transmitter and receiver synchronization to within 12.6 ps directly over the quantum channel of QKD systems. Once synchronized, the same system can be switched over to quantum transmission by user-defined time delay. The workflow was implemented on a Xilinx Kintex-7 KC705 FPGA board. We studied the robustness of our technique by evaluating the stability of the interferometer over an operation of 10 min with standard deviation of interference to be less than 9% of the mean detection amplitude.","PeriodicalId":100644,"journal":{"name":"IEEE Transactions on Quantum Engineering","volume":"6 ","pages":"1-10"},"PeriodicalIF":0.0,"publicationDate":"2024-11-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10769019","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142825841","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-11-18DOI: 10.1109/TQE.2024.3501683
Miloš Prokop;Petros Wallden;David Joseph
Finding the shortest vector in a lattice is a problem that is believed to be hard both for classical and quantum computers. Many major postquantum secure cryptosystems base their security on the hardness of the shortest vector problem (SVP) (Moody, 2023). Finding the best classical, quantum, or hybrid classical–quantum algorithms for the SVP is necessary to select cryptosystem parameters that offer a sufficient level of security. Grover's search quantum algorithm provides a generic quadratic speedup, given access to an oracle implementing some function, which describes when a solution is found. In this article, we provide concrete implementation of such an oracle for the SVP. We define the circuit and evaluate costs in terms of the number of qubits, the number of gates, depth, and T-quantum cost. We then analyze how to combine Grover's quantum search for small SVP instances with state-of-the-art classical solvers that use well-known algorithms, such as the block Korkine Zolotorev (Schnorr and Euchner, 1994), where the former is used as a subroutine. This could enable solving larger instances of SVP with higher probability than classical state-of-the-art records, but still very far from posing any threat to cryptosystems being considered for standardization. Depending on the technology available, there is a spectrum of tradeoffs in creating this combination.
{"title":"Grover's Oracle for the Shortest Vector Problem and Its Application in Hybrid Classical–Quantum Solvers","authors":"Miloš Prokop;Petros Wallden;David Joseph","doi":"10.1109/TQE.2024.3501683","DOIUrl":"https://doi.org/10.1109/TQE.2024.3501683","url":null,"abstract":"Finding the shortest vector in a lattice is a problem that is believed to be hard both for classical and quantum computers. Many major postquantum secure cryptosystems base their security on the hardness of the shortest vector problem (SVP) (Moody, 2023). Finding the best classical, quantum, or hybrid classical–quantum algorithms for the SVP is necessary to select cryptosystem parameters that offer a sufficient level of security. Grover's search quantum algorithm provides a generic quadratic speedup, given access to an oracle implementing some function, which describes when a solution is found. In this article, we provide concrete implementation of such an oracle for the SVP. We define the circuit and evaluate costs in terms of the number of qubits, the number of gates, depth, and T-quantum cost. We then analyze how to combine Grover's quantum search for small SVP instances with state-of-the-art classical solvers that use well-known algorithms, such as the block Korkine Zolotorev (Schnorr and Euchner, 1994), where the former is used as a subroutine. This could enable solving larger instances of SVP with higher probability than classical state-of-the-art records, but still very far from posing any threat to cryptosystems being considered for standardization. Depending on the technology available, there is a spectrum of tradeoffs in creating this combination.","PeriodicalId":100644,"journal":{"name":"IEEE Transactions on Quantum Engineering","volume":"6 ","pages":"1-15"},"PeriodicalIF":0.0,"publicationDate":"2024-11-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10756628","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142825840","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-30DOI: 10.1109/TQE.2024.3488518
Jorge M. Ramirez;Elaine Wong;Caio Alves;Sarah Chehade;Ryan Bennink
This study investigates the frame potential and expressiveness of commutative quantum circuits. Based on the Fourier series representation of these circuits, we express quantum expectation and pairwise fidelity as characteristic functions of random variables, and we characterize expressiveness as the recurrence probability of a random walk on a lattice. A central outcome of our work includes formulas to approximate the frame potential and expressiveness for any commutative quantum circuit, underpinned by convergence theorems in the probability theory. We identify the lattice volume of the random walk as means to approximate expressiveness based on circuit architecture. In the specific case of commutative circuits involving Pauli- $Z$ rotations, we provide theoretical results relating expressiveness and circuit structure. Our probabilistic representation also provides means for bounding and approximately calculating the frame potential of a circuit through sampling methods.
{"title":"Expressiveness of Commutative Quantum Circuits: A Probabilistic Approach","authors":"Jorge M. Ramirez;Elaine Wong;Caio Alves;Sarah Chehade;Ryan Bennink","doi":"10.1109/TQE.2024.3488518","DOIUrl":"https://doi.org/10.1109/TQE.2024.3488518","url":null,"abstract":"This study investigates the frame potential and expressiveness of commutative quantum circuits. Based on the Fourier series representation of these circuits, we express quantum expectation and pairwise fidelity as characteristic functions of random variables, and we characterize expressiveness as the recurrence probability of a random walk on a lattice. A central outcome of our work includes formulas to approximate the frame potential and expressiveness for any commutative quantum circuit, underpinned by convergence theorems in the probability theory. We identify the lattice volume of the random walk as means to approximate expressiveness based on circuit architecture. In the specific case of commutative circuits involving Pauli-\u0000<inline-formula><tex-math>$Z$</tex-math></inline-formula>\u0000 rotations, we provide theoretical results relating expressiveness and circuit structure. Our probabilistic representation also provides means for bounding and approximately calculating the frame potential of a circuit through sampling methods.","PeriodicalId":100644,"journal":{"name":"IEEE Transactions on Quantum Engineering","volume":"5 ","pages":"1-15"},"PeriodicalIF":0.0,"publicationDate":"2024-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10738429","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142736338","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2024-10-25DOI: 10.1109/TQE.2024.3486546
Benjamin Gys;Lander Burgelman;Kristiaan De Greve;Georges Gielen;Francky Catthoor
The development of future full-scale quantum computers (QCs) not only comprises the design of good quality qubits, but also entails the design of classical complementary metal–oxide semiconductor (CMOS) control circuitry and optimized operation protocols. The construction and implementation of quantum error correction (QEC) protocols, necessary for correcting the errors that inevitably occur in the physical qubit layer, form a crucial step in this design process. The steadily rising numbers of qubits in a single system make the development of small-scale quantum architectures that are able to execute such protocols a pressing challenge. Similar to classical systems, optimized simulation tools can greatly improve the efficiency of the design process. We propose an automated simulation framework for the development of qubit microarchitectures, in which the effects of design choices in the physical qubit layer on the performance of QEC protocols can be evaluated, whereas the focus in the current state-of-the-art design tools only lies on the simulation of the individual quantum gates. The hybrid Hamiltonian framework introduces the innovative combination of a hybrid nature that allows to incorporate several levels throughout the QC stack, with optimized embedded solvers. This provides the level of detail required for an in-depth analysis of the QEC protocol's stability.
{"title":"Hybrid Hamiltonian Simulation Approach for the Analysis of Quantum Error Correction Protocol Robustness","authors":"Benjamin Gys;Lander Burgelman;Kristiaan De Greve;Georges Gielen;Francky Catthoor","doi":"10.1109/TQE.2024.3486546","DOIUrl":"https://doi.org/10.1109/TQE.2024.3486546","url":null,"abstract":"The development of future full-scale quantum computers (QCs) not only comprises the design of good quality qubits, but also entails the design of classical complementary metal–oxide semiconductor (CMOS) control circuitry and optimized operation protocols. The construction and implementation of quantum error correction (QEC) protocols, necessary for correcting the errors that inevitably occur in the physical qubit layer, form a crucial step in this design process. The steadily rising numbers of qubits in a single system make the development of small-scale quantum architectures that are able to execute such protocols a pressing challenge. Similar to classical systems, optimized simulation tools can greatly improve the efficiency of the design process. We propose an automated simulation framework for the development of qubit microarchitectures, in which the effects of design choices in the physical qubit layer on the performance of QEC protocols can be evaluated, whereas the focus in the current state-of-the-art design tools only lies on the simulation of the individual quantum gates. The hybrid Hamiltonian framework introduces the innovative combination of a hybrid nature that allows to incorporate several levels throughout the QC stack, with optimized embedded solvers. This provides the level of detail required for an in-depth analysis of the QEC protocol's stability.","PeriodicalId":100644,"journal":{"name":"IEEE Transactions on Quantum Engineering","volume":"5 ","pages":"1-11"},"PeriodicalIF":0.0,"publicationDate":"2024-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10735416","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"142691744","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"OA","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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