Interfaces in Computing最新文献

A comparison of hardware and software interfaces shows some differences between them; these differences may explain why it is harder to develop modular software than modular hardware.

A mathematical model of a software interface interconnection topology is developed to provide a better understanding of the mechanisms involved in modularization.

Polybus is a general purpose multiprocessor bus system which links modules such as processors, memories and input-output devices in a homogeneous way. It is a multiple common bus consisting of an arbitrary number of busses capable of independent operation. Connected modules, however, access the Polybus system like a single common bus. The multiple bus structure is user transparent, i.e busses may be added or removed without hardware or software modifications. The bus bandwidth can therefore be adjusted to actual requirements. Transfer speeds of up to n × 12 Mbytes s⁻¹ (where n is the number of busses used) can be achieved. Circuit switching through the bus system is managed by a decentralized arbiter which allows access according to priority as well as fair treatment of requests. Random assignment of busses to requests enables automatic by passing of faulty paths by re-try. Several addressing modes allow access to specific modules, to pools of modules or to an arbitrary member of a pool. This supports multiprocessor-transparent programming as well as data flow applications. In this paper an overview of the Polybus system, details of its operation and a comparison of some implementation details with other standard solutions are presented.

The objective of this paper is to discuss some hardware and software features of an experimental network of 8080 and 8085 microcomputers named Micronet. The interprocessor communication in the ring network is established using ring interfaces consisting of universal synchronous-asynchronous receivers-transmitters (USARTs). Another aspect considered is the interfacing of an 8080 microcomputer to a PDP-11/35 minicomputer and the development of the software for the microcomputer-minicomputer link which has been established over a serial line using the USART interface of the microcomputer and the DZ11 module of the minicomputer. This is useful in developing a host-satellite configuration of microcomputers and the minicomputer.

When computing systems that have connections to other systems are built, clearly defined interfaces between the various components are essential. The problems that arise when these systems are implemented before internationllly agreed standards on the interfaces exist are outlined. To illustrate this, an Ethernet local area network is considered as an example.

The MACE (modular access to computer equipment) is an intelligent front-end communications device designed to interface general-purpose computers to a high speed local area network (LAN). Considerable care has been taken to define external interfaces, both upper and lower, which are largely independent of the details of both the attached host computer system and the supporting communications techniques. The implementation described incorporates the necessary low level protocol handling in a combination of hardware and software for attachment to a slotted Cambridge Ring. The same techniques could, however, also be readily applied to interface to other LAN technologies. The principles of operation and design objectives are described, together with some details of the hardware and software implementation features which are combined to produce a general high performance communications facility.

Fundamental incompatibilities among entity representations greatly complicate data base interchange between computer-assisted design-computer-assisted manufacture (CAD-CAM) systems. Even simple geometric entities, such as circular arcs, are represented by incompatible forms in many systems. To preserve the original intent of a CAD-CAM data base, the treatment of these incompatible representations in initial graphics exchange specification (IGES) processors must be carefully specified and verified. The challenge of IGES processor design is to meet these specifications within the framework of current IGES and CAD-CAM system architecture.

As a first stage in an investigation into improved serial data transmission, experiments have been carried out on an asynchronous system in which several frames are packaged into a “superframe”. The superframe contains message, synchronization and cyclic redundancy information. Simulations have shown that long superframes are better at low error rates, and short superframes at high rates. A cyclic redundancy check (CRC) of degree 14 gives very good security against undetected error. Alternative methods of start-bit detection had little effect. The system appears to be suitable as the basis of an adaptive method of communication, in which the superframe length and the CRC degree could be subject to closed-loop control.

Programming languages tend to be more and more frequently interpreted rather than compiled. This is mainly because hardware is becoming cheaper and newer hardware with a still higher degree of complexity is rapidly appearing.

The well-known separation of interpretation and execution is used together with an intermediate code to present a technique which achieves an important improvement in program execution speed. The solution given involves a highly interactive multiprocessor with extremely short parallel processes. A pipelining system at the level of the intermediate code together with a first-in first-out queuing buffer is used.

Our proposal amounts to combining a set of microprocessors into a multiprocessor system. The set consists of an interpretation processor and one or more execution processors. The execution processors run a code that is free of jumps. The performance thus reaches the level of compiled code. No restriction on intermediate codes is made. However, a complex an powerful code that is not storage consuming will generally speed up the type of machine presented.

The machine architecture together with the technological possibilities and the realization of the machine are emphasized in this paper.