Interfaces in Computing最新文献

The Computing Division at the Los Alamos National Laboratory has designed and is building a parallel microprocessor system (PμPS) to serve as a research tool for evaluating parallel processing of large-scale scientific codes. The PμPS is an experimental architecture consisting of an orthogonal array of 20 processing elements by 32 memory elements, establishing a tightly coupled shared memory (16-Mbyte) machine. The hardware incorporates very-large-scale integration components, such as 16-bit microprocessors, floating-point co-processors and dynamic random access memories. The design replaces the conventional medium-scale integration or small-scale integration circuitry with programmable array logic, logic sequencers and logic arrays. This experimental system, which is only one element of the parallel processing research being done by the Laboratory's Computing Division, will enable direct comparisons of speed-ups of algorithms for a variety of multiprocessor architectures.

In this paper the interfacing of a CAMAC system to a PDP-11/45 running UNIX version 7 is described. The main emphasis of the paper is to describe the CAMAC device driver for UNIX and to illustrate the advantages of programming the driver in the high level language C as compared with programming in assembler. It is assumed that the readership is primarily from a hardware background, and therefore we summarize some of the background and history of the UNIX system.

A design for a low speed simple-to-build analogue-to-digital converter peripheral circuit is described. Portability between as many different main computers as possible is achieved by using a serial communication port. An 8748 single-chip microcomputer chip is used to give versatility and hardware independence to the design while at the same time retaining a simple circuit. Two analogue inputs are provided, digitized to a resolution of 12 bits, while a real-time clock is included on the basis that expired time is very frequently needed in data-logging work.

At Strathclyde University we have a dual local area network configuration consisting of a commercial Cambridge Ring and an Ethernet-style network called Strathnet designed and built in the Department of Computer Science. The majority of the hosts in our dual configuration are PDP-11 and LSI-11 computers.

With these networks we are investigating the comparative performances of each and investigating the architectures and protocols of local networks in general. One of our chief interests is in designing “access units” by means of which computers, terminals and other devices are interfaced to local network communication media.

In this paper our dual network configuration is outlined, our approach to building a general-purpose network access unit is explained and a description is given of how we at present interface the PDP-11 and LSI-11 computers to both networks.

VME is a new high performance standard bus for multimicoprocessor systems. Its characteristics originate in the 68000 microprocessor's interface signals. Processors with other interface characteristics can, however, also be used in VME systems. The case study of the interfacing of a 6809-based subsystem to the VME bus is presented. A mixture of hardware and software has been used to implement at low cost the matching functions. The 6809-based subsystem can perform all VME-related functions: bus requester in multiprocessor environments, bus master, interrupt handler, bus slave and interrupter. The last two functions are performed by a dual-port memory included in the subsystem, which is designed to be used as the main processor in small VME systems or as the intelligent peripheral controller in larger VME systems.

A hierarchical local area network architecture is proposed for laboratory process control automation. Coaxial cables are used as communication media and the control of access is totally distributed. Two different arbitration algorithms are implemented in the experimental networks: the first works on a modified algorithm for carrier sense multiple access with collision detection, while the second realizes a low level fast token-passing method. Both arbitration algorithms as well as the logical link control will be described briefly in the paper. Only a connection-oriented logical link service is available. The contention-free multiframe control sequences supported by the physical layer provide a facility to implement a selective flow control, which is applied independently for each logical link.

In this paper an analogue data acquisition device, which is multiprocessor oriente, is described; using parallel transfer structures and direct access in private memories, the system involves a specific analogue-to-digital converter. The design and operation of the system are optimized so as to increase the acquisition rate for various numbers of channels and word lengths. One of the processors leads the conversion and interfaces, without reducing the availability of the other processors. The prototype of the device has been working in a hybrid simulation computer with the predicted efficiency.

The JNT-PAD is a packet assembly-diassembly facility capable of connecting up to 16 asynchronous terminals to an X.25-based wide area network. A variant has also been developed for connection to a Cambridge Ring local area network. These units form the basis of a range of internetworking products such as bridges and gateways, connecting between dissimilar networks via a network-independent transport service.